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Thesis Report

EVA2 Calibration

Author: Gefei Zhu

Institution: HZ University of Applied Sciences Company: NXP Semiconductors N.V.

Date:6/5/2021

Version: 1.0

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Thesis Report

EVA2 Calibration

Author: Gefei Zhu

Student number: 00082748 Contact number: +310683406957 Email address: zhu0025@hz.nl Program: Mechatronic engineering

Organization: HZ University of Applied Sciences Company: NXP Semiconductors N.V.

In-company 1st mentor: John van Zwam

In-company 2nd mentor: Brecia Nurastu Sasongko 1st examiner: Peter van der Heide

2nd examiner: L.M. Blok

Place & date: Nijmegen, 6th of May, 2021 Version: 1.0

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Summary

Aiming at analyzing the failed products of NXP semiconductors, the company utilizes a test setup called EVA2 bench test platform. The EVA2 bench test platform is required maintenance and one of the requirements of a tester is calibration. In order to ensure the accuracy of the test, NXP is only allowed to effectively calibrated measurement equipment. The calibration is to check if the tool is still measuring within the specification and the failed parts or the whole tools will be calibrated or replaced. Hence, a project called “EVA2 calibration” is established to

designed and make a device to calibrate the EVA2 setup.

This thesis report describes the design of the EVA2 calibration device. In this thesis, the background of the whole project will be first introduced. And then, the theoretical framework which is built up based on the research and problems analyzing will be depicted thoroughly.

The main question which is included in the theoretical framework is: What is the design of a calibration device which can check if the EVA’s test tools meet the specification, can be operated by a software and return the results via a graphical user interface (GUI)?

The main method to guide the whole project is the V-model method. The V-model contains two major phases: design and integration, each containing several subphases. The activities and deliverables of each phase are described clearly.

After that, the results will be depicted on the basis of the V-model method. The system is divided into six subsystems, including ADC calibration subsystem, DAC calibration subsystem, PowerIO calibration subsystem, JTAG calibration subsystem, Oscilloscope calibration subsystem and AFG calibration subsystem. The design phases of each subsystem will be described clearly, and the following part would be the description of the system integration.

Finally, the results discussion, conclusions and recommendations of this project will be shown in the last phase. The results discussion focuses on the fault tolerance and error range set for the EVA2 calibration device. Moreover, the conclusions of whole design are depicted in the following phase. Last, the recommendation for this design is drawn for the feature using and design of the EVA2 calibration device.

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Foreword

Thanks to having the internship in NXP for five months with a learning attitude at the very beginning, I have learned a lot not only about the academic knowledge but also the skills of solving the problem systematically.

My project is to design a EVA2 calibration device which requires software knowledge, hardware knowledge and programming knowledge. There are two software used in this project. By designing the PCBs of EVA2 calibration device, I have learnt how to use the Altium Designer to draw the schematic symbols of each components and design the schematics and how to put all the components in a PCB plane logically and correctly. The programming part is based on the schematics to realize and control the PCBs. During this period, I have learnt how to use Delphi 10.3 and Pascal, the programming language, to program the device with target function and design a GUI. For the hardware knowledge, I have obtained lots of microelectronics knowledge when designing the schematics of the calibration device.

Hereby, I would like to express my appreciation to all my in-company and in-school tutors. My in-company tutors provided not only the academic help but also built up a relaxed and pleasant working environment for me; my in-school tutor helped me a lot when I was trapped in writing the report. Without their help, I will never accomplish the project so successfully.

Gefei Zhu Nijmegen, The Netherlands 5-6-2021

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General abbreviation

Abbreviation Full name

SMU Source Measurement Unit

JTAG Joint Test Action Group

TMU Time Measurement Unit

ADC Analog to Digital Converter

DAC Digital to Analog Converter

IVN In-Vehicle Networking

PCB Printed Circuit Board

CAN Controller Area Network

LIN Local Interconnect Network

GUI Graphical User Interface

TSSOP Thin Shrink Small Outline Package

SPI Serial Peripheral Interface

AFG Arbitrary Function Generator

𝐈𝟐𝐂 Inter-Integrated Circuit

AM Amplitude Modulation

FM Frequency Modulation

PM Phase Modulation

FSK Frequency-Shift Keying

SUM Sum Modulation

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Content

Summary ... iii

Foreword ... iv

General abbreviation ... v

Table of figures ... ix

Table of tables ... xi

Chapter 1 Introduction ... 1

1.1 Background ... 1

1.1.1 Company Background ... 1

1.1.2 Assignment background ... 1

1.2 Problem analysis ... 3

1.2.1 Present situation ... 3

1.2.2 Desired situation ... 4

1.3 Research questions ... 4

1.3.1 Main question ... 4

1.3.2 Sub questions ... 4

1.4 Research objectives ... 4

Chapter 2 Theoretical framework ... 5

2.1 EVA’s measurement tools and specification ... 5

2.1.1 ADC/DAC ... 5

2.1.2 TMU/Oscilloscope ... 7

2.1.3 JTAG board ... 8

2.1.4 Power IO module ... 9

2.1.5 AFG ... 10

2.2 PCB design ... 11

2.3 GUI design ... 13

Chapter 3 Method ... 14

3.1 Overview of V-model methodology ... 14

3.2 Phases of V-model ... 14

Chapter 4 Results ... 16

4.1 Requirements phase ... 16

4.2 System design phase ... 17

4.2.1 System description ... 17

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4.2.2 System validation plan ... 18

4.3 Subsystem design phase ... 18

4.3.1 ADC and DAC calibration subsystems ... 19

4.3.2 PowerIO calibration subsystem ... 24

4.3.3 JTAG calibration subsystem ... 28

4.3.4 Oscilloscope and AFG calibration subsystems ... 31

4.4 System integration ... 37

4.4.1 Overall PCB design ... 37

4.4.2 Integration of GUI design ... 37

Chapter 5 Discussion ... 38

5.1 Result discussion ... 38

5.2 Method discussion ... 39

5.3 Conclusions & recommendations ... 39

References ... 1

Appendix I Test Plan ... 3

1. EVA2’s function check plan ... 3

2. System verification plan ... 8

3. Subsystems – ADC calibration ... 9

4. Subsystems – DAC calibration ... 12

5. Subsystems – PowerIO calibration... 16

6. Subsystems – JTAG calibration ... 20

7. Subsystem – Oscilloscope calibration ... 23

8. Subsystem – AFG calibration ... 26

Appendix II PCB Schematics ... 29

1. Integration sheet ... 29

2. Connector A ... 30

3. Connector B ... 30

4. Connector C... 31

5. Connector D ... 31

6. Connector E ... 32

7. Connector F ... 32

8. JTAG subsystem ... 33

9. Oscilloscope and AFG subsystems ... 34

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viii

Appendix III The logic table for multiplexers ... 35

1. 74HC4067DB ... 35

2. 74HC4066 ... 35

Appendix IV PCB layout ... 37

Appendix V The logic diagrams for GUI design ... 38

1. Logic diagram for ADC subsystem ... 38

2. Logic diagram of DAC subsystem ... 39

3. Logic diagram of PowerIO subsystem ... 40

4. Logic diagram of JTAG subsystem ... 41

5. Logic diagram of AFG subsystem ... 42

6. Logic diagram of Oscilloscope subsystem ... 42

7. Logic diagram of main GUI design ... 43

Appendix VI User Manual (GUI design)... 44

1. ADC and DAC subsystems ... 44

2. PowerIO subsystem ... 45

3. JTAG subsystem ... 46

4. Oscilloscope and AFG subsystems ... 47

Appendix VII Test Results ... 50

1. EVA2’s function check results ... 50

2. System verification test results ... 52

3. Subsystems – ADC calibration test results ... 52

4. Subsystems – DAC calibration test results ... 53

5. Subsystems – PowerIO calibration test results ... 54

6. Subsystems – JTAG calibration test results ... 55

7. Subsystems – Oscilloscope calibration test results... 56

8. Subsystems – AFG calibration test results ... 57

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Table of figures

Figure 1-1 EVA2's motherboard, daughter board and adapter board ... 1

Figure 1-2 EVA2's hardware cabinet ... 2

Figure 1-3 Block schematic of EVA2 bench test platform ... 2

Figure 1-4 The module board for connecting functional boards with PC ... 3

Figure 2-1 EVA2’s ADC module schematics (NXP, Schematics of EVA2's ADC module, 2020) ... 5

Figure 2-2 EVA2’s DAC module schematics (NXP, Schematic of EVA2's DAC module, 2020) ... 6

Figure 2-3 Single DAC Channel Architecture ... 7

Figure 2-4 The schematics of JTAG Board (NXP, Schematic of EVA2's JTAG board, 2020) ... 8

Figure 2-5 The Logic Diagram of the supply transceivers (Instruments, 2007) ... 9

Figure 2-6 The schematics of EVA2's PowerIO module (NXP, Schematics of EVA2's PowerIO module, 2020) ... 9

Figure 2-7 The schematics of ULN2903 (elprocus, 2020) ... 10

Figure 2-8 The AFG which is not calibrated ... 10

Figure 2-9 The Active Bar ... 11

Figure 2-10 Complete design flow ... 11

Figure 2-11 The Libraries... 11

Figure 2-12 The interfaces of Delphi10.3 ... 13

Figure 3-1 The overview of V-model (Kwekkeboom, 2019) ... 14

Figure 4-1 System description ... 17

Figure 4-2 EVA2 calibration subsystem integration diagram ... 18

Figure 4-3 The inputs and outputs of the ADC/DAC subsystems ... 20

Figure 4-4 Hardware integration for ADC/DAC subsystems ... 21

Figure 4-5 Schematic of partial connector E ... 22

Figure 4-6 Schematics of connector A ... 22

Figure 4-7 Schematic of the analog switch (DAC subsystem) ... 23

Figure 4-8 Schematic of the analog switch (ADC subsystem) ... 23

Figure 4-9 Schematic of PCA9555 part ... 23

Figure 4-10 The inputs and outputs of PowerIO subsystem ... 25

Figure 4-11 Voltage measurement analysis of PowerIO subsystem... 25

Figure 4-12 The calculation process of Vmeasurement(ref) ... 26

Figure 4-13 Hardware integration for PowerIO subsystem ... 26

Figure 4-14 Partial schematic of connector A ... 27

Figure 4-15 Schematic of the analog switch (PowerIO subsystem) ... 27

Figure 4-16 Schematic of the SN74LVC2T45 on the JTAG board ... 28

Figure 4-17 The inputs and outputs of JTAG subsystem... 28

Figure 4-18 The logic diagram of hardware design (JTAG subsystem) ... 29

Figure 4-19 Schematic of header on the JTAG board ... 29

Figure 4-20 Schematic of analog multiplexer (JTAG subsystem) ... 30

Figure 4-21 Schematic of header 5X2 ... 30

Figure 4-22 Partial schematic of main sheet ... 30

Figure 4-23 The inputs and outputs of Oscilloscope and AFG subsystems ... 32

Figure 4-24 The logic diagram of the oscilloscope subsystem ... 33

Figure 4-25 The logic diagram of the AFG subsystem... 33

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Figure 4-26 Schematic of the oscillator ... 35

Figure 4-27 Schematic of the binary ripple counter ... 35

Figure 4-28 Schematic of analog multiplexers (oscilloscope subsystem) ... 35

Figure 4-29 Schematic of analog multiplexers (AFG subsystem) ... 36

Figure 4-30 The main GUI design ... 37

Figure 2-1 schematic of integration sheet ... 29

Figure 2-2 schematic of connector A ... 30

Figure 2-3 schematic of connector B ... 30

Figure 2-4 schematic of connector C ... 31

Figure 2-5 schematic of connector D ... 31

Figure 2-6 schematic of connector E... 32

Figure 2-7 schematic of connector F ... 32

Figure 2-8 schematic of JTAG subsystem ... 33

Figure 2-9 Schematic of oscilloscope and AFG subsystems ... 34

Figure 3-1 Logic table of 74HC4067DB (Nexperia, 74HC4067DB, 2021) ... 35

Figure 3-2 Logic table of 74HC4066 (Nexperia, 74HC4066; 74HCT4066, 2020) ... 35

Figure 3-3 Logic table of 74HC4051 (Nexpiria, 2017) ... 36

Figure 3-4 Logic table of MAX14757EUET (Maximintegrated, 2021) ... 36

Figure 5-1Logic diagram of ADC subsystem ... 38

Figure 5-2 Logic diagram of DAC subsystems ... 39

Figure 5-3 Logic diagram of PowerIO subsystem ... 40

Figure 5-4 Logic diagram of JTAG subsystem ... 41

Figure 5-5 Logic diagram of AFG subsystem ... 42

Figure 5-6 Logic diagram of Oscilloscope subsystem... 42

Figure 5-7 The logic diagram of the main GUI design ... 43

Figure 7-1 ADC modules 1.25 V test results ... 50

Figure 7-2 ADC modules 4 V test results ... 50

Figure 7-3 DAC modules 1 V test results ... 51

Figure 7-4 DAC modules 4 V test results ... 51

Figure 7-5 PowerIO modules test results ... 51

Figure 7-6 Power supply test results ... 52

Figure 7-7 ADC calibration all channels test results... 52

Figure 7-8 ADC calibration one channel test result ... 53

Figure 7-9 DAC calibration all channels test results... 53

Figure 7-10 DAC calibration one channel test result ... 53

Figure 7-11 PowerIO calibration all channels test results ... 54

Figure 7-12 PowerIO calibration one channel test result ... 54

Figure 7-13 JTAG calibration TDI channel test result ... 55

Figure 7-14 JTAG calibration TCK channel test result ... 55

Figure 7-15 JTAG calibration TMS channel test result ... 55

Figure 7-16 JTAG calibration TDO channel test result ... 56

Figure 7-17 Test result of opening Picoscope Software ... 57

Figure 7-18 Input signal from AFG ... 57

Figure 7-19 AFG test results in Picoscope software... 57

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xi

*All the figures from references are inserted citations.

Table of tables

Table 2-1 The specification of ADC ... 6

Table 2-2 The specification of DAC (Analog Devices, AD5308/AD5318/AD5328 Data sheet, 2002) ... 7

Table 2-3 The specifications of PicoScope 2406B (Pico®Technology, PicoScope®2000 series) ... 7

Table 2-4 The specifications of PicoScope 5444D (Pico®Technology, PicoScope®5000D Series) ... 8

Table 2-5 The specifications of supply transceivers (Instruments, 2007)... 9

Table 2-6 The specification of Power IO (elprocus, 2020) ... 10

Table 2-7 The specifications of AFG-2225 (Good Will Instrument Co.) ... 11

Table 3-1 Phases, activities and deliverables of V-model ... 15

Table 4-1 The requirements of the ADC and DAC subsystems ... 19

Table 4-2 The list of components for ADC/DAC subsystem ... 21

Table 4-3 The list of components for PowerIO subsystem ... 26

Table 4-4 The list of components for JTAG subsystem ... 29

Table 4-5 The requirements of oscilloscope and AFG subsystems ... 31

Table 4-6 The list of components for oscilloscope/AFG subsystem ... 34

Table 5-1 Each subsystem's margin of errors ... 39

Table 1-1 EVA2 function checker plan's average bandwidth of reactions ... 4

Table 1-2 System verification's average bandwidth of reactions ... 9

Table 1-3 ADC calibration subsystem's average bandwidth of reactions ... 10

Table 1-4 DAC calibration subsystem's average bandwidth of reactions ... 14

Table 1-5 PowerIO calibration subsystem's average bandwidth of reactions ... 17

Table 1-6 JTAG calibration subsystem's average bandwidth of reactions ... 21

Table 1-7 Oscilloscope calibration subsystem's average bandwidth of reactions ... 25

Table 1-8 AFG calibration subsystem's average bandwidth of reactions ... 27

Table 7-1 System verification test results ... 52

Table 7-2 Input signal test results of Oscilloscope calibration test results ... 56

Table 7-3 Channels' test results of Oscilloscope calibration test results ... 56

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Chapter 1 Introduction

In chapter 1, firstly, the background of this project will be described. Secondly, a list of research questions will be introduced. Finally, there will be an analysis of the research objective.

1.1 Background

In 1.1, the company background will be briefly introduced, followed by the introduction of assignment background. Afterwards, there will be a project overview which involves a graph to show the structure of the project.

1.1.1 Company Background

NXP Semiconductors N.V. is one of the top ten semiconductor companies in the world. The company was founded in 2006 as the semiconductor division of Philips AG, headquartered in Eindhoven, the Netherlands, which was established in 1953. From the beginning of NXP's independence, CEO Richard Clemmer and the management team established the company's strategy to develop market-leading, highly differentiated businesses and generate profits. In 2015, NXP merged with Freescale, another leading semiconductor company, to further expand its business on the Internet of Things and automotive, with a focus on secure and reliable edge computing, connectivity technology, and efficient power management solutions. And established market leadership positions in key areas such as next-generation electric vehicles, and secure connectivity across the Internet of Things, mobile devices, and automotive ecosystems.

NXP's products are widely used, covering the market and application fields of secure connected vehicles, mobile devices, industrial Internet of Things, smart city, smart home, communication infrastructure and so on. Moreover, NXP has operations in more than 25 countries now.

1.1.2 Assignment background

NXP semiconductors automotive business line produces chips for IVN which must reach the quality inspection, like temperature tolerance and anti-interference ability, before entering the market. Even under such circumstances, some devices will still fail at a low rate which is lower

Figure 1-1 EVA2's motherboard, daughter board and adapter board

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2 than 0.1 ppm (parts per million) and be sent back to NXP. In order to analyze the failed

products like curve tracing tests, NXP utilizes a test setup called EVA2 bench test platform.

The EVA2 has three main constructions: a motherboard (the green square) and a daughter board (the red square) as shown in the Fig.1.1, a hardware cabinet as shown in the Fig.1.2.

The EVA2 has an embedded Windows PC which takes the charge of controlling the

motherboard. And the motherboard has 96 pins which can be inserted by the daughter board so that the curve tracing test which has been mentioned above can be controlled by the PC through daughter board. Moreover, aiming at analyzing different failed products, an adapter board as the yellow square which is shown in the Fig.1-1 is required to connect all the pins of the chips.

The block schematic of EVA2 bench test platform is shown in the Fig.1-3.

Figure 1-2 EVA2's hardware cabinet

Figure 1-3 Block schematic of EVA2 bench test platform

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3 The hardware cabinet contains 5 functional boards: power input/output (IO), Joint test action group (JTAG), analog to digital converter (ADC), digital to analog converter (DAC), time

measurement unit (TMU). All the boards are inserted on a module board as shown in the Fig 1- 4 which connects the PC with all the functional boards. Furthermore, the embedded

oscilloscopes connect to the PC through USB interface and CAN/LIN connect to PC through CAN/LIN controller. Last, the source measurement unit is connected to the motherboard to provide source voltage or current and simultaneously measure voltage and/or current. The detailed explanation of the components will be clarified in Chapter 2. And the whole setup is controlled by software written in Delphi XE7 which is a windows-based object-oriented programming tool.

The EVA2 tester is required maintenance and one of the requirements of a tester is calibration.

In order to ensure the accuracy of test, NXP is only allowed to use the measuring equipment that has a valid calibration. The calibration is to check if the tool is still measuring within the specification and the failed parts or the whole tools will be calibrated or replaced.

1.2 Problem analysis

In 1.2, the problem analysis will be clarified, including the analysis of the present situation and expectations. Moreover, the requirements of customers will be listed.

1.2.1 Present situation

As what has been mentioned in 1.1.2 Assignment background, EVA2 has several tools like TMU, ADC, DAC, JTAG board and Power IO module which are required to be calibrated. The

uncalibrated tools will give the wrong measurement results and might damage the device.

Normally, a calibration is valid for a year and the tools are necessary to be sent back for calibration from all over the world to the Netherlands. Under such circumstances, the calibration will waste lots of transportation costs and time.

Figure 1-4 The module board for connecting functional boards with PC

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1.2.2 Desired situation

Hence, a calibration device which can be inserted into EVA2’s motherboard through the 96 pins is in demand. This device will check whether all the tools meet their specification and the check will be accomplished to compare the measurement results with valid calibrated equipment to check if the value is correct. Last, if EVA2 is failing, then the calibration and/or repairment will be executed by the specialist. The required device is able to prevent the EVA2 from out of specification. The calibration device will ensure the accuracy of the EVA2’s test results and increase its flexibility. Most importantly, the embedded calibration device will save lots of transportation time and safe costs of both transportation and calibration.

1.3 Research questions

In 1.2, the main question will be illustrated, and the sub questions are related to the main questions. And all the questions are led by 1.2 Problem Analysis.

1.3.1 Main question

What is the design of a calibration device which can check if the EVA’s test tools meet the specification, can be operated by a software and return the results via a graphical user interface (GUI)?

1.3.2 Sub questions

1. What are the specifications of each EVA2’s measurement tools?

2. What are the rough block designs for the calibration tasks?

3. What are the suitable Printed Circuit Board (PCB) designs for each measurement tools’

calibration task?

4. What is the best design to combine each designed calibration device into one PCB board?

5. What software with GUI could be designed to operate the calibration device and return the results?

6. What kind of test can be done to make sure the designed calibration device’s testing results are equal to the valid calibrated equipment’s?

1.4 Research objectives

In sum, the objective of this project is to design a calibration device with a software, and which can check if all the EVA2’s measurement tools are meeting the specification. The users can utilize the device to calibrate the EVA2 more conveniently and don’t need to send EVA2 back to the NXP for yearly calibration. With the calibration device, which is inserted into the EVA2, the NXP can reduce the costs and both the calibration and transportation time.

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Chapter 2 Theoretical framework

In this chapter, the theoretical framework will be depicted. The theoretical framework is providing a fundamental context of facts and knowledge to further refine the statement of the research problem.

2.1 EVA’s measurement tools and specification

Because the project is based on EVA2’s tools and boards, including ADC, DAC, TMU, JTAG board, Power IO module, AFG, the functions of those tools should be researched and

elaborated. Besides, the ADC and DAC measurement tools are analogous and expounded in one part. Moreover, each measurement tool has its own specification which is an important

element for calibration and is required to do research.

2.1.1 ADC/DAC

ADC (digital-to-analog converter) and DAC (analog-to-digital converter) are systems which can convert a digital signal to analog signal or convert an analog signal to digital analog. ADC function board performs as input source for EVA setup. It can generate 96 channels of digital voltage ranging from 0 – 5V which can be defined by users (Zheng, 2018). And the DAC function board is to analog voltage ranging from 0 – 5V.

EVA2 utilizes AD7927 and AD5328 as the analog devices which are a combination of both analog machine and analog media that can together measure, record, reproduce, or broadcast continuous information (Wikipedia, Analog device, 2020).

Figure 2-1 EVA2’s ADC module schematics (NXP, Schematics of EVA2's ADC module, 2020)

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6 AD7927 is a 12-bit, high speed, low power, 8-channel, SAR (successive approximation) ADC as shown in the Fig.2-1 (Analog Devices, AD7927 Data sheet, 2003). And, AD5328 is an octal 12-bit buffered voltage output DAC in a 16-lead TSSOP (Thin shrink small outline package) as shown in the Fig.2-2.

The ADC has two phases, the acquisition phase and the conversion phase. The ADC is comprised of control logic, SAR (Successive-approximation-register), and a capacitive DAC that are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition.

And the calibration device is required to measure these parameters when the user gives the command to test if the measure values are in their specifications. If not, the calibration device will calibrate it, or some components will be replaced. The specification of the ADC will be shown in the table 2-1 (Analog Devices, AD7927 Data sheet, 2003).

AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V;

Table 2-1 The specification of ADC

Parameter Min Max Unit Test Conditions/Comments Analog Input

Input Voltage Ranges

0 REFIN V RANGE bit set to 1

0 2 × REFIN V RANGE bit set to 0, AVDD / VDRIVE = 4.75 V to 5.25 V

Figure 2-2 EVA2’s DAC module schematics (NXP, Schematic of EVA2's DAC module, 2020)

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7 For the DAC, the architecture of one DAC channel consists of a resistor string DAC followed by an output buffer amplifier. The voltage at the VREF pin provides the reference voltage for the corresponding DAC. Fig. 2-3 shows a block diagram of the DAC architecture (Analog Devices, AD5308/AD5318/AD5328 Data sheet, 2002).

(Analog Devices, AD5308/AD5318/AD5328 Data sheet, 2002) The specification of the DAC will be shown in the table 2-2.

VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND;

Temperature range (A, B version): −40°C to +125°C; typical at 25°C.

Table 2-2 The specification of DAC (Analog Devices, AD5308/AD5318/AD5328 Data sheet, 2002) Parameters A Version

MIN Typ Max

B Version

MIN Typ Max

Unit Conditions/Comments

DAC Reference Input VREF Input

Range

1.0 VDD 1.0 VDD V Buffered reference mode

0.25 VDD 0.25 VDD V Unbuffered reference

mode

2.1.2 TMU/Oscilloscope

TMU (Time Measurement Unit) is an EVA application that can measure the time difference between two signals or between two transients of one signal (Zwam, 2017). But for the EVA2, NXP has utilized two oscilloscopes called PicoScope 2406B and PicoScope 5444D, to measure the time and to get rid of the TMU device. The specifications of the PicoScope 2406B and the PicoScope 5444D will be shown in the Table.2-3 and 2-4.

Table 2-3 The specifications of PicoScope 2406B (Pico®Technology, PicoScope®2000 series)

Parameters Value Unit

Time base

Longest timebase 5000 s/div

Shortest timebase 2 ns/div

Max waveforms per second 8000 Amplitude

Input ranges ±20 m, ±50 m, ±100 m, ±200 m, ±500 m, ±1, ±2, ±5, ±10, ±20

V Figure 2-3 Single DAC Channel Architecture

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8 Analog offset range (vertical

position adjustment)

±250 m (20 m to 200 m ranges) ±2.5 (500 m to 2 ranges) ±25 (5 to 20 ranges)

V

Analog offset control accuracy ±1% of offset setting, additional to basic DC accuracy

Table 2-4 The specifications of PicoScope 5444D (Pico®Technology, PicoScope®5000D Series)

Parameters Value Unit

Time base (1 ns/div to 5000 s/div in 39 ranges)

Longest timebase 100 ps/div

Amplitude

Input ranges ±10 m to ±20 full scale, in 11 ranges

V Analog offset range

(vertical position adjustment)

±250 m (10, 20, 50, 100, 200 m ranges)

±2.5 (500 m, 1, 2 ranges) ±20 V (5, 10, 20 ranges)

V

Analog offset control accuracy

±0.5% of offset setting, additional to basic DC offset accuracy

2.1.3 JTAG board

JTAG (Joint Test Action Group) board is a functional board for motherboard supply. As what is shown in the Fig.2-4, the board concludes 96 pins to connect with the motherboard, two FPGA (Field-Programmable Gate Array) modules, a header and 5 dual supply transceivers with configurable voltage-level shifting.

Figure 2-4 The schematics of JTAG Board (NXP, Schematic of EVA2's JTAG board, 2020)

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9 The 4 dual supply transceivers called SN74LVC2T45 are used for asynchronous communication between two data buses.

This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port shown in the Fig.2-5 is designed to track VCCA. VCCA accepts any supply voltage from 1.5 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.5 V to 5.5 V.

This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes (Instruments, 2007).

Hence, if the voltage is under the absolute maximum ratings may cause permanent damage to the device which is required to be calibrated. The specifications of those supply transceivers will be depicted in the Table.2-5. However, the VCCA is supplied by SMU which is calibrated while VCCB is supplied by DAC which is required to be calibrated.

Table 2-5 The specifications of supply transceivers(Instruments, 2007)

Parameters Min Max Unit

VCCA supply voltage range 1.5 5.5 V

VCCB supply voltage range 1.5 5.5 V

2.1.4 Power IO module

Power IO module with 96 channels is inserted in the backplane of the EVA2’s motherboard. It takes charge of controlling relays and communicating with PC through I2C. As what has shown in the schematics of PowerIO module, it includes PCA9555, ULN2803 and 24AA512.

The PCA9555 is a 24-pin CMOS (Complementary metal–oxide–semiconductor) device that provides 16 bits of GPIO (General Purpose parallel Input/Output) expansion for I2C-bus I/O Figure 2-5 The Logic Diagram of the

supply transceivers (Instruments, 2007)

Figure 2-6 The schematics of EVA2's PowerIO module (NXP, Schematics of EVA2's PowerIO module, 2020)

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10 expanders (NXP, 2017). The ULN2803 is high-voltage, high-current Darlington drivers comprised of eight NPN Darlington pairs. It plays the role of controlling the relays and the schematics is

shown in Fig. 2-6.

The Darlington transistor pair circuit shown in the Fig.2-7 consists of two transistors. The emitter of the input transistor is connected to the base terminal of the output transistor, base and collectors of these transistors are wired together.

Therefore, the current that is amplified by the first transistor then by the second transistor (elprocus, 2020). The collector- emitter saturation voltage decides the worst condition of the circuitry and is required to be calibrated.

Table 2-6 The specification of Power IO (elprocus, 2020)

Parameter Symbol Test condition Typical value Maximum value Unit Collector-

Emitter saturation voltage

V CE(SAT) I c=350mA, I IN=500𝜇𝐴 I c=200mA, I IN=350𝜇𝐴 I c=100mA, I IN=250𝜇𝐴

1.3 1.1 0.9

1.6 1.3 1.1

V

2.1.5 AFG

An arbitrary waveform generator (AFG) is a piece of electronic test equipment used to generate electrical waveforms (Wikipedia, arbitrary waveform generator, 2020).

EVA2 utilizes the AFG-2225, shown in the Fig.2-8, as analog signal sources which are not calibrated yet. The “uncalibrated” sign is posted on it. AFG-2225 has the functions of AM/FM/PM/FSK/SUM modulation, scanning, burst and frequency counter, which can be applied to various communication fields. The USB host and device interface are equipped with the function of linking the AFG-2225 with other devices, thus providing a more flexible

waveform generation function, which can be used for more practical purposes. By linking to the GW Instek GDS series digital storage oscilloscope (DSO), the waveform of interest can be

captured and reconstructed. Users can also use arbitrary waveform PC software to edit the waveform, and then send it directly to AFG-2225, or save the waveform to a flash drive, and then transfer it to AFG-2225. (Gwinstek, 2020).

Figure 2-8 The AFG which is not calibrated Figure 2-7 The schematics of

ULN2903 (elprocus, 2020)

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11 The specification of AFG-2225 will be shown in the Table.2-7.

Table 2-7 The specifications of AFG-2225 (Good Will Instrument Co.)

Parameters value

Output Characteristics

Amplitude Range 1mVpp to 10 Vpp (into 50Ω) 2mVpp to 20 Vpp (open-circuit) 1mVpp to 5 Vpp (into 50Ω) for 20MHz25MHz 2mVpp to 10 Vpp (open-circuit) for 20MHz25MHz

Accuracy ±2% of setting ±1 mVpp (at 1 kHz) Resolution 1mV or 3 digits

Offset Range ±5 Vpk ac +dc (into 50Ω) ±10Vpk ac +dc (Open circuit) ±2.5 Vpk ac +dc (into 50Ω) for 20MHz-25MHz

±5Vpk ac +dc (Open circuit) for 20MHz25MHz Accuracy 2% of setting + 20mV+ 0.5% of amplitude

2.2 PCB design

A printed circuit board (PCB) is utilized to precisely uphold and electrically interface electronic parts utilizing conductive pathways, tracks or sign follows scratched from copper sheets overlaid onto a non-conductive substrate (Eurocircuits, 2021).

In order to design a PCB in a propriate way, the design flow can be divided into two phases, including prototyping phase and product document phase. The whole design flow is depicted in Fig. 2-9. The prototyping phase is to design a certain system or application which meets all the specifications at the earliest stage of design, including part research and selection, schematic capture and simulation, board layout, and verification and validation. The product development is a preparation of PCBs for a final application and manufacturing (NI, 2019).

For the PCB design of the EVA2, the former designers have utilized a software called Alitum Designer, hence, Altium will also be used during this project. To start designing PCB in

Alitum, the first step is capturing the desired schematic and then, building a project in Alitum and adding the schematic to the project. Secondly, use the Active Bar and the Libraries which are shown in Fig.2-10 and Fig.2-11 to place the components on the schematic diagram and connect all the components. After that, the validation and simulation are important to clarify

Figure 2-9 The Active Bar

Figure 2-11 The Libraries Figure 2-10 Complete design flow

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12 the schematic. Then, transfer the schematic to the PCB and place the corresponding

components on the PCB. Next, connect all the components and modify the trace and reroute.

Last, verify the PCB design and view the PCB in 3D. finally is to generate PCB fabrication output files (Haboud, 2018).

Moreover, there is an inspection standard in electronics industry called IPC-A-610, Acceptable of Electronics Assemblies, which has earned an international reputation as the source for end- product acceptance criteria for consumer and high reliability printed circuit assemblies (BEST, 2021). Also, for the soldering part, there is a standard called J-STD-001, Requirements for Soldered Electrical and Electronic Assemblies, which includes guidance on materials, manufacturing methods and verification criteria (Enterprises, 2018). However, IPC-A-610 includes all of J Standard. Basically, the IPC J-STD-001 is the soldering specification, which describes the process of producing high-quality soldering connections and reliable electronic components, while the supporting IPC A-610 standard is used for manufacturing and

assembling printed circuit boards of commercial electronic equipment, providing visual reference for the characteristics of printed circuit boards, as well as all defects and process indexes when inspecting a board.

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13

2.3 GUI design

A graphical user interface is a system of interactive visual components, including icons, cursors and buttons, for computer software. A GUI displays objects that convey information and represent actions that can be taken by users (Hope, 2019).

The EVA2 set up is controlled by the Delphi 10.3. Delphi is a part of rad studio and the database support is so strong that it can be applied to design GUI for desktop, web, mobile, and console applications. As an integrated development environment (ide), Delphi is equipped with multiple functions like code completion, refactoring, error insight, debugging, etc.

Setting up a project is the first step to start GUI design in Delphi and the built project will be shown in the blue square of the Fig.2-12. There are three panels, including code, design, history which is depicted in the green square, to design the interface, program the components and show the steps of editing. The structure which is as shown in the red square displays a tree diagram that shows the hierarchy of elements in the active window (that is, the Code Editor or the Form Designer) and will redirect to the code panel when double clicking it. The object inspector shown in the yellow square is to examine and edit the properties and events for the currently selected component. Moreover, the program methods of Delphi are the same as the methods of normal IDE software.

Figure 2-12 The interfaces of Delphi10.3

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14

Chapter 3 Method

The method as a guideline for implementing this project is required to be determined. V-model design methodology is chosen. In chapter 3, the V-model will be introduced, including the overview of V-model with the reason why it is chosen, and the explanation of each phase.

3.1 Overview of V-model methodology

V-model is a type of SDLC (Software Development life cycle) model where process executes in a sequential manner in V-shape and is known as verification and validation model (Kumar, 2019).

The main purpose of this methodology is to guarantee functionality of the result, by building layers upon layers of proof during the design process. The V-model contains two major phases:

design and integration, each containing several subphases. The overview of the V-model is depicted in the Fig.3-1 (Kwekkeboom, 2019).

The V-model’s purpose is validating but not innovating that means it does not aim to find the ideal solution to the problem but aims to make the design functional. The main goal of this project is to design a device which meets all the requirements from customers and the V-model can fully lead it into the efficient track. That is the reason why it is chosen as the guidance method of this project.

3.2 Phases of V-model

As what has been mentioned in chapter3.1, the V-model contains two phases: design and integration. The design phase is to determine the dimensions and variables of the result, whereas the integration phase is to test and verify the dimensions and variables.

The design and integration phases are divided into 6 phases and each one has its deliverables.

Moreover, each phase has a relationship with the sub-questions that will be solved by sub- Figure 3-1 The overview of V-model (Kwekkeboom, 2019)

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15 systems. The requirements phase will guide to determine a list of clients’ requirements, briefly functions of each sub-question’s sub-systems. The system design phase is aiming at analyzing the current situation and making a draft design of the system which will lead to the sub-system design phase. Then, the sub-system design takes the charge of dividing and designing the sub- systems, making a test plan to ensure the feasibility of the sub-systems. Next, the component design phase is to decide the suitable components for each sub-system and the component integration phase is to order and test the components. The following phase is the sub-system phase which plays a role of assembling and testing the sub-systems. Last, the system

integration phase which is related to the main problem, will lead to assembling the whole system and test if the obtained system is stable and meeting all the requirements.

Table.3-1 below will show the details of the phases, activities and their deliverables.

Table 3-1 Phases, activities and deliverables of V-model

Phases Activities Deliverables

Requirements phase Make a list of the clients’ requirements List of demands Make a document about all the functions

that is required and corresponding to the sub questions which are led by the list of demands

Function of overview

System design phase Make a table of the external interactions, the input and the output to analyze the situation

Analysis of the current situation

Make a test plan to ensure the feasibility of the system

System test plan Sub-system design

phase

Divide the system into several sub-systems Sub-system division Make a test plan to ensure the feasibility of

the sub-system

Sub-system test plan Make descriptions of the formula for each

sub-system

Formula overview Component design

phase

Make a list of all the components List of components Make a description of the component Component description Make a test plan for checking if the

components are suitable for the design

Component test plan Component

integration phase

Order the components Component orderings

Test the components based on the test plan Component test Sub-system

integration phase

Make plans of how to assemble the sub- system

Sub-system assembly plan Assemble the sub-system based on the

assembly plan

Sub-system assembly

Test the sub-system Sub-system test

System integration phase

Make plans of how to assemble the system System assembly plan Assemble the system based on the assembly

plan

System assembly

Test the system System test

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16

Chapter 4 Results

In chapter 4, the results of this project will be presented based on each stage of the V-model which has been mentioned in Chapter 3. Besides, the process of how to achieve the result is expounded as well. First, a requirements phase of the whole project will be presented with a list of requirements which is divided into functional and non-functional parts. Next, the system and sub-system design phase which correspond with the main question and sub questions will be well-explained. Meanwhile, all the selections of components for the design are motivated and reason will be clarified in the design phase. Then, the integration phase will show the building process. Additionally, all the test plans, test results and more details will be shown in the appendix.

4.1 Requirements phase

1. Functional requirements:

• The EVA2’s calibration device shall be inserted to the EVA2’s motherboard via 96 pins.

• The EVA2’S calibration device shall be operated by a software with graphical user interface (GUI).

• The EVA2’s calibration device shall be able to calibrate the EVA2’s all measurement tools:

- ADC - DAC

- Oscilloscope\TMU - Power IO module - JTAG board - AFG

• The EVA2’s calibration can be done automatically and manually.

• The EVA2’s calibration time should be limited.

2. Non-functional requirements:

• The EVA2’S calibration device shall be low cost as long as possible and the Product Life Cycle should meet the market.

• The EVA2’s calibration device shall be calibrated by the common equipment easily.

• The EVA2’s calibration device shall be validated which ensures the accuracy of the results which are within the resolution error range.

• The EVA2’s calibration device’s user manual.

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17

4.2 System design phase

This phase includes the description of the system design and the brief system validation test plan.

4.2.1 System description

Figure 4-1 shows the description of the whole system, including the relationship among the EVA2 setup, EVA2 calibration device and external devices.

The EVA2 calibration device is required to relate to EVA2’s motherboard with 6 connectors which contain 96 pins each. From the figure, the motherboard acts as the connector between SMU and EVA2 calibration device as well as between the function board and the calibration device.

For the SMU, it not only supplies power to the motherboard but also can measure the output voltage and current from the EVA2 calibration device which will play an important role in calibration (the details will be explained in sub-system design phase). Meanwhile, the SMU can also send and receive analog data from motherboard to accomplish the command, including measuring the voltage or supplying the voltage or current set by the user in software. For the functional board, it contains three DAC modules, three ADC modules, six PowerIO modules in the backplane of the motherboard and a JTAG board and a signal generator switch board inside the EVA2 box. DAC, ADC, PowerIO and JTAG board are the targets which will be calibrated by the device. Moreover, for the oscilloscopes and AFG, they will be connected directly via the

Figure 4-1 System description

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18 BNC connector in the calibration device and the oscilloscopes should be calibrated before the AFG because the calibration of AFG will utilize one of the two calibrated oscilloscopes.

If all the hardware setups are connected properly and all the drivers (software) for activating each hardware are running, the software with GUI for operating the calibration device will show the calibration results based on user’s command. There are two calibration modes for the user: general calibration for all channels and individual calibration for each channel, which means that the whole process can be completed automatically and manually.

4.2.2 System validation plan

The system validation plan is required to check if the EVA2 calibration device meets all the requirements according to the phase 4.1. Hence, it will involve both functional and one- functional requirements. The functional requirements will be checked through the GUI in the PC and the non-functional requirements will be checked with different evaluation form. The detailed system validation plan is shown in the Appendix I- system validation plan.

4.3 Subsystem design phase

In this phase, each subsystem’s design process will be explained thoroughly. First, the system will be divided into nine parts corresponding to six calibration target boards, a power supply subsystem, SMU subsystem and an interaction subsystem. The relationship among those subsystems is shown in the Fig4-2. And the detailed description of each subsystem design will be depicted from phase 4.3.1 to 4.3.8.

Figure 4-2 EVA2 calibration subsystem integration diagram

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19 The power supply subsystem provides the numerous types of power and most types of the power supply are directly from the motherboard except the +24V and -24V. Those two kinds of power supply are provided by the DC-DC converter in the EVA2 calibration board who changes the +12 V into +24V and -24 V. Meanwhile, the SMU subsystem plays an important role in the comparison between the value set by users and the value measured by the calibrated SMU.

Furthermore, the SMU can supply current with specific value which plays an essential part in calibrating the PowerIO module. Also, the interaction subsystem, including the whole software helps the user to control and operating the calibration device. It will transfer the command set by users to those six target subsystems through the I2C interface.

The main purpose of this project is to calibrate the target components, hence, the following phase will be based on the ADC, DAC, PowerIO, JTAG, AFG and oscilloscope subsystems. Due to the SMU, interaction and power supply subsystems are related to those six subsystems, the introduction of those subsystems will be interspersed in those six phases.

For the introduction, it will be divided into five parts. Firstly, a list of requirements of two subsystems will be listed as the basis of the design. Then, the following part is a general description of the subsystems to explain how they are designed as well as the SMU subsystem and power supply subsystem will be mentioned. After the subsystems’ description phase, the implementation work will start with the components selection and end with the schematics integration. Moreover, the corresponding software with GUI should is also involved in the integration phase. Last, aiming at validating the design, the subsystem test plan will be drafted.

4.3.1 ADC and DAC calibration subsystems

Due to ADC and DAC modules having numerous characters in common, the introduction of those two subsystems is demonstrated in the same phase. Because the function of ADC and DAC, the main idea for both subsystems is converting the output data transmitted from modules to the same type as the input data and comparing it with the input data.

4.3.1.1 Subsystem requirements

The requirements for the ADC and DAC calibration systems are listed below in the Table 4-1.

Table 4-1 The requirements of the ADC and DAC subsystems

ADC calibration subsystem DAC calibration subsystem 1. The 96 channels can be tested all at once or one by one

2. The test results of all the channels can be shown clearly in the GUI 3. The results of the failed channels can be shown in the GUI

4. The input analog value (within the specification) can be set by users

4. The input digital value (within the specification) can be set by users

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20 4.3.1.2 Subsystem description

The inputs and the outputs of the ADC and DAC subsystems are shown in the Figure 4-3.

As shown in the Fig.4-3, the inputs contain the power supply and commands from PC. The power supply will be provided directly by the motherboard via one of the connectors which connect the daughterboard to the motherboard. Moreover, the I2C signal will transmit the commands from the PC to ADC or DAC subsystem and the detailed commands will be explained in the Subsystem Integration phase. For the outputs, the channel state will be high or low which means the channel is enabled or disabled. And, the test results will be transmitted as the I2C signal to the PC.

The main ideas of the calibration process are: First, the user can set the desired value within the range of specification of ADC and DAC. For ADC subsystem, the PC will send the command to SMU for setting the desired input analog value from SMU to ADC module through one of the 96 channels and the ADC module will convert the analog input data to digital data sending to PC.

After that, the value shown in the PC will be compared with the value which set by users and the result after converting. For DAC subsystem, the PC will send the command to DAC module for setting the input digital value and the DAC module will convert the digital signal to analog signal as the voltage value, then the SMU will measure the value. Similarly, the set value will be compared with the measured value. However, those action will repeat for 96 times until all the channels are calibrated.

Figure 4-3 The inputs and outputs of the ADC/DAC subsystems

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21 4.3.1.3 Components selection

The logic diagram of the hardware will be shown in the Figure 4-4.

As what has mentioned in 4.3.1.2, the whole processes for ADC and DAC subsystems both require six connectors with 96 channels, analog multiplexers, capacitors and MCUs. The connectors are to connect the daughterboard to the motherboard. The analog multiplexers play a role of switch to enable and disable the channel. Last, the MCUs take the charge of controlling the multiplexer and communicating with the PC. The Table 4-2 will show the components selection of ADC and DAC subsystems.

Table 4-2 The list of components for ADC/DAC subsystem

ADC subsystem DAC subsystem

Connector Ept 304-40064-01

Analog multiplexer 74HC4067DB,118

MCU PCA9555

The reason for choosing the Ept 304-40064-01 is that, the connectors must match the connectors on the motherboard. There are sixteen ADC or DAC channels on each connector.

Aiming at calibrating one channel at once, a switch should be utilized to enable one channel while disabling the rest of them. Hence, the 16-channel analog multiplexer is considered.

Meanwhile, the analog multiplexers should meet a requirement that the power supply can be VCC (5V). Because it requires to ensure the number of power supplies as less as possible to save the energy and improve the efficiency. And, it requires to be handled by the MCU, hence, the voltage on the circuit should be on the range of MCU’s operating power supply. The PCA9555 is chosen to be the MCU because it can be supplied by 5V and provide GPIO for I2C -bus

applications for communicating with the PC.

Figure 4-4 Hardware integration for ADC/DAC subsystems

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22 4.3.1.4 Subsystem integration (PCB &GUI design)

This phase will be divided into two parts: PCB integration and GUI integration.

In order to explain the logic of designing the schematics more clearly and briefly, the schematics will be separated into 5 parts based on the

important components and function. Furthermore, due to there are six similar connectors, the

connector A will be represented on behalf of other five connectors (BCDEF).

The schematic of the connector A is shown in the Figure 4-6.

The SMU1 will connect the components on the calibration device with the SMU1+ and SMU1S+

pins for both measuring and providing power.

The In0 to In15 as shown in the orange box are the ADC input pins which will transmit the analog data from analog multiplexer to the ADC module. The Out0 to Out15 as shown in the green box are the DAC output pins which will transmit the digital analog to the analog multiplexer.

Moreover, among those 6 connectors, the

connector E has different function. It has two pins called SCL and SDA which can transmit the I2C signal as shown in the Figure 4-5.

Figure 4-6 Schematics of connector A

Figure 4-5 Schematic of partial connector E

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23 As what has mentioned before, the analog multiplexer is utilized to select the channel one by one as a switch. The schematics of the analog multiplexer parts of ADC and DAC subsystems are shown in the Figure 4-7 and 4-8.

The analog multiplexer 74HC4067DB,118 is a single-pole 16-throw analog switch. As mentioned before, it can be supply by VCC (5V). Furthermore, in order to stable the circuit, capacitors will be connected in parallel to the VCC to filter the spiking voltage. The switch features four digital select inputs (S0, S1, S2 and S3), sixteen independent inputs/outputs (Yn), a common

input/output (Z) and a digital enable input (E) (Nexperia, 74HC4067DB, 2021). So, pins, from Y0 to Y15, are connecting with In0 to In 15 of ADC subsystem and Out0 to Out15 of DAC

subsystem. In order to select the channels, the four digital select inputs and one digital enable input are controlled by the MCU via a hardness called MUXcontrol and a port. When the digital enable input E is HIGH, the switches are turned off. So, the channels can be activated by setting the digital select inputs as HIGH or LOW and the detailed function table will be shown in the Appendix III. Besides, the inputs/outputs pin connects with SMU1 as the blue box in Figure 4-5.

For ADC subsystem, the SMU will provide programable voltage as the analog input data. For DAC subsystem, the SMU will measure the output analog data which will be compared with the input value later.

Next, the design of MCU parts will be explained below. The schematic of PCA9555 part is shown in the Figure 4-9.

Figure 4-9 Schematic of PCA9555 part

Figure 4-8 Schematic of the analog switch (ADC subsystem) Figure 4-7 Schematic of the analog switch (DAC subsystem)

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24 Due to there are six connectors, it is hard to organize them into one schematic. So, the Sheet Symbol with hardness and ports will be utilized to combine those seven parts together and the schematic with MCU will be the main sheet to control six sub sheets. For the PCA9555, the SDA and SCL pins are connecting with the pins with same name in connector E as shown in the Figure 4-6 for I2C communication. The A0, A1, A2 pins will determine the address of this MCU by connecting with VCC or GND to set the pins as HIGH or LOW (0 or 1). After calculating, the combination of A0, A1, A2 has eight different ways which is enough for four required PCA9555 chips. Moreover, as mentioned before, PCA 9555 will controlled the digital select inputs pins and digital enable inputs pins of all analog multiplexers from ADC and DAC subsystems.

The GUI design will be shown in the Appendix VI – ADC and DAC subsystems and the corresponding logic diagrams will be shown in the Appendix V – Logic diagram for ADC subsystem and Logic diagram for DAC subsystem.

4.3.1.5 Subsystem test plan

The subsystem test plans for ADC and DAC subsystems are shown in the Appendix I - Subsystems – ADC calibration & DAC calibration. The test plans were used to validate the function of the ADC and DAC subsystems.

4.3.2 PowerIO calibration subsystem

According to the 2.1.4 of Theoretical framework, the Darlington transistor pair circuit of ULN2803 on the PowerIO module is the target subject to be calibrated. Based on the principle of Darlington circuit, the main idea of this subsystem is to provide the input current among the test conditions according to ULN2803’s data sheet and measure the output voltage and

compare the output value with the correct voltage corresponding to the specific test conditions.

4.3.2.1 Subsystem requirements

The requirements for the PowerIO subsystem are listed below.

• The 96 channels can be tested all at once or one by one.

• The test results of all the channels can be shown in the GUI.

• The results of the failed channels can be shown in the GUI.

• The input test value can be set by users.

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25 4.3.2.2 Subsystem description

The inputs and the outputs of the PowerIO subsystem are shown in the Figure 4-10.

As shown in the Fig.4-10, same as the ADC and DAC subsystems, the inputs contain the power supply and commands from PC. The difference is that it has a command for activating SMU to provide a voltage input and a command for activating SMU to measure the output value.

The principle of calibrating the PowerIO module will be depicted below.

The target chip to be calibrated is ULN2803A (the introduction of ULN2803A is demonstrated in the 2.1.4) and calibration goal is to check if the collector-emitter saturation voltage (Vce) is stable or not. The voltage on the orange box shown in the 4-11 represents the Vce. In order to calibrate all the channels of PowerIO module one by one, analog multiplexers will be connected to select the channel. Meanwhile, when the analog multiplexer works, it will have a stable resistance value (Ron) and the input current is Ic. Hence, the value measured by SMU is the sum of the Vce and the voltage on the analog multiplexer as the equation below.

Moreover, in order to verify if the all the Vce from three PowerIO modules are stable, it is required to supply two different Ic to calculate the Ron and Vce and supply another Ic to calculate the desired Vmeasurement(ref) as shown in the Figure 4-12. And then, compare the real Vmeasurement measured by SMU with the desired one. If they are same or the difference

Figure 4-10 The inputs and outputs of PowerIO subsystem

Figure 4-11 Voltage measurement analysis of PowerIO subsystem

𝑉𝑚𝑒𝑎𝑠𝑢𝑟𝑒𝑚𝑒𝑛𝑡= 𝑅𝑜𝑛𝐼𝑐+ 𝑉𝑐𝑒

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26 between the two values is within the margin of error, then the PowerIO module is on its

specification.

So, the main ideas of calibrating the PowerIO module based on this purpose is depicted below.

First, the SMU inputs two different Ic1 and Ic2 and measures the output voltage

Vmeasurement1 and Vmeasurement2 separately. Then, the software will calculate Ron and Vce. After that, SMU will input another Ic and measure the output voltage. Last, the voltage value will be compared with the V measurement(ref). However, those action will also repeat for 96 times until all the channels are calibrated.

4.3.2.3 Components selection

The logic diagram of the hardware is shown in the Figure 4-13.

The components for the PowerIO subsystem are similar to the DAC and ADC subsystems as shown in the 4.3.1.3 and the difference is the usage of the SMU. Hence, the function of those components will not be repeat again. The selection of components is listed below.

Table 4-3 The list of components for PowerIO subsystem PowerIO subsystem

Connector Ept 304-40064-01

Analog multiplexer 74HC4067DB,118

MCU PCA9555

Figure 4-13 Hardware integration for PowerIO subsystem Figure 4-12 The calculation process of Vmeasurement(ref)

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