JTAG calibration subsystem

According to 2.1.3 of Chapter 2. Theoretical framework, there are four dual supply transceivers called SN74LVC2T45, shown in the Figure 4-16, to be calibrated. Each transceivers’ VCCB supply voltage is required to be calibrated and the B ports are designed to track VCCB. Hence, those four port B1 are should be connected with the EVA2 calibration device and calibrated. All the design will be accomplished based on this goal.

4.3.3.1 Subsystem requirements

The requirements for the JTAG subsystem are listed below.

• The four Port B1 channels can be tested all at once or one by one.

• The test results of all the channels can be shown in the GUI.

• The results of the failed channels can be shown in the GUI.

• The input test value can be set by users.

4.3.3.2 Subsystem description

The inputs and outputs of JTAG subsystem are shown in the Figure 4-17.

The inputs of the JTAG subsystem include the power supply of 5 V from the motherboard and the command from PC and the outputs include the high or low state of channel, the digital data to PC and the command from PC to activate SMU to the measuring function.

The main ideas of the calibration process are: In order to calibrate the four dual supply

transceivers called SN74LVC2T45, firstly, it is required to send command to the JTAG board for Figure 4-16 Schematic of the SN74LVC2T45 on the JTAG board

Figure 4-17 The inputs and outputs of JTAG subsystem

29 setting the input VCCA value among the range of its specification on the data sheet. After that, the command from PC to SMU will be sent to activate SMU’s measuring voltage function. The Port B1 of the SN74LVC2T45 for tracking VCCB will be measured by the SMU. Last the measured voltage will be compared with the determined input value. Besides, the whole process will repeat for four times until all the transceivers are calibrated.

4.3.3.3 Components selection

The logic diagram of the hardware design is shown in the Figure 4-18.

The four SN74LVC2T45 transceivers have four Port B1 for tracking each VCCB value and all the Port B1 are connecting to a header connector which has ten pins in total as shown in the Figure 4-19. Hence, a header for connecting with this header is required to be designed on the EVA2 calibration device. Besides, an analog multiplexer will be chosen to select those four ports and a MCU is designed to control the multiplexer and communicate with the PC.

The Table 4-4 lists the components selection of JTAG subsystem.

Table 4-4 The list of components for JTAG subsystem

JTAG subsystem

Connector Pin header 5X2(61201021621)

Analog multiplexer 74HC4066D,652

MCU PCA9555

The pin header 61201021621 matches with the connector which can connect this header with the same header on the motherboard. The reason for choosing the 74HC4066D,652 as the analog multiplexer is that it features four input/output terminals (nY and nZ) which is suitable for selecting the four tracking Port B1 and an active HIGH enable input (nE). When nE is LOW,

Figure 4-18 The logic diagram of hardware design (JTAG subsystem)

Figure 4-19 Schematic of header on the JTAG board

30 the analogue switch is turned off. Also, it can be supplied by the 5V power. As the analog

multiplexer choosed before, it also required to be controlled by a MCU to enable the enable input (nE). Under the same condition of power supply and the same requirement of controlling and communicating with the PC as before, the PCA9555 can be choosen with the same reason as ADC,DAC and PowerIO subsystems.

4.3.3.4 Subsystem integration

The PCB design will be introduced first and it will be divided into three parts.

The VCCB signal is transmitted from the header 5X2 as what Figure 4-21 shown. The header is supplied with VCC and its four pins corresponding to the header on the motherboard which transmits the VCCB signal will be selected by the analog multiplexer through four nets called TDI, TCK, TMO, TDO.

The shematics of the analog multiplexer is shown in the Figure 4-20. All the nY pins take the charge of receiving the value from the header as the input pins. The nZ pins play the roles of output pins which are connecting with a SMU1JTAG port and the SMU1JTAG port will connect the SMU+ port in the connector A. Moreover, the enable pins nE will be controlled by PCA9555 in the main sheet as shown in the Figure 4-22.

The GUI design will be shown in the Appendix VI –JTAG subsystem. And, the Logic diagram of JTAG calibration system is shown in the Appendix V – Logic diagram for JTAG subsystem.

Figure 4-21 Schematic of header 5X2 Figure 4-20 Schematic of analog multiplexer (JTAG subsystem)

Figure 4-22 Partial schematic of main sheet

31 4.3.3.5 Subsystem test plan

The subsystem test plans for JTAG subsystem are shown in the Appendix I – JTAG calibration.

The software and hardware of the subsystem complement each other. The purpose of the JTAG calibration test plan is to check whether data can be transmitted between the PC and

microcontroller, and whether data can be transmitted between the PC and the SMU. And check if the MCUs can select the channels. Finally, check whether the users can use the GUI to realize calibration functions.