PowerIO calibration subsystem

4.3.2 PowerIO calibration subsystem

According to the 2.1.4 of Theoretical framework, the Darlington transistor pair circuit of ULN2803 on the PowerIO module is the target subject to be calibrated. Based on the principle of Darlington circuit, the main idea of this subsystem is to provide the input current among the test conditions according to ULN2803’s data sheet and measure the output voltage and

compare the output value with the correct voltage corresponding to the specific test conditions.

4.3.2.1 Subsystem requirements

The requirements for the PowerIO subsystem are listed below.

• The 96 channels can be tested all at once or one by one.

• The test results of all the channels can be shown in the GUI.

• The results of the failed channels can be shown in the GUI.

• The input test value can be set by users.

25 4.3.2.2 Subsystem description

The inputs and the outputs of the PowerIO subsystem are shown in the Figure 4-10.

As shown in the Fig.4-10, same as the ADC and DAC subsystems, the inputs contain the power supply and commands from PC. The difference is that it has a command for activating SMU to provide a voltage input and a command for activating SMU to measure the output value.

The principle of calibrating the PowerIO module will be depicted below.

The target chip to be calibrated is ULN2803A (the introduction of ULN2803A is demonstrated in the 2.1.4) and calibration goal is to check if the collector-emitter saturation voltage (Vce) is stable or not. The voltage on the orange box shown in the 4-11 represents the Vce. In order to calibrate all the channels of PowerIO module one by one, analog multiplexers will be connected to select the channel. Meanwhile, when the analog multiplexer works, it will have a stable resistance value (Ron) and the input current is Ic. Hence, the value measured by SMU is the sum of the Vce and the voltage on the analog multiplexer as the equation below.

Moreover, in order to verify if the all the Vce from three PowerIO modules are stable, it is required to supply two different Ic to calculate the Ron and Vce and supply another Ic to calculate the desired Vmeasurement(ref) as shown in the Figure 4-12. And then, compare the real Vmeasurement measured by SMU with the desired one. If they are same or the difference

Figure 4-10 The inputs and outputs of PowerIO subsystem

Figure 4-11 Voltage measurement analysis of PowerIO subsystem

𝑉𝑚𝑒𝑎𝑠𝑢𝑟𝑒𝑚𝑒𝑛𝑡= 𝑅_𝑜𝑛𝐼_𝑐+ 𝑉𝑐𝑒

26 between the two values is within the margin of error, then the PowerIO module is on its

specification.

So, the main ideas of calibrating the PowerIO module based on this purpose is depicted below.

First, the SMU inputs two different Ic1 and Ic2 and measures the output voltage

Vmeasurement1 and Vmeasurement2 separately. Then, the software will calculate Ron and Vce. After that, SMU will input another Ic and measure the output voltage. Last, the voltage value will be compared with the V measurement(ref). However, those action will also repeat for 96 times until all the channels are calibrated.

4.3.2.3 Components selection

The logic diagram of the hardware is shown in the Figure 4-13.

The components for the PowerIO subsystem are similar to the DAC and ADC subsystems as shown in the 4.3.1.3 and the difference is the usage of the SMU. Hence, the function of those components will not be repeat again. The selection of components is listed below.

Table 4-3 The list of components for PowerIO subsystem PowerIO subsystem

Connector Ept 304-40064-01

Analog multiplexer 74HC4067DB,118

MCU PCA9555

Figure 4-13 Hardware integration for PowerIO subsystem Figure 4-12 The calculation process of Vmeasurement(ref)

27 4.3.2.4 Subsystem integration

The PCB integration will be depicted first. Same as ADC and DAC subsystems, the PowerIO modules are connecting to six connectors on the motherboard. So, PowerIO subsystem also relates to six connectors on the EVA2 calibration device. Take connector A as an example, as the red box shown in the Figure 4-14, the Pout0 to Pout 15 in the connector A are the pins to transmit the data between a PowerIO module and the analog multiplexer connects with the connector A same as the ADC and DAC subsystems to select the channels.

The schematics of the analog multiplexer is shown in the Figure 4-15. The digital select inputs (S0, S1, S2 and S3) are controlled by the PCA9555 as well through the same harness as ADC and DAC subsystems. Differently, the digital enable input E connects with the PCA9555 on the main sheet with Port P. Furthermore, the SMU signals via SMU1A from SMU1+ and SMU1S+ pins play a role in providing the current and measuring the voltage from PowerIO module via the

selected channel.

Meanwhile, the I2C signal transmitted between PC and EVA2 device is also working between the SCL and SDA pins on the connector E as Figure 4-5.

The GUI design will be shown in the Appendix VI –PowerIO subsystem. Moreover, the Logic diagram of JTAG calibration system is shown in the Appendix V – Logic diagram for PowerIO subsystem.

4.3.2.5 Subsystem test plan

The subsystem test plans for PowerIO subsystem are shown in the Appendix I – Subsystem – PowerIO calibration. The test plans were used to check if the data can be transmitted between the PC and MCUs and be transmitted between the PC and SMU. And check if the MCUs can select the channels. Last, check if users can use GUI to achieve the calibration functions.

Figure 4-15 Schematic of the analog switch (PowerIO subsystem)

Figure 4-14 Partial schematic of connector A

28