ADC and DAC calibration subsystems

Due to ADC and DAC modules having numerous characters in common, the introduction of those two subsystems is demonstrated in the same phase. Because the function of ADC and DAC, the main idea for both subsystems is converting the output data transmitted from modules to the same type as the input data and comparing it with the input data.

4.3.1.1 Subsystem requirements

The requirements for the ADC and DAC calibration systems are listed below in the Table 4-1.

Table 4-1 The requirements of the ADC and DAC subsystems

ADC calibration subsystem DAC calibration subsystem 1. The 96 channels can be tested all at once or one by one

2. The test results of all the channels can be shown clearly in the GUI 3. The results of the failed channels can be shown in the GUI

4. The input analog value (within the specification) can be set by users

4. The input digital value (within the specification) can be set by users

20 4.3.1.2 Subsystem description

The inputs and the outputs of the ADC and DAC subsystems are shown in the Figure 4-3.

As shown in the Fig.4-3, the inputs contain the power supply and commands from PC. The power supply will be provided directly by the motherboard via one of the connectors which connect the daughterboard to the motherboard. Moreover, the I2C signal will transmit the commands from the PC to ADC or DAC subsystem and the detailed commands will be explained in the Subsystem Integration phase. For the outputs, the channel state will be high or low which means the channel is enabled or disabled. And, the test results will be transmitted as the I2C signal to the PC.

The main ideas of the calibration process are: First, the user can set the desired value within the range of specification of ADC and DAC. For ADC subsystem, the PC will send the command to SMU for setting the desired input analog value from SMU to ADC module through one of the 96 channels and the ADC module will convert the analog input data to digital data sending to PC.

After that, the value shown in the PC will be compared with the value which set by users and the result after converting. For DAC subsystem, the PC will send the command to DAC module for setting the input digital value and the DAC module will convert the digital signal to analog signal as the voltage value, then the SMU will measure the value. Similarly, the set value will be compared with the measured value. However, those action will repeat for 96 times until all the channels are calibrated.

Figure 4-3 The inputs and outputs of the ADC/DAC subsystems

21 4.3.1.3 Components selection

The logic diagram of the hardware will be shown in the Figure 4-4.

As what has mentioned in 4.3.1.2, the whole processes for ADC and DAC subsystems both require six connectors with 96 channels, analog multiplexers, capacitors and MCUs. The connectors are to connect the daughterboard to the motherboard. The analog multiplexers play a role of switch to enable and disable the channel. Last, the MCUs take the charge of controlling the multiplexer and communicating with the PC. The Table 4-2 will show the components selection of ADC and DAC subsystems.

Table 4-2 The list of components for ADC/DAC subsystem

ADC subsystem DAC subsystem

Connector Ept 304-40064-01

Analog multiplexer 74HC4067DB,118

MCU PCA9555

The reason for choosing the Ept 304-40064-01 is that, the connectors must match the connectors on the motherboard. There are sixteen ADC or DAC channels on each connector.

Aiming at calibrating one channel at once, a switch should be utilized to enable one channel while disabling the rest of them. Hence, the 16-channel analog multiplexer is considered.

Meanwhile, the analog multiplexers should meet a requirement that the power supply can be VCC (5V). Because it requires to ensure the number of power supplies as less as possible to save the energy and improve the efficiency. And, it requires to be handled by the MCU, hence, the voltage on the circuit should be on the range of MCU’s operating power supply. The PCA9555 is chosen to be the MCU because it can be supplied by 5V and provide GPIO for I2C -bus

applications for communicating with the PC.

Figure 4-4 Hardware integration for ADC/DAC subsystems

22 4.3.1.4 Subsystem integration (PCB &GUI design)

This phase will be divided into two parts: PCB integration and GUI integration.

In order to explain the logic of designing the schematics more clearly and briefly, the schematics will be separated into 5 parts based on the

important components and function. Furthermore, due to there are six similar connectors, the

connector A will be represented on behalf of other five connectors (BCDEF).

The schematic of the connector A is shown in the Figure 4-6.

The SMU1 will connect the components on the calibration device with the SMU1+ and SMU1S+

pins for both measuring and providing power.

The In0 to In15 as shown in the orange box are the ADC input pins which will transmit the analog data from analog multiplexer to the ADC module. The Out0 to Out15 as shown in the green box are the DAC output pins which will transmit the digital analog to the analog multiplexer.

Moreover, among those 6 connectors, the

connector E has different function. It has two pins called SCL and SDA which can transmit the I2C signal as shown in the Figure 4-5.

Figure 4-6 Schematics of connector A

Figure 4-5 Schematic of partial connector E

23 As what has mentioned before, the analog multiplexer is utilized to select the channel one by one as a switch. The schematics of the analog multiplexer parts of ADC and DAC subsystems are shown in the Figure 4-7 and 4-8.

The analog multiplexer 74HC4067DB,118 is a single-pole 16-throw analog switch. As mentioned before, it can be supply by VCC (5V). Furthermore, in order to stable the circuit, capacitors will be connected in parallel to the VCC to filter the spiking voltage. The switch features four digital select inputs (S0, S1, S2 and S3), sixteen independent inputs/outputs (Yn), a common

input/output (Z) and a digital enable input (E) (Nexperia, 74HC4067DB, 2021). So, pins, from Y0 to Y15, are connecting with In0 to In 15 of ADC subsystem and Out0 to Out15 of DAC

subsystem. In order to select the channels, the four digital select inputs and one digital enable input are controlled by the MCU via a hardness called MUXcontrol and a port. When the digital enable input E is HIGH, the switches are turned off. So, the channels can be activated by setting the digital select inputs as HIGH or LOW and the detailed function table will be shown in the Appendix III. Besides, the inputs/outputs pin connects with SMU1 as the blue box in Figure 4-5.

For ADC subsystem, the SMU will provide programable voltage as the analog input data. For DAC subsystem, the SMU will measure the output analog data which will be compared with the input value later.

Next, the design of MCU parts will be explained below. The schematic of PCA9555 part is shown in the Figure 4-9.

Figure 4-9 Schematic of PCA9555 part

Figure 4-8 Schematic of the analog switch (ADC subsystem) Figure 4-7 Schematic of the analog switch (DAC subsystem)

24 Due to there are six connectors, it is hard to organize them into one schematic. So, the Sheet Symbol with hardness and ports will be utilized to combine those seven parts together and the schematic with MCU will be the main sheet to control six sub sheets. For the PCA9555, the SDA and SCL pins are connecting with the pins with same name in connector E as shown in the Figure 4-6 for I2C communication. The A0, A1, A2 pins will determine the address of this MCU by connecting with VCC or GND to set the pins as HIGH or LOW (0 or 1). After calculating, the combination of A0, A1, A2 has eight different ways which is enough for four required PCA9555 chips. Moreover, as mentioned before, PCA 9555 will controlled the digital select inputs pins and digital enable inputs pins of all analog multiplexers from ADC and DAC subsystems.

The GUI design will be shown in the Appendix VI – ADC and DAC subsystems and the corresponding logic diagrams will be shown in the Appendix V – Logic diagram for ADC subsystem and Logic diagram for DAC subsystem.

4.3.1.5 Subsystem test plan

The subsystem test plans for ADC and DAC subsystems are shown in the Appendix I - Subsystems – ADC calibration & DAC calibration. The test plans were used to validate the function of the ADC and DAC subsystems.