Update of the “Digital EMC project”

MICAS Department of Electrical Engineering (ESAT)

June 5th, 2007

Junfeng Zhou

Promotor: Prof. Wim Dehaene

KULeuven ESAT-MICAS

Update of the “Digital EMC project”

MICAS Department of Electrical Engineering (ESAT)

EME and di/dt measurement Setups

Low Drop-out /

Serial Regulator AMIS digital load EMI-Suppressing

Regulator (MICAS)

GND

VCC VDD<1..10>

VDD2 = 3.3 V VCCC =12 V

i i

i i

and V and V

i

i i

and V and V

PC

configuration bits VCC = 4.5 V ~ 8 V

i

Setup-1 Setup-2

Setup-3

Semi-automatic setup is ready both for Semi-automatic setup is ready both for

time and frequency domain !

time and frequency domain !

MICAS Department of Electrical Engineering (ESAT)

Description of the gate counts comparison

9 inverters Other 2 inverter chains

FFs are connected through MUX

FF FF FF FF

Din CLK RST

Out 60 FF

Chain 2 Chain 3

Chain 4 Chain 5 1 inverter-chain

Chain 1

MUX MUX

There are 7 work modes There are 7 work modes

MICAS Department of Electrical Engineering (ESAT)

Some words on the comparison itself

 Focus on comparisons in Time Domain:

 | di/dt | maximum value

 Difficulty in comparison and interpretation in Frequency Domain:

 Fundamental or harmonic frequency ?

 Is it fair to only compare the PEAK in spectrum ? PEAK

 How about when peak value happens in different

harmonics for different waveform ?

MICAS Department of Electrical Engineering (ESAT)

An example

^{9.87x10 9.87x10}

^{A/s A/s}

Gate counts : Gate counts : condition 2 condition 2

Gate counts : Gate counts : condition 4

condition 4

^{56.7 dB uV 56.7 dB uV 60.1 dB uV 60.1 dB uV}

^{1.25x10 1.25x10}

^{A/s A/s}

MICAS Department of Electrical Engineering (ESAT)

Setup-1 – di/dt vs. Slave Clock Domain ( MSFF )

untitled

Note:

1. MSFF-chain 1 (no decoupling capacitor ),

2. MSFF - master slave non-overlap time 5.8 ns, 3. Periodic data input,

4. Clk=10 MHz,

1 slave clock domain

3 slave clock domains

1 slave clock domain :

Disable delays between slave clock signals SCLK1, SCLK2 and SCLK3.

3 slave clock domains:

Enable delays between slave clock signals SCLK1, SCLK2 and SCLK3.

Conclusion: Conclusion:

Very effective method, more than 2.5 time Very effective method, more than 2.5 time

di/dt reduction,. di/dt reduction,.

MICAS Department of Electrical Engineering (ESAT)

Setup-1 – di/dt vs. distributed clock ( MSFF )

untitled

Note:

1. MSFF-chain 1 (no decoupling capacitor ),

2. Periodic data input, 3. Clk=10 MHz,

master

slave

Non-overlap time 5.8ns

33ns

Discussion:

1. Reduction is quite limited, expected more di/dt reduction ?!

2. Probably more apparent when more chains are on,

17.4ns

MICAS Department of Electrical Engineering (ESAT)

Setup-1 – di/dt peak vs. Gate counts

Note:

1. Periodic data input, 2. Clk= 10 MHz,

3. MSFF - master slave non- overlap time

5.8 ns.

Description of gate counts:

1 1. Chain 1, neighbouring FFs are connected directly, 2 2. Chain 1, neighbouring FFs are connected via an inverter chain, +

the upper inverter chain toggling,

3 3. ‘2’ condition + bottom inverter chains toggling, 4 4. chain 1 and 2 in ‘3’

condition,

5. 5. chain 1, 2 and 3 in ‘3’

condition

6 6. chain 1, 2, 3 and 4 in ‘3’

condition

7 7. chain 1, 2 , 3 , 4 and 5 in

‘3’ condition

linear relationship from 3 ~ 7 linear relationship from 3 ~ 7

1 1 2 2 3 3 4 4 5 5 6 6 7 7

di/dt vs. Gate counts

Gate counts

MICAS Department of Electrical Engineering (ESAT)

Setup-1 – di/dt peak vs. V _DD

In First order:

di/dt is proportional to V _DD

Note:

1. DFF-chain 1 and MSFF- chain 1 (no

decoupling capacitor ), 2. MSFF - master slave non-overlap time

5.8 ns

3. Clk = 10MHz,

4. Periodic data input,

5. VDD=1.5v, 2.0v, 2.7v,

3.3v .

MICAS Department of Electrical Engineering (ESAT)

Setup-1 – di/dt vs. Clock Frequency

To be discussed the To be discussed the relationship

relationship

Note:

1. DFF-chain 1 and MSFF- chain 1 (no

decoupling capacitor ), 2. MSFF - master slave non-overlap time

5.8 ns

3. Periodic data input,

4. Clk=2.5, 4, 5, 8 ,10 MHz

2.5 4 5 8 10

MICAS Department of Electrical Engineering (ESAT)

Setup-1 – di/dt vs. Decoupling Strategy

untitled

Note:

1. Periodic data input, 2. Clk=8 MHz,

3. MSFF - master slave non-overlap time

5.8 ns 1: No decoupling capacitors. 1:

2: 1/2 times PNMOS decoupling capacitors. 2:

3:

3: PNMOS decoupling capacitors 4:

4: PNMOS decoupling capacitors, with thick metal 4 power ring.

5: MIMC decoupling capacitors next to the chain, 5:

with the same capacity value as PNMOS capacitor in the chains 3 and 4.

Conclusion:

1. decoupling capa helps to reduce the di/dt, 2. the MIMC capacitor is most effective, 3. Power ring might introduce noise,

1 1 2 2 3 3 4 4 5 5

Note: PNMOS means Pseudo-NMOS

Note: PNMOS means Pseudo-NMOS

1 time PNMOS capacitor = ?? pF

MICAS Department of Electrical Engineering (ESAT)

Questions for AMIS and KHBO

 What do you really want ?

 time domain or frequency domain

 Output = F _unction ^{(Input) ?}

 If frequency domain ? What is the most important ?

 I(w) ? ( spectra of i(t) )

 s*I(w) ? ( spectra of di/dt )

 For which is the Gabarit made ?

MICAS Department of Electrical Engineering (ESAT)

Example of spectrum of di/dt

^{56.7 dB uV 56.7 dB uV 60.1 dB uV 60.1 dB uV}

226.4 dB 226.4 dB

227.7 dB 227.7 dB

Gate counts : Gate counts : condition 2 condition 2

Gate counts : Gate counts : condition 4

condition 4

^{jw jw jw jw}

MICAS Department of Electrical Engineering (ESAT)

Other conclusion

 It seems that MSFF is more di/dt friendly given the same other conditions,

 MSFF offers more degrees of freedom for di/dt reduction:

 Clock domains,

 Distributed Clock  more exploration needed !

MICAS Department of Electrical Engineering (ESAT)

Future Work

 Interpretation of the measured results,

 Time domain,

 Frequency domain

 Model Construction