Design-In for EMC on digital circuit

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MICAS Department of Electrical Engineering (ESAT)

Design-In for EMC on digital circuit

December 5th, 2005

Low Emission Digital Circuit Design

Junfeng Zhou Wim Dehaene

KULeuven ESAT-MICAS

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Outline

1. Introduction

2. Logic family selection 3. Clock strategy selection

SSCG - Delay cell array approach 4. Low noise power supply

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Part I: Introduction

 Electro-Magnetic Interference (EMI) and radiated emission have become a major problem for high speed digital circuit,

 Most of them are due to power and ground fluctuation.

 Although the detailed calculation of EMI noise is rather difficult , we can use the di/dt as the index, since the current loop

contributes the EMI.

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Part 2: Logic Family Selection

SCMOS PNMOS RSBCMOS

CSL MCML FSCL

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Comparison of di/dt ,power and area

Target : Mixed-Mode Automotive Electronics Design Key aspects : di/dt + Power + Area + Speed

Inv erter Power in different logic techniques

0.00E+00 5.00E+01 1.00E+02 1.50E+02 2.00E+02 2.50E+02

SCMOS PNMOS RSBMOS CSL MCML FSCL

Power [μW]

Inv erter area in different logic techniques

0 0.5 1 1.5 2 2.5 3 3.5 4

SCMOS PNMOS RSBMOS CSL MCML FSCL

Area [μm2]

Ring Oscillator of 21-stages

(Static + Dynamic)

Current Steering Logic

But there is static power !!

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Detailed comparison of CSL and SCMOS

0 20 40 60 80 100 120 140 160 180

10^-6 1x10^-5 1x10^-4 10^-3

Frequency [ MHz ]

Power consumption [ W ]

CSL dynamic power

CSL static power CSL dynamic power CSL power

(activity=0.5) SCMOS power (activity=0.5)

SCMOS power activity=0.5 CSL power activity=0.5 CSL static power

V_DD=1.5v

Note:

The curve of CSL 16-bit RCA was obtained by calculating the real speed F of the circuit, given the different supply current I.

CSL

One-bit Adder

IT is a static power problem, Switching off when standby ?

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Detailed comparison of CSL and SCMOS

SCMOS

CSL

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Problem with CSL

 Mismatch sensitive, annoying for standard cells

 rather slow/power hungry

 Not full swing

Matching required!

M1 > M3

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Can we do it better ?



C-CBL:

 sizing for optimal current balance is really difficult ,process dependent

CBL

[Albuquerque, E.F.M.; Silva, M.M., Current-balanced logic for mixed-signal IC's]

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Solution- Enhanced current steering logic

 Still current source basing

 Increase in logic level, hence increase the robustness

 Reduced output capacitance, hence the speed is increased

Fig.3 E-CSL inverter

Minimum size

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Comparison of CSL, C-CBL,

ECSL and SCMOS

10M 100M 1G 10G

1 10 100 1k 10k 100k 1M 10M 100M

CSL C-CBL E-CSL SCMOS V_DD=3 v C_LOAD=5 fF

F [Hz]

di/dt p-p [A/s]

Fig.5 di/dt vs. frequency Fig.4 power vs. frequency

10M 100M 1G 10G

1E-7 1E-6 1E-5 1E-4

1E-3 Area@500 MHz

CSL 7.2 um² C-CBL 2.1 um² E-CSL 1.53 um² SCMOS 6.5 um²

V_DD=3 v C_LOAD=5 fF

Power [w]

F [Hz]

CSL C-CBL E-CSL SCMOS

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di/dt performance vs.

process variation

10M 100M 1G 10G

10 100 1k 10k 100k 1M 10M

100M V_DD=3 v C_LOAD=5 fF

TT FF FS SF SS F [Hz]

di/dt p-p [A/s]

CSL

10M 100M 1G 10G

10 100 1k 10k 100k 1M 10M

TT FF FS SF SS F [Hz]

di/dt p-p [A/s]

E-CSL

10M 100M 1G 10G

10 100 1k 10k 100k 1M 10M

TT FF FS SF SS

F [Hz]

di/dt p-p [A/s]

C-CBL

10M 100M 1G 10G

10 100 1k 10k 100k 1M 10M

TT FF FS SF SS di/dt p-p [A/s]

F [Hz]

SCMOS

Fig.6 di/dt vs. process corner

MAX di/dt change

MIN di/dt change

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Conclusion of Low noise Logic Families

Winner is E-CSL

 CSL,E-CSL show a smaller area per logic function for complex digital gates and systems compared to SCMOS logic technique.

 Current source ensures the major di/dt reduction,

 Process variation sensitivity also becomes better due to the dominance of current source,

 E-CSL gives comparable di/dt performance with CSL,

 E-CSL is Faster and Less power consuming than CSL due to the lower area and lower capacitance.

 Static power consumption remains the challenge for wide application of the CSL,E-CSL technique in very large

digital systems. Can be solved by using power down strategies, which is highly application dependent

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Part II: Clock strategy (SSCG)

[Keith B. Hardin, Spread Spectrum Clock Generation for the Reduction of Radiated Emissions]



 



  



MOD o SSC

dB f

f

A  n

log10

10

1. Deviating the period of the clock signal from its fundamental by a small

percentage(usually +/- 1% ) and in a predictable fashion(usually Triangular modulation profile )

2. The total power of the clock signal remains the same.

Implementation:

1. PLL-SSCG: VCO has its input voltage controlled by a modulation waveform.

2. DCA-SSCG: By controlling the temporal spacing of the edges, the clock’s frequency is indirectly

controlled

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SSCG - PLL vs. DCA ?

Disadvantage of PLL-SSCG:

 Basically analog circuit(VCO, charge pump, loop filter), more susceptible to noise

 PLL-SSCG suffers from the drawback of reduction in maximum achievable EMI reduction due to the inherent random jitter of the circuitry(due to thermal noise, flicker noise).

 Leads to large jitter in clock which is unacceptable

Advantage of DCA-SSCG

 Digital circuits, good immunity to noise.

 Leads to smaller random jitter, simpler implementation and reduction in area

 The reduction in variance of unintentional jitter is key to the delay cell array technique being able to achieve greater reduction in EMI.

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SSCG-DCA: How does it work^?

Each delay cell comprised of delay element and a positive latch:

EN D Q

EN D

… Q

Delay Cell #1 Delay Cell #2 Delay Cell #N

Result: Edge-to-edge jitter varied in deterministic fashion.

f⁰

SSC: f⁰+ ∆f

N/2 Counter Q T

T Flip-Flop

Delay Cell Control

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Clock Attenuation

Our results show:

 Dominant power in odd harmonics

 DCA-SSCG:

 Delay cell based SSCG

implemented shows low power and simple circuit implementation

 8dB of clock attenuation on fundamental

 Improved design can be achieved by using differential delay cell

element

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Part III: Low Noise Power supply design

However 2 problems still remain:

• Static power consumption

• New logic family standard cell must be designed and characterised

?? Is there any global approach ??

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Questions

Thank you for your attention