Automotive IC Design for Low EMC Automotive IC Design for Low EMC AID-EMC AID-EMC

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Silicon Solutions for the Real World Silicon Solutions for the Real World

AID-EMC

Automotive IC Design for Low EMC

AID-EMC

Automotive IC Design for Low EMC

Review Meeting 29 augustus 2006 VILVOORDE

KUL-ESAT-MICAS

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Slide 2 AID-EMC review meeting 29/08/2006 CONFIDENTIAL

AID-EMC review meeting 29/08/2006 CONFIDENTIAL

Agenda Agenda

Structure of the IWT project Progress per workpackage

WP1:

WP2:

WP3:

WP4:

Status Deliverables Resources used

Cooperation

Conclusions

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Structure of the project Structure of the project

WP2 Analog

specs Comparison

of results

Comparison of results specs

Improved design techniques

WP3 Digital

WP4 CAD WP1 Specs &

Measurements

WP2 Analog

specs Comparison

of results

Comparison of results specs

Improved design techniques

WP3 Digital

WP4 CAD WP1 Specs &

Measurements

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WP1: Specifications and measurements

WP1: Specifications and

measurements

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WP1: Technical problems WP1: Technical problems

Nearly impossible to achieve

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T1.1: Correlation between different test set-ups

Target is to increase current handling

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T1.2: Influence of PCB and attached cabling

VDMOS is more stable and robust

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T1.3: Validation of the ICEM model T1.3: Validation of the ICEM model

Need for additional

Selection

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T1.4: Characterization of the coupling paths

Need for additional

Selection

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T1.5: Measurements T1.5: Measurements

Need for additional

Selection

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Contributions by partners Contributions by partners

AMIS

Aa bb

KUL-ESAT

aa

KHBO

cc

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WP1: Innovation Realised WP1: Innovation Realised

Improved

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WP2: EMC susceptibility of analogue circuits

WP2: EMC susceptibility of

analogue circuits

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WP2: Technical problems WP2: Technical problems

LDMOS

Surface

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T2.1: Finalization of the LIN driver T2.1: Finalization of the LIN driver

Design

Use

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T2.2: Design DC current regulator with low EMS

ESD

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T2.3: Design input structure with low EMS

Optimize

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T2.4: Design input structure with high common mode rejection

Optimize

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T2.3: Design guidelines for low EMS T2.3: Design guidelines for low EMS

Optimize

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Contributions by partners Contributions by partners

AMIS

Aa bb

KUL-ESAT

aa

KHBO

cc

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WP2: Innovation Realised WP2: Innovation Realised

New Better

Guidelines

Technical Risks

Protection Protection

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WP3: Digital techniques

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WP3: Technical problems WP3: Technical problems

Logic families with reduced current variation

how logic circuits can be designed in such a way that they generate less current variation (di/dt) in the supply lines

EMC-friendly clock strategy

how the electromagnetic radiation caused by digital circuits can be reduced by adapting the clock strategy.

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T3.1: Design of EMC-friendly logic families - I

Selection of EMC-friendly logic family:

6 different logic design techniques are compared,

The design goal is to reduce di/dt noise while still keep the compromise on the speed, power, area trade-off under control, Based on the simulations, we conclude that CSL logic is the best choice.

Comparison of CSL and SCMOS:

The CSL logic produces an amount of di/dt noise almost 36dB smaller than the SCMOS logic,

If controlled properly, we can keep the power of CSL circuit comparable to the SCMOS,

CSL show a smaller area per logic function for complex digital gates and systems.

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T3.1: Design of EMC-friendly logic families - II

Target : Mixed-Mode Automotive Electronics Design Key aspects : di/dt + Power + Area + Speed

Inv erter Power in different logic techniques

0.00E+00 5.00E+01 1.00E+02 1.50E+02 2.00E+02 2.50E+02

SCMOS PNMOS RSBMOS CSL MCML FSCL

Power [μW]

Inv erter area in different logic techniques

0 0.5 1 1.5 2 2.5 3 3.5 4

SCMOS PNMOS RSBMOS CSL MCML FSCL

Area [μm2]

Ring Oscillator of 21-stages

(Static + Dynamic)

Current Steering Logic

But there is static power !!

di/dt Peak-Peak Power Area

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T3.1: Design of EMC-friendly logic families - III

Power spectrum density Power spectrum density of di/dt comparison

of di/dt comparison

SCMOS

CSL 36dB

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T3.2: EMC-friendly clock strategies - I

Clock skew

Clock skew:

based on the introduction of different skews to the branches of a clock tree.

Only 2-5dB reduction,

Need smart algorithm to control and optimize the skew.

Spread Spectrum Clock Generation(SSCG)

Spread Spectrum Clock Generation(SSCG):

based on an existing DLL idea.

Spread the clock period by a programmable amount, Fully digital and simple implementation,

More than 12dB on the maximum di/dt power spectrum reduction.

2 different clock strategies are studied:

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T3.2: EMC-friendly clock strategies - II

Spectrum from 300MHz to 800MHz

Spread Spectrum

Clock

Regular Clock

12dB reduction

Zoom in

A test chip for SSCG will be designed to prove the A test chip for SSCG will be designed to prove the

simulation(next project phase).

Problem remains: introduction into a standard Problem remains: introduction into a standard

design flow.

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T3.3: Test chip for the EMI Suppressing Regulator - I T3.3: Test chip for the EMI

Suppressing Regulator - I

The EMI suppressing regulator replaces the EMC-friendly logic:

Control the way the current delivered to the internal digital core, hence keep the EMI under control,

Compatible with conventional CMOS logic,

Large EMI reduction is ensured (40dB), comparable with low noise digital cells only,

More power efficient than low noise logic cells,

Can be adjusted to a wide range of chip size and power consumption level.

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T3.3: Test chip for the EMI Suppressing Regulator - II T3.3: Test chip for the EMI

Suppressing Regulator - II

current of Vbat

di/dt ^p-p =8.5x10⁴ [A/s]

load current of digital core

FFT FFT

di/dt ^p-p =1.8x10⁹ [A/s]

di/dt of Vbat di/dt

of V3v3

40dB (EMI regulator) + 20dB (Serial regulator 40dB (EMI regulator) + 20dB (Serial regulator))

9x10⁶

7x10³

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T3.3: Test chip for the EMI Suppressing Regulator - III T3.3: Test chip for the EMI Suppressing Regulator - III

Micrograph of the RD2E test chip and the EMI suppressing regulator

EMI

Suppressing regulator

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T3.3: Test chip for the EMI Suppressing Regulator - IV T3.3: Test chip for the EMI Suppressing Regulator - IV

Measurements

di/dt@Vbat

di/dt@source

> 5x reduction

TBD:

• figure out low current capability problem,

• detailed measurements will be ready in 2nd phase

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Contributions by partners Contributions by partners

AMIS

Deliver specifications for the chip, Deliver design kit,

Process the chip,

Evaluate the chip measurement results.

KUL-ESAT-MICAS

Scientific analysis, Chip design,

Chip measurements.

KHBO

Advice on the EMC measurements.

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