Status of the “Digital EMC project”

MICAS Department of Electrical Engineering (ESAT)

AID–EMC: Low Emission ^Digital

Circuit Design

Status of the “Digital EMC project”

Junfeng Zhou

Wim Dehaene

MICAS Department of Electrical Engineering (ESAT)

Logic styles under investigation

Logic style

1. Standard CMOS logic

2. Pseudo NMOS logic

3. CSL (CMOS Current Steering Logic)

4. MCML (MOS Current Mode Logic--differential version of CSL)

MICAS Department of Electrical Engineering (ESAT)

Comparison---Maximum di/dt of an Inverter

1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07 1.00E+08

1 2 3 4

logic style

di/dt(amp/s)

Standard CMOS Pseudo NMOS CSL

MCML

Why CSL ?

Target : Mixed-Mode Automotive Electronics Design Key aspects : di/dt + Power + Area + Speed

Current Steering Logic

MICAS Department of Electrical Engineering (ESAT)

CSL – Static Characteristic

Static Characteristic

0 0.5 1 1.5 2 2.5

0 5 10 15 20 25

R

Voltage(v)

VOH VOL VIL VIH

Design Parameter:

R=

Vdd=2.5v

I=20uA

C

=20fF

MICAS Department of Electrical Engineering (ESAT)

CSL – Noise Margin

Noise Margin vs. R

0 0.2 0.4 0.6 0.8 1 1.2

0 5 10 15 20 25

R

Noise Margin(v)

NMH NML

Vdd=2.5v I=20uA C

=20fF

300mV

R >4



MICAS Department of Electrical Engineering (ESAT)

CSL – Dynamic Characteristic

Propagation delay vs. R

0 1E-10 2E-10 3E-10 4E-10 5E-10 6E-10

0 5 10 15 20

R

tp(s)

tp

Vdd=2.5v

I=20uA

C

=20fF

MICAS Department of Electrical Engineering (ESAT)

The Effect of Decoupling Capacitance

There is a Trade off !

Cd

Vdd=3.3v I=10uA R=6

C

=20fF

di/dt

1p

10p,100p,1n,10n

MICAS Department of Electrical Engineering (ESAT)

Comparison of 16-bit RCA, CSL vs.

SCMOS

Note:

The curve of CSL 16-bit RCA was obtained by calculating the real speed F of the circuit, given the different supply current I.

Solution:

power consumption management

• power down , sleep transistors,

• switching activity improvement

• …

Power vs. Frequency

1.00E-07 1.00E-06 1.00E-05 1.00E-04 1.00E-03 1.00E-02 1.00E-01 1.00E+00

0.00E+00 5.00E+01 1.00E+02 1.50E+02 2.00E+02

Frequency(MHz)

Power(Watt)

CSL(Static) CSL(Dynamic )

SCMOS(static +dynamic) 乘幂 (CSL(Dynamic )) 乘幂 (SCMOS(static +dynamic))

乘幂 (CSL(Static))

MICAS Department of Electrical Engineering (ESAT)

Spectrum Analysis of di/dt

10⁵ 10⁶ 10⁷ 10⁸ 10⁹ 10¹⁰

70 80 90 100 110 120 130 140

150 Power Spectral Analysis of the CMOS 16-bit RCA

Frequency (Hz)

Power

10⁵ 10⁶ 10⁷ 10⁸ 10⁹ 10¹⁰

40 50 60 70 80 90 100 110 120

Power Spectral Analysis of The Current Steering 16-bit RCA

Frequency (Hz)

Power

30db

decrease

MICAS Department of Electrical Engineering (ESAT)

Variants of CMOS inverter

Ground

V

C

C

Input Output

Local VDD

Local VDD

Ground

V

Cdecouple

C

Input Output

Local VDD

Local VDD

Variant 1 Variant 2

MICAS Department of Electrical Engineering (ESAT)

The effect of decoupling capacitance

 Time domain

10fF 100fF

1pF

10pF

100pF 1nF

MICAS Department of Electrical Engineering (ESAT)

The effect of decoupling capacitance

 Frequency domain

Bit rate=100MHz

MICAS Department of Electrical Engineering (ESAT)

CSL D-type Flip-Flop

CSL inverter CSL inverter

V_DD

D_bar D_bar

clk

clk

D

Vbias

clk_bar

Vbias

clk_bar

Gnd

Gnd

Gnd

Gnd Gnd

Gnd

Q

master slave

MICAS Department of Electrical Engineering (ESAT)

Clock=50MHz

Comparison of D-FF Spectrum, CSL vs. SCMOS

38dB reduction

MICAS Department of Electrical Engineering (ESAT)

Intentional clock skew

 Principle

 Circuit under Simulation Q

Q

SET

CLR

D

Variable Delay Cell

Q Q

SET

CLR

D

set

set

Q1

Q0 Clock

2-bit Toggle flip-flop

Clock 1

Clock 2

Tdelay

Tdelay Clock 1

Time(ns) Clock 2

MICAS Department of Electrical Engineering (ESAT)

The effect of clock skew on the reduction of di/dt

No skew

120ps skew

• Time domain

MICAS Department of Electrical Engineering (ESAT)

The effect of clock skew on the reduction of di/dt

• Frequency domain

MICAS Department of Electrical Engineering (ESAT)

Spread Spectrum Clocking ---SSC

1. Frequency modulating(FM) the clock signal with a unique modulating waveform.

2. The total power of the switching noise remains the same.

Figure 1. Frequency domain representation at

a harmonic of a clock signal with and without SSC Figure 2. Time domain representation of the modulated clock signal

Hardin, K.B. Fessler, J.T. Bush, D.R., ” Spread spectrum clock generation for the reduction of radiated emissions”, IEEE International Symposium on Electromagnetic Compatibility, 1994, pp 227-231

MICAS Department of Electrical Engineering (ESAT)

Digital Pseudo Random Modulation-PRM

Figure 3 Circuit implementation of PRM

Figure 4 Timing diagram of PRM

MICAS Department of Electrical Engineering (ESAT)

Spread Spectrum Clock

0 10 20 30 40 50

1 2 3 4 5 6 7 8

clock

MHz

Spr eadi ng per cent age

0%

1%

2%

3%

4%

5%

6%

1 2 3 4 5 6 7 8

cl ock

Percent

Test circuit

F

= 40MHz F

= 1GHz N=3,M=8

Q Q

SET

CLR

D

Combinational

logic 1 Combinational

logic 2 Q

Q

SET

CLR

D

Q Q

SET

CLR

D

Q Q

SET

CLR

D Combinational

logic 3 Combinational

logic 4

set

SSC-Clock

Digital Pseudo-Random Modulation Clock Generator

Fclk_prm

Figure 5 Test circuit under simulation

MICAS Department of Electrical Engineering (ESAT)

Comparison of Spectrum

Spread Spectrum

Clock

Regular Clock

12dB reduction

Figure 6 Spectrum from 300MHz to 800MHz Zoom in

promising