Design-In for EMC on digital circuit

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MICAS Department of Electrical Engineering (ESAT)

Design-In for EMC on digital circuit

October 27th, 2005

AID–EMC: Low Emission Digital Circuit Design

Junfeng Zhou Wim Dehaene

KULeuven ESAT-MICAS

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Outline

1. Introduction

2. Logic family selection

3. Clock strategy selection (not discuss today due to lack of time) 1. clock skew

2. SSCG

3. Delay cell array approach

4. Low noise power supply – EMI reducer 1. continuous time

2. stability analysis 3. future work

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Part I: Introduction

 Electro-Magnetic Interference (EMI) and radiated emission have become a major problem for high speed digital circuit,

 Most of them are due to power and ground fluctuation.

 Although the detailed calculation of EMI noise is rather difficult , we can use the di/dt as the index, since the current loop

contributes the EMI.

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Part 2: Logic Family Selection

SCMOS PNMOS RSBCMOS

CSL MCML FSCL

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Comparison of di/dt ,power and area

Target : Mixed-Mode Automotive Electronics Design Key aspects : di/dt + Power + Area + Speed

Peak to Peak value of di/dt

1.0E+00 1.0E+01 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07

SCMOS PNMOS RSBMOS CSL MCML FSCL

di/dt [A/s]

Inv erter Power in different logic techniques

0.00E+00 5.00E+01 1.00E+02 1.50E+02 2.00E+02 2.50E+02

Power [μW]

Inv erter area in different logic techniques

0 0.5 1 1.5 2 2.5 3 3.5 4

Area [μm2]

Ring Oscillator of 21-stages

(Static + Dynamic)

Current Steering Logic

But there is static power !!

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Detailed comparison of CSL and SCMOS

0 20 40 60 80 100 120 140 160 180

10^-6 1x10^-5 1x10^-4 10^-3

Frequency [ MHz ]

Power consumption [ W ]

CSL dynamic power

CSL static power CSL dynamic power CSL power

(activity=0.5) SCMOS power (activity=0.5)

SCMOS power activity=0.5 CSL power activity=0.5 CSL static power

V_DD=1.5v

Note:

The curve of CSL 16-bit RCA was obtained by calculating the real speed F of the circuit, given the different supply current I.

CSL

One-bit Adder

IT is a static power problem, Switching off when standby ?

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Detailed comparison of CSL and SCMOS

SCMOS

CSL

SCMOS

CSL

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Problem with CSL



Mismatch sensitive, annoying for standard cells



rather slow/power hungry



Not full swing

Matching required!

M1 > M3

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Can we do it better ?



C-CBL:

 sizing for optimal current balance is really difficult ,process dependent

CBL

[Albuquerque, E.F.M.; Silva, M.M., Current-balanced logic for mixed-signal IC's]

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Solution- Enhanced current steering logic

 Still current source basing

 Increase in logic level, hence increase the robustness

 Reduced output capacitance, hence the speed is increased

Fig.3 E-CSL inverter

Minimum size

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Comparison of CSL, C-CBL,

ECSL and SCMOS

10M 100M 1G 10G

1 10 100 1k 10k 100k 1M 10M 100M

CSL C-CBL E-CSL SCMOS V_DD=3 v C_LOAD=5 fF

F [Hz]

di/dt p-p [A/s]

Fig.5 di/dt vs. frequency Fig.4 power vs. frequency

10M 100M 1G 10G

1E-7 1E-6 1E-5 1E-4

1E-3 Area@500 MHz

CSL 7.2 um² C-CBL 2.1 um² E-CSL 1.53 um² SCMOS 6.5 um²

V_DD=3 v C_LOAD=5 fF

Power [w]

F [Hz]

CSL C-CBL E-CSL SCMOS

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di/dt performance vs.

process variation

10M 100M 1G 10G

10 100 1k 10k 100k 1M 10M

100M V_DD=3 v C_LOAD=5 fF

TT FF FS SF SS F [Hz]

di/dt p-p [A/s]

CSL

10M 100M 1G 10G

10 100 1k 10k 100k 1M 10M

TT FF FS SF SS F [Hz]

di/dt p-p [A/s]

E-CSL

10M 100M 1G 10G

10 100 1k 10k 100k 1M 10M

TT FF FS SF SS

F [Hz]

di/dt p-p [A/s]

C-CBL

10M 100M 1G 10G

10 100 1k 10k 100k 1M 10M

TT FF FS SF SS di/dt p-p [A/s]

F [Hz]

SCMOS

Fig.6 di/dt vs. process corner

MAX di/dt change

MIN di/dt change

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Conclusion of Low noise Logic Families

Winner is E-CSL

 CSL,E-CSL show a smaller area per logic function for complex digital gates and systems compared to SCMOS logic technique.

 Current source ensures the major di/dt reduction,

 Process variation sensitivity also becomes better due to the dominance of current source,

 E-CSL gives comparable di/dt performance with CSL,

 E-CSL is Faster and Less power consuming than CSL due to the lower area and lower capacitance.

 Static power consumption remains the challenge for wide application of the CSL,E-CSL technique in very large

digital systems. Can be solved by using power down strategies, which is highly application dependent

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Part 4: Low Noise Power Supply design

However 2 problems still remain:

• Static power consumption

• New logic family standard cell library must be

designed and characterised. (large NRE cost, risk)

?? Is there any global approach ??

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Principles of Low Noise Power supply

Fig.9 Diagram of Low noise power supply

1. Current source ensures the major di/dt reduction

2. Do not give more current than the circuit needs, i.e.

minimize the static current 3. Slow varying is key to EMC

success

1. Can be done with switched or

continuous mode.

Both are studied, 2. Continuous mode

potentially has better di/dt suppression.

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Continuous mode Power Delivery

Fig.13 Continuous time power delivery system

Determine the switching speed, Hence determine the di/dt

Energy reservoir when slow Switching

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Functionality Simulation

Fig.14 Functionality simulation of continuous time power delivery system

continuous time OTA feedback loop stable

Idd

di/dt

Vcontrol VDD_input 9v

2^nd order under damped behaviour , still under study

VDD_input

Vcontrol

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Comparison with standard CMOS

Fig.15 di/dt and FFT comparison with standard CMOS w/o CT, 3.3V only

12v supply current

12v supply current di/dt ^p-p = 1.0x10⁷^A/s di/dt w/o CT, di/dt ^p-p =1.51x10¹¹ A/s

162 times= 44dB

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Stability analysis - Small signal analysis

1 Gota

p  Caux ²

1 2 1

tan * 1

3, 4

1 2

2 1 *( 3 )*

( tan 1* )* * 3* *

p Gota

Caux p Gds

C k M Cgd p p

M gm gm

p Gds gm Gdg Caux

GBW C k Cgd M Gm gm M Gdg

 

  



 



dominant pole

second-dominant pole high frequency poles

mirror factor

p1

p2 p4 p3

>3 for > 72° phase margin (2^nd order system)

Approximation:

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Stability analysis- Calculation vs. Simulation

Maple Spectre --- DC gain(dB): 97.72 97.25 --- Phase Margin(degree): 62.5 49 --- Gain Crossover(Hz): 325K 275K --- P2/GBW: 1.275 1.264 ---

(dB)

(deg)

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Trade-off in Ctank and Caux

P2/GBW P2/GBW

3 3

2 1 *(2 3 )*

( tan 1* )* * 3* *

p Gds gm Gdg Caux

GBW C k Cgd M Gm gm M Gdg

 



Ctank=100pF Caux=100pF

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Current pulse step response

10 ( / )9

di A s

dt 

1.35 10 ( / )5

di A s

dt  

An input current step of 1 mA and 100-ps rise time was used for the calculation and simulation

10 ( / )9

di A s

dt 

Can be improved if more stable

~10⁴reduction !!

1.38 10 ( / )5

di A s

dt  

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Coupling problem !

Cgs_1,2 ≈ Cgd1

∆ V_{DD_input}

∆ V_bias

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Future work



Improve circuit structure to reduce coupling between output node and gate of the current source transistor



Figure out supply current behaviour of a typical AMIS digital block



Add a real voltage regulator into consideration

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Design-In for EMC on digital circuit