Temperature differences influence the behavior of semiconductors. It is important to check the mea-sured temperature dependence with the expectancy from literature. The temperature dependence can be found in the intrinsic carrier concentration ni via the mass action low (equation (32)). The bandgap energy Eg is also dependent on temperature via equation (34), where Eg(0) = 1.169eV α = 4.9 · 10−4eV /K and β = 655K for Silicon [9]. The intrinsic carrier concentration scales with the saturation current via equation (11). Figure 5.45 shows the saturation current I0as a function of temperature. In addition, if one takes I0 at 0◦C, the increase in I0 with temperature can be determined with equation (35) [9]. It can be seen in Figure 5.45 that the measured increase of I0
with temperature indeed follows equation (35) and thus the temperature dependent behavior is as expected. This expected behavior is also incorporated in the models design engineers use to model the IC circuit.
Figure 5.46 shows the series resistance with temperature, it can be seen that the series resistance is not greatly affected by the temperature.
n2i = n · p = NCNVexp −(Eg)
Figure 5.45: The saturation current I0as a function of temperature; measured data compared with the expected increase from literature of equation (35). The error bars represent two times the standard deviation of 5 devices on the wafer.
Figure 5.46: The series resistance Rs with temperature. Rsis not greatly affected by the tempera-ture. The error bars represent two times the standard deviation of 5 devices on the wafer.
6 Conclusion
The main objective of this research was to make a proposition for the most optimal PiN diode regarding the lowest Figure Of Merit (FOM) and highest breakdown voltage (BV). The variations in the PiN diode structure that have been studied are the anode area, parallel structures, the EPI thickness and the PPLUS v.s. PSB diodes.
Increasing the anode area mainly aims at decreasing Ron. Ron does decrease, however; Ron does not scale directly proportional with 1/anode area. This is due to the non linear scaling of the series resistance Rs with 1/anode area. Rs is higher for big diodes than expected and this is because of the favorable path around the STI for the current to flow. With this favorable path, only the edge of the anode area is effectively used. This phenomena has more consequences for big diodes than for small diodes. In addition, Cof f does increase directly proportional with the anode area. Therefore, the FOM increases with the anode area and thus this is not an effective way to optimize the FOM. When using small diodes, the FOM is the most optimal but the insertion loss can be too high due to the rather high Ron. Therefore, it is evaluated if parallel structures can effectively decrease Ron.
Using parallel structures aims at decreasing Ronwith a factor of the number of parallel diodes.
However, Cof f is increasing with the same factor and thus the FOM is constant. For the parallel structures, NXP has designed two type of diodes. Firstly, by putting only the anode in parallel with so-called parallel fingers. It has been shown that using parallel fingers is not effective; this does not represent a parallel structure but has the same effect as scaling the anode area. Secondly, putting both the anode and cathode in parallel with so-called parallel cells is more effective than using the parallel fingers. However, the FOM is still increasing with the cells. This is because not the whole diode is perfectly parallel; the cathode located between the diodes are not doubled and thus two diodes share a part of the cathode together; this makes Ron not decrease effectively.
Therefore, it has been shown with simulation that if the complete diode is put in parallel and the cathode between the diodes is doubled, Ron and Cof f scale with the cells as expected and the FOM is approximately constant. Thus, if designed properly, parallel cells are an effective way of decreasing Ron. However, Cof f should not increase too much; especially at high frequencies the isolation becomes too low. Therefore, it is evaluated if increasing the EPI thickness is an effective way to decrease Cof f.
Increasing the EPI thickness aims at decreasing Cof f and increasing the breakdown voltage.
However, Ron also increases with the EPI thickness. It has been shown that the decrease of Cof f
is more dominant than the increase of Ron and thus the FOM decreases with the EPI thickness.
However, by making the EPI too thick, the insertion loss can become too high especially at low frequencies. With increasing the default EPI thickness from 0.63 µm to 0.73 µm the FOM already decreases from 197 fs to 146 fs and the BV increases from -5.3V to -8V. Thus, this is an effective way of decreasing Cof f and increasing the BV, while not compromising too much on the insertion loss. However, increasing the EPI thickness means increasing the EPI thickness for all the devices on the chip. Therefore, further research is needed to evaluate if the performance of the other devices is not decreased significantly.
Another way to optimize both Ron and Cof f is to make use of PSB diodes instead of the de-fault PPLUS diodes. With the PSB diodes, the anode is made of poly-Si and the EPI is effectively thicker. Unfortunately, no RF measurements could be performed on the PSB diodes. However, from DC measurements follows that Rs does not increase significantly and the BV increases from -5.3 to -5.6V. Additionally, from literature study it is expected that Cof f will decrease due to the effectively thicker EPI. However, due to this thicker EPI, Ron will increase but, it also expected that Ron decreases due to better diffusion through the poly-Si crystal. Further research is needed with RF measurements to evaluate the PSB diodes.
The main question that now remains is; what is the most optimal PiN diode to use? In terms of the EPI thickness it is worth it to increase to 0.73 µm if this is allowed considering the other devices on the chip. In terms of the area and number of parallel diodes; there is not one answer to this question. It depends on the application and the requirements for the insertion loss and isolation and on the operating frequency. The insertion loss and isolation both decrease with frequency.
Therefore, at high frequencies the isolation can become too low. However, parameters of the anode area and number of parallel structures are accessible by the design engineers during the design process. Therefore it is important to equip the design engineers with a model that the describes
the behavior of the PiN diode precisely. For example, the non-linear scaling of Rs is now not equipped in the available model. Also, when making use of parallel structures it is important to develop the proposed parallel structure where the whole diode is in parallel. Otherwise, the model again does describe the parallel behavior correctly. The model can be used to model the whole switch configuration. This is important because the IL and ISO are not only determined by the PiN but also by the IL and ISO of the complete TX or RX path of the switch configuration. When the design engineer has the proper model, he or she can study the whole switch configuration and choose the most optimal PiN diode for the set requirements.
Also, before the PiN diode can be implemented various problems still have to be faced and this research needs to be extended.
7 Outlook
To further research the most optimal PiN diode three main recommendations can be made.
Firstly, the PSB diodes have to be evaluated with RF measurements to study if there is an advantage over the PPLUS diodes.
Secondly, it is recommended to include a dedicated-short de-embedding structure. De-embedding is now done with generic open, generic short and dedicated-open structures. With this, the mea-surements are corrected for external capacitance’s, series resistances of the cables and bias tees, external inductions and internal capacitance’s respectively. However, with a dedicated-short struc-ture one can also de-embed the internal induction due to the metal contacts. This induction influences the diode behavior at high frequencies. With the dedicated-short de-embedding equa-tion (27) can be extended to equaequa-tion (36). With ZDS as the impedance of the dedicated-short, which also has to be de-embedded itself with the generic open, generic short and dedicated open.
YDU T = YDU T 1− YDO (26)
YDU T =h
(YDU T 1− YDO)−1− ZDS−1i−1
(36) If the induction is de-embedded the RF measurements can be confidently analyzed at higher frequencies. In this research the analysis were done at 2 GHz and 10 GHz but in reality the operating frequency of the PiN diode will be above 20 GHz. Thus, it is important to do analysis at high frequencies and to include a dedicated-short structure. Therefore, the next batch of wafers will include this dedicated-short structure.
Thirdly, it is recommended to further study the parasitic PN junction at the connection be-tween the PiN diode and the substrate. In this research the focus has been on the behavior bebe-tween anode and cathode. However, this substrate connection also influences the behavior of the diode.
Therefore, it is beneficial to study if this leakage path can be optimized.
The TCAD simulations could also have a predicting function. When the simulations predict the PiN behavior correctly, one could do further research on the process parameters optimization.
For this the TCAD simulations should be calibrated and optimized with the measurements and extended with more physical models.
In addition, the compact model for the design engineers should be adjusted such that it describes the PiN diode characteristics evaluated in this research. Such as the non-linear scaling of the series resistance. This non-linear scaling can be precisely evaluated with TCADs if the simulations are calibrated.
In March 2021 Foissey et al proposed an innovative BiCMOS PiN diode (Figure 7.1). With this technology, the PiN is made horizontally instead of vertically. The result is that the series resistance Rs is reduced and thus the FOM decreases. In this paper they achieve a FOM of 85 fs at a forward bias of 8 mA [3]. Therefore, this design of the PiN diode is worth investigating in the future to reduce Ron further. Fortunately, these type of diodes are already available at NXP and will be analysed in the near future.
Figure 7.1: The innovative BiCMOS PiN diode proposed by Foissey et al. [3]
8 References
[1] Yunyi Gong, Jeffrey W Teng, and John D Cressler. “A Compact, High-Power, 60 GHz SPDT Switch Using Shunt-Series SiGe PIN Diodes”. In: 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). IEEE. 2019, pp. 15–18.
[2] Ericsson mobility report, November 2020. url: https://www.ericsson.com/en/mobility-report/reports. (Accessed: 11/04/2021).
[3] O Foissey et al. “85 fs R ON× C OFF and CP 1dB@ 28GHz¿ 25dBm Innovative PIN Diode Integrated in 55 nm BiCMOS Technology Targeting mmW 5G and 6G Front End Module”.
In: 2021 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF). IEEE. 2021, pp. 40–43.
[4] The teardown report of the Samsung Galaxy Fold. url: https : / / www . ifixit . com / Teardown/Samsung+Galaxy+Fold+Teardown/122600. (Accessed: 11/04/2021).
[5] NXP Semiconductors. WLAN7001C: WLAN 5 GHz Front-end IC. url: https://www.nxp.
com/products/radio-frequency/wlan-front-end-ics-and-modules/wlan7001c-wlan-5-ghz-front-end-ic:WLAN7001C. (Accessed: 29/03/2021).
[6] L. De Xing et al. “Design of front end of a RF receiver”. In: (2009), pp. 533–536.
[7] B Jayant Baliga. Fundamentals of power semiconductor devices. Springer Science & Business Media, 2010.
[8] Josef Lutz et al. “Semiconductor power devices”. In: Physics, characteristics, reliability 2 (2011).
[9] Simon M Sze and Kwok K Ng. Physics of semiconductor devices. John wiley & sons, 2006.
[10] Robert H Caverly. Microwave and RF semiconductor control device modeling. Artech House, 2016.
[11] Kurt A. Moen et al. “0.18µm SiGe BiCMOS technology for fully-integrated front-end ICs capable of sub-300fs Ron × Coff switch performance”. In: 2015 IEEE Bipolar/BiCMOS Circuits and Technology Meeting - BCTM. 2015, pp. 109–112. doi: 10.1109/BCTM.2015.
7340562.
[12] A. Uhlir. “The Potential of Semiconductor Diodes in High-Frequency Communications”. In:
Proceedings of the IRE 46.6 (1958), pp. 1099–1115.
[13] M. E. Hines. “Fundamental limitations in RF switching and phase shifting using semicon-ductor diodes”. In: Proceedings of the IEEE 52.6 (1964), pp. 697–708.
[14] D Leenov. “The silicon PIN diode as a microwave radar protector at megawatt levels”. In:
IEEE transactions on electron devices 11.2 (1964), pp. 53–61.
[15] Donald A. Neamen. Semiconductor physics and devices: basic principles. Mcgraw hill higher education, 2012.
[16] H. A. Schafft. “Second breakdown—A comprehensive review”. In: Proceedings of the IEEE 55.8 (1967), pp. 1272–1288.
[17] Wallace B Smith, Duane H Pontius, and PAUL P Budenstein. “Second breakdown and damage in junction devices”. In: IEEE Transactions on Electron devices 20.8 (1973), pp. 731–
744.
[18] ML Lucia et al. “Capacitance measurements of pn junctions: depletion layer and diffusion capacitance contributions”. In: European journal of physics 14.2 (1993), p. 86.
[19] Ranbir Singh and B. Jayant Baliga. “P-I-N Diode”. In: Cryogenic Operation of Silicon Power Devices. Boston, MA: Springer US, 1998, pp. 37–48.
[20] K Taretto, U Rau, and JH Werner. “Closed-form expression for the current/voltage charac-teristics of pin solar cells”. In: Applied Physics A 77.7 (2003), pp. 865–871.
[21] James F Gibbons. “Ion implantation in semiconductors—Part I: Range distribution theory and experiments”. In: Proceedings of the IEEE 56.3 (1968), pp. 295–319.
[22] Scotten W Jones. “Diffusion in silicon”. In: IC Knowledge LLC (2008), pp. 23–61.
[23] PA Stolk et al. “Physical mechanisms of transient enhanced dopant diffusion in ion-implanted silicon”. In: Journal of Applied Physics 81.9 (1997), pp. 6031–6050.
[24] Ted Kamins. Polycrystalline silicon for integrated circuit applications. Vol. 45. Springer Sci-ence & Business Media, 2012.
[25] Susumu Namba and Kohzoh Masuda. “Ion Implantation in Semiconductors”. In: Advances in Electronics and Electron Physics. Vol. 37. Elsevier, 1975, pp. 263–330.
[26] V Probst et al. “Analysis of polysilicon diffusion sources”. In: Journal of The Electrochemical Society 135.3 (1988), p. 671.
[27] CascadeMicrotech. Datasheet CM300 probe station. url: https://www.formfactor.com/
download / cm300xi - data - sheet / ?wpdmdl = 3294 & refresh = 5f9002deefe0b1603273438.
(Accessed: 14/10/2020).
[28] The CascadeMicrotech infinity probe. url: https : / / www . formfactor . com / product / probes/infinity/infinity-probe/. (Accessed: 19/04/2021).
[29] Datasheet Keysight PNA network analyzer N5227A. url: https://www.keysight.com/nl/
en/assets/7018-01609/technical-overviews/5989-6841.pdf. (Accessed: 28/04/2021).
[30] Keysight Technologies. Datasheet B1500A Semiconductor Device Analyzer. url: https://
www.keysight.com/us/en/assets/7018-01289/data-sheets/5989-2785.pdf. (Accessed:
14/10/2020).
[31] Keysight Technologies. Technical overview IC-CAP Device Modeling Software. url: https:
//www.keysight.com/us/en/assets/7018- 06692/technical- overviews/5965- 7742.
pdf. (Accessed: 21/10/2020).
[32] P. Hruska, Z. Chobola, and L. Grmela. “Diode I-U Curve Fitting with Lambert W Function”.
In: 2006 25th International Conference on Microelectronics. 2006, pp. 468–471. doi: 10.1109/
ICMEL.2006.1651003.
[33] M Khalis et al. “Two methods for extracting the parameters of a non-ideal diode”. In:
International Journal of Physical Sciences 10.8 (2015), pp. 270–275.
[34] William T Joines, William Devereux Palmer, and Jennifer Lyn Truman Bernhard. Microwave transmission line circuits. Artech House, 2012.
[35] Dean A Frickey. “Conversions between S, Z, Y, H, ABCD, and T parameters which are valid for complex source and load impedances”. In: IEEE Transactions on microwave theory and techniques 42.2 (1994), pp. 205–211.
[36] M.C.A.M. Koolen, J.A.M. Geelen, and M.P.J.G. Versleijen. “An improved de-embedding technique for on-wafer high-frequency characterization”. In: Proceedings of the 1991 Bipolar Circuits and Technology Meeting. 1991, pp. 188–191. doi: 10.1109/BIPOL.1991.160985.
[37] L.F. Tiemeijer and R.J. Havens. “A calibrated lumped-element de-embedding technique for on-wafer RF characterization of high-quality inductors and high-speed transistors”. In: IEEE Transactions on Electron Devices 50.3 (2003), pp. 822–829. doi: 10.1109/TED.2003.811396.
[38] BR de Souza, Wilson A Artuzi Jr, Marlio JC Bonfim, et al. “A PIN diode model for finite-element time-domain simulations”. In: Journal of Microwaves, Optoelectronics and Electro-magnetic Applications (JMOe) 8.1 (2009), 38S–48S.
[39] Basic TCAD solver. url: http://www.flooxs.ece.ufl.edu/index.php?title=Device_
Simulation_Overview&oldid=562. (Accessed: 29/04/2021).
[40] Jelke Toonen, Ir A Mels, and Ir HGA Huizing. “Improving low-voltage integrated power devices”. In: ().
[41] K Sentaurus Device User Guide. “SP1”. In: Synopsys, Mountain View, CA, USA (2015).
[42] D.B.M. Klaassen. “A unified mobility model for device simulation—I. Model equations and concentration dependence”. In: Solid-State Electronics 35.7 (1992), pp. 953–959.
[43] N Convers Wyeth. “Sheet resistance component of series resistance in a solar cell as a function of grid geometry”. In: Solid-State Electronics 20.7 (1977), pp. 629–634.