MASTER
Critical analysis of the device optimization for the PiN diode as RF switch
Römkens, Demi D.I.A.
Award date:
2021
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Author
Demi R¨ omkens 1387200
University Supervisor Prof. Dr. Paul Koenraad External Supervisor Dr. Ir. Peter Magn´ ee
University of Technology, Eindhoven Faculty of Applied Physics
Nanoscience and Technology
Photonics and Semiconductor Nanophysics
NXP Semiconductors, Nijmegen Front End Innovation
RF technology
July 1, 2021
This public master thesis represents a studyload of 60 ECTS and follows the TU/e Code of Scientific Integrity
Author
D.D.I.A. R¨omkens
MSc student Applied Physics 1387200
Eindhoven University of Technology Faculty of Applied Physics
Department of Nanoscience and technology
Research group Photonics and Semiconductor Nanophysics (PSN) demiromkens@hotmail.com
External supervisor Dr. Ir. P.H.C. Magn´ee
Technical Director RF Technology NXP Semiconductors Nijmegen Front End Innovation
RF technology
peter.magnee@nxp.com
University supervisor Prof. Dr. P.M Koenraad
Eindhoven University of Technology Faculty of Applied Physics
Department of Nanoscience and technology
Research group Photonics and Semiconductor Nanophysics (PSN) p.m.koenraad@tue.nl
Thesis Committee Prof. Dr. A. Fiore Dr. J.E.M. Haverkort
ogy Eindhoven (TUe). The research is conducted at NXP semiconductors Nijmegen, Netherlands, and focuses on the I-V and small signal characterization of PiN diodes for RF switches. The end result presents the most optimal device geometry for the PiN diode. During this research I learned to work independently and developed a hands-on mentality by working on a practical problem in the semiconductor industry. The end result of this research and my personal development is also achieved by the optimal supervision and assistance of my supervisors and colleagues of the Front-End innovation team at NXP. Therefore, I want to thank the whole team for making me feel welcome and helping me whenever needed, even though the circumstances were not always op- timal due to the COVID-19 pandemic. Additionally, I want to thank a few people on a specific note.
First I would like to thank Peter Magn´ee and Alessandro Baiano for their daily supervision.
Both Peter and Alessandro created a good learning environment with frequent supervision but also taught me to work independently. The supervision had to switch between online and offline multiple times but we managed to make it work. Unfortunately, Alessandro chose for another career opportunity during my research and Peter took the full supervision on him. This did not have a negative influence on the project progression, for which I thank Peter specifically.
Secondly, I want to show my appreciation to Thanh Viet Dinh for helping me with my TCAD simulations after Alessandro left the team. Viet pushed me to explore the process simulation myself, which was not always easy but with his assistance I learned a lot about simulating a semi- conductor process in TCAD.
Thirdly, I want to thank Ihor Brunets and Maarten Swaanenberg for helping me with the RF measurements and DC measurements respectively. The effort and time they invested in assisting me is greatly appreciated.
At Last, thanks to Prof. Paul Koenraad of the TUe for connecting me with NXP semiconduc- tors and for our monthly meetings which kept me focused on the end-goal of the research.
Demi R¨omkens Eindhoven, June 2021
puts pressure on the industry to develop innovative electronic technologies, typically consisting of Integrated Circuits (IC) which is also known as a chip. An important chip on the main board of a smartphone is the front-end module which is responsible for wireless communication. This module is equipped with a Single-Pole-Double-Throw (SPDT) switch [1], making it possible to switch between receiving or transmitting a signal via the corresponding antenna. In this research, a PiN diode is studied as RF switch, representing an open or closed switch upon reverse of forward bias respectively. The most important parameters of the PiN diode are the on-resistance Ron, the off-capacitance Cof f and the breakdown voltage BV. Ron and Cof f represent the Figure of Merit F OM = Ron· Cof f. In this research 4 categories of device optimization for the PiN diode are evaluated with DC and RF measurements; anode area scaling, using parallel structures, EPI thickness scaling and PPLUS v.s. PSB diodes.
Increasing the anode area mainly aims at decreasing Ron. This research shows that increasing the anode area is not effectively decreasing Ron. Ron does decrease, however; Ron does not scale directly proportional with 1/anode area. This is due to the non linear scaling of the series resistance Rswith 1/anode area. Rsis higher for big diodes than expected due to the favorable path around the STI for the current to flow. With this favorable path, only the edge of the anode area is effectively used. In addition, Cof f does increase directly proportional with the anode area.
Using parallel structures aims at decreasing Ronwith a factor of the number of parallel diodes.
However, Cof fis increasing with the same factor and thus the FOM is constant. It has been shown with simulation that if the complete diode is put in parallel and the cathode between the diodes is doubled, Ron and Cof f scale with the cells as expected and the FOM is approximately constant.
NXP has designed two type of diodes to achieve a parallel structure in practice. Firstly, by putting only the anode in parallel with so-called parallel fingers. It has been shown that using parallel fingers is not effective; this does not represent a parallel structure but has the same effect as scaling the anode area. Secondly, putting both the anode and cathode in parallel with so-called parallel cells is more effective than using the parallel fingers. However, the FOM is still increasing with the cells. This is because not the whole diode is perfectly parallel; the cathode located between the diodes are not doubled and thus two diodes share a part of the cathode together. Therefore, the structures presented by NXP are not an efficient method to achieve parallel structures.
Increasing the EPI thickness aims at decreasing Cof f and increasing the breakdown voltage.
However, Ron also increases with the EPI thickness. It has been shown that the decrease of Cof f
is more dominant than the increase of Ron and thus the FOM decreases with the EPI thickness.
Thus, increasing th EPI thickness is very effective for decreasing Cof f; With increasing the default EPI thickness from 0.63 µm to 0.73 µm the FOM decreases from 197 fs to 146 fs and the BV increases from -5.3V to -8V.
With PSB diodes one can optimize both Ron and Cof f. With the PSB diodes, the anode is made of poly-Si and the EPI is effectively thicker. Unfortunately, only DC measurements are performed on the PSB diodes. For RF measurements it is expected that Cof f will decrease due to the effectively thicker EPI. However, due to this thicker EPI, Ronwill increase but, it also expected that Ron decreases due to better diffusion through the poly-Si crystal. It is recommended to do further research with RF measurements on the PSB diodes.
Thus, this research has shown that using parallel structures and increasing the EPI thickness are the most efficient ways to decrease Ron and Cof f respectively. Furthermore, the most important recommendation is to perform RF analysis on the PSB diodes. The PSB diodes are promising and could decrease the FOM further.
1.1 Market demand . . . 1
1.2 Switching concept . . . 1
1.3 Research outline . . . 3
2 Physical background 5 2.1 PN diode . . . 5
2.1.1 Structure of the PN junction . . . 5
2.1.2 Biasing the PN junction . . . 6
2.1.3 Current-Voltage characteristics . . . 7
2.1.4 Small signal model . . . 8
2.2 PiN diode . . . 9
2.2.1 Characteristics . . . 9
2.2.2 Process flow of the PiN diode . . . 11
2.3 Doping profiles . . . 12
2.3.1 Diffusion after implantation . . . 13
2.3.2 Diffusion in single-crystalline silicon and poly-crystalline silicon . . . 13
2.3.3 Junction capacitance for realistic doping profiles . . . 15
3 Experimental methodology 16 3.1 Measurement equipment and set-up . . . 16
3.1.1 DC probe station . . . 16
3.1.2 RF probe station . . . 17
3.1.3 Device analyzer, network analyzer and software . . . 19
3.2 DC measurement . . . 19
3.3 RF measurement . . . 19
3.4 Test structures . . . 23
4 Simulation Methodology 26 4.1 Process simulation . . . 26
4.2 Physics . . . 26
4.3 Electrical simulations . . . 27
4.3.1 DC simulations . . . 27
4.3.2 RF simulations . . . 28
5 Results and discussion 30 5.1 Behavior of the PiN diode . . . 30
5.2 Area scaling . . . 34
5.2.1 DC measurements . . . 34
5.2.2 RF measurements . . . 36
5.3 Parallel structures . . . 40
5.3.1 Parallel fingers . . . 40
5.3.2 Parallel Cells . . . 42
5.4 EPI thickness . . . 47
5.4.1 DC measurements . . . 47
5.4.2 RF measurements . . . 48
5.5 PPLUS v.s. PSB diodes . . . 50
5.6 Temperature scaling . . . 52
6 Conclusion 54
7 Outlook 55
8 References 57
1 Introduction
1.1 Market demand
In 2020, the COVID-19 pandemic changed the way we work and live inevitably and society took a giant leap forward in the process of digitalization. For this digitalization process, good connectivity is an essential element and the demand for fast wireless communication by society continues to grow. This increasing demand is clearly visible in the Ericsson Mobility reports; the subscription uptake for 5G is significantly higher than that for 4G when it was launched in 2009 and 2.6 billion 5G subscriptions are expected by 2026 [2]. With 5G, higher data rate wireless technologies are enabled by moving to higher frequencies [3]. This increasing demand puts pressure on industries like NXP Semiconductors to develop innovative sophisticated electronic technologies.
Electronic technologies typically consist of an Integrated Circuit (IC), also known as a chip. The chip is made of a semiconductor material (typically silicon). These chips are implemented in smart- phones that are used for wireless communication. The most important chips of a smartphone can be recognized when looking at the main board of a typical smartphone. Figure 1.1 shows the main board of Samsung’s Galaxy Fold [4].
Figure 1.1: Teardown of Samsung’s Galaxy Fold; the main board [4]
From Figure 1.1 it can be recognized that the front-end module is placed on the main board multiple times. The front-end module is responsible for the wireless communication, and the mod- ule of interest in this research. A front-end module developed by NXP is the WLAN7001C WLAN 5 GHz Front-end IC [5] which is for instance integrated in the Samsung Galaxy Fold.
The heart of the front-end module consists of a power amplifier (PA), a low noise amplifier (LNA) and a Single-Pole-Double-Throw (SPDT) switch. The switch makes it possible to switch between receiving or transmitting a radio frequency (RF) signal through the antenna [6][1]. The next section will explain the switching concept in more details.
1.2 Switching concept
A switch is typically a semiconductor device that exhibits high or low impedance, representing an open or closed switch respectively. Examples of these semiconductor devices are MOS transistors and PiN diodes. The most important electrical parameters of these devices are insertion loss (IL) and isolation (ISO). The insertion loss is used to describe the signal loss between the input and output of the device in forward bias and the isolation describes the attenuation in reverse bias.
Ideally, insertion loss should be as low as possible and isolation as high as possible. However in reality this is not achievable; the two separated contacts create a capacitance Cof f in reverse bias and in forward bias there is an on-resistance Ron. Additionally, in reverse bias the breakdown volt- age (BV ) defines the voltage at which the device conducts a large current and the blocking ability is lost. Therefore, Ron· Cof f is the Figure Of Merit (FOM) for the PiN diode and is, together with BV , an important physical parameter and thus a key design target. However, one must always
look for a trade-off between these parameters. It is very difficult to improve one parameter without comprising another one [7][8][9].
These physical parameters are dependent on the type of device, the geometry of the device and the type of silicon structure used [10]. Additionally, it is also important to consider the topology in which the switch is used.
The general switch topology considered in this research is the single-pole double-throw (SPDT) switch topology. This is a switch topology which has an antenna signal and switches between two modes; receiving (RX) or transmitting (TX) a signal. The RX path consists of a Low Noise Ampli- fier (LNA), which function is to amplify the signal coming from the antenna for further processing.
The TX path consists of a Power Amplifier (PA), which function is to amplify the signal that is sent to the antenna. The SPDT topology is shown in Figure 1.2, note that Figure 1.2 represents the transmitting mode.
Figure 1.2: The Single-Pole Double-Throw topology in the transmitting (TX) mode with a Low Noise Amplifier at the RX path and a Power Amplifier at the TX path.
Figure 1.2 shows four switches, while ideally two switches should be sufficient. However, in practice an open switch is not perfectly open; a small leakage signal is present. This leakage signal is provided to the ground by the additional switch in the RX or TX path. The SPDT topology is clasically achieved by implementing NMOS switches (Figure 1.3). The FOM achieved with the typical NMOS is between 300 and 450 fs [11]. However, the Quality-factor of the series switch in the RX path is decreasing with frequency. Therefore, the so-called lambda/4 topology can be used (Figure 1.4) [1]. In this topology, one makes use of a transmission line of one-quarter of the wavelength (represented by the inductor in Figure 1.4). The lambda/4 topology is suitable for RF frequencies because one-quarter of the wavelength is then small enough to integrate the component on the chip. Note that the maximum operating frequency of the lambda/4 topology is thus dependent on the manufacturing tolerances; how small the component can be made.
Figure 1.3: The classical SPDT switch with implemented NMOS switches. Note that the NMOS is also implemented at the switches in the TX path.
Figure 1.4: The lambda/4 topology with a transmission of one-quarter of the wavelength, displayed here as an induction element.
To improve the lambda/4 topology, a PiN diode is intended to replace the NMOS transistor.
The use of a PiN diode as a RF switch was first mentioned by Uhlir [12]. Since then, PiN diodes have been studied for many applications in a broad frequency spectrum [13][14]. The advantages of the PiN diode are also demonstrated by NXP’s design engineers to have better insertion loss and lower Ron· Cof f value. However, before implementing the PiN diode, RF design engineers should be equipped with enough understanding and research. Therefore, the Front-End innovation RF technology group within NXP requires a full characterization of a variety of PiN diodes, to determine its capabilities and limitations.
1.3 Research outline
In previous years, NXP has started research on the characterization of the PiN diode. This re- search was mainly done to provide a compact model to design engineers. However, the research was not very extensive due to time limits. Therefore, the Front-End innovation RF technology group wants a more extensive research that describes the most optimal PiN diode regarding the lowest FOM and highest BV achievable. This research is continued in this graduation project.
The main objective of this research is to make a proposition for the most optimal PiN diode, with the lowest FOM and highest BV that can be achieved. In this research, the influence of area, par- allel structures, EPI thickness is evaluated. Increasing the area and using parallel structures aims at decreasing Ron, increasing the EPI thickness aims at decreasing Cof f. In addition, PPLUS and PSB diodes are compared; PPLUS diodes have an anode made of mono-Si and PSB diodes have an anode made of poly-Si. Furthermore, a recommendation will be given which other technologies are worth investigating to optimize the PiN diode further.
The PiN diodes are studied with experimental methods in the DC and RF regime. First, the focus will be on the DC characterization of the diode; the Current-Voltage (I-V) characteristics.
Secondly, the RF (small signals) characterization will take place. With the RF characterization, Ron, Cof f, insertion loss and isolation are studied upon different frequencies and voltages. Then, its corresponding results are supported by TCAD simulations.
The research is documented in this thesis, divided in 7 chapters including this first chapter; the introduction.
In chapter two, an overview of the physical background is given that is required to understand the physics involved in this research. Here, the physics of the PN junction, PiN diode, the process flow and the effect of doping profiles is discussed.
In chapter three, the experimental methodology is discussed. First, the used equipment is listed;
the DC and RF probe stations and the corresponding analyzers and software. Secondly, the mea- surement and analysis routine for the DC and RF measurements is explained. Followed by an overview of the available test structures at NXP that will be measured.
Chapter four provides the simulation methodology. Starting with an explanation about the simu- lation tool TCAD and the process flow simulation. Followed by the simulation routine and analysis for the DC and RF simulation that are mimicking the measurements in reality.
Chapter five reports the obtained results via measurements and simulations that are executed to study the optimization of the FOM for the PiN diode with various approaches. The results are divided in 6 sections. First, the general behavior of the diode is shown to validate the I-V curves and the behavior of the diode with frequency. Secondly, the optimization of Ron via area scaling is studied in DC and RF. Thirdly, the optimization of Ron with using parallel diodes is discussed.
Then, varying the EPI thickness is studied to decrease Cof f and increase the BV. Followed by a comparison between PPLUS and PSB diodes. At last, it is checked if the temperature dependent behavior of the diode is as expected.
In chapter six and seven, the conclusion of this research, with an evaluation of the most optimal PiN diode, and the outlook for further research is given respectively.
2 Physical background
In this chapter, the PiN diode is studied upon its capabilities to function as a RF switch. First, the PN diode has to be explained in order to understand the capabilities of the PiN diode to work as a RF switch afterwards. At last, the doping profile throughout the layers of the diode has to be discussed to understand the consequences for the on-resistance and off-capacitance.
2.1 PN diode
The physics of the PN junction is an important basis for the understanding of other semiconductor devices, such as the PiN diode. Therefore, the structure, biasing, current-voltage characteristics and small signal model are discussed in this section.
2.1.1 Structure of the PN junction
The structure of a PN junction consists of a region doped with acceptor impurities (p-type region) and a region doped with donor impurities (n-type region). The majority charge carriers for the p-type and n-type region are holes and electrons respectively. These two regions are combined in a junction. At this junction, a large concentration gradient for electrons and holes will exist.
Therefore, the majority electrons/holes will diffuse into the p-type/n-type region respectively.
The majority electrons leave positively charged donor atoms behind and the majority holes leave negatively charged acceptor atoms behind. This region of positive and negative charges is called the depletion region (WD). The depletion region WD ranges from −WDp to WDn (Figure 2.1a and equation (1)). Along the depletion region a potential drop establishes, the built-in potential ψbi [V], described with equation (2). With ND [cm−3] and NA [cm−3] as the donor and acceptor doping concentrations respectively, T as the temperature [K], k as the boltzmann constant [1.38
·10−23 J/K], q as the elementary charge [1.6 ·10−19C] and nias the intrinsic carrier concentration [cm−3] [15][9][8].
WD= s2
q
NA+ ND NDNA
ψbi (1)
ψbi= kT
q ln NDNA
n2i
(2) Within the depletion region an electric field establishes and no mobile charge charges are present here (Figure 2.1b). The distribution of the electric field and built-in voltage can be determined with the Poisson equation of equation (3), with s as the dielectric permittivity [F/cm] and ρ(x) as the charge density [cm−3]. This yields equation (4) and (5) for the electric field distribution.
The built-in potential distribution is then given by equation (6) and (7) [15][9].
−d2ψi dx2 = dE
dx = ρ(x)
s
(3)
E(−WDp< x < 0) = −−qNA(x + WDp)
s
(4)
E(0 < x < WDp) = −−qND(WDn− x)
s (5)
ψi(−WDp < x < 0) = qNA 2s
(x + WDp)2 (6)
ψi(0 < x < WDp) = ψi(0) +qND 2s
(WDn− x/2) x (7)
Note that the equations above assume a constant doping profile. A constant doping profile is not achieved in practice, the effects of this are discussed in section 2.3.
If no external potential is applied to the PN junction, the junction is in thermal equilibrium;
the Fermi-level is constant throughout the system. At thermal equilibirum, no net current flows through the system. The current consists of the drift current, induced by the built-in voltage and the diffusion current, induced by the carrier concentration gradient at both edges of the depletion
layer. These two currents work in opposite direction and cancel each other when no external volt- age is applied. When an external voltage is applied, current will flow. This is called biasing the PN junction [15][9].
Figure 2.1: The space charge distribution in the PN junction (a), The distribution of the electric field in the depletion region (b), The potential distribution with built-in voltage ψbi (c) and the energy band diagram (d) [9].
2.1.2 Biasing the PN junction
When an external voltage is applied to a PN junction, the Fermi level is not constant through the system. If the external voltage is applied in such a way that the anode is placed at a lower potential than the cathode (reverse bias) the potential barrier increases. Therefore, the depletion region width also increases and the majority electrons and holes cannot diffuse into the p-region and n-region respectively. Thus, ideally, no net current will flow at reverse bias. However, in re- verse bias, the electric field and separation of positive and negative charges induces a capacitance.
This capacitance per unit area is defined in equation (8), where dQD is the differential charge [C/cm2] on each side of the junction, dV is the differential applied voltage [V]. Note that here is assumed again that the doping profile is constant [9][15].
CD=dQD
dV = s
WD = rqsN
2
ψbi− V −2kT q
−1/2
(8) equation (8) is often rearranged to equation (9). This is done because by plotting 1/C2 versus V, the impurity concentration N can be determined with the slope and the built-in voltage can be
determined at 1/C2= 0.
1 c2D = 2
qsN
ψi− V −2kT q
(9) In contrast to reverse bias, also a forward bias can be applied. In this case, the anode is placed at a higher potential than the cathode. With forward bias, the potential barrier and depletion region width decreases. When the depletion region width decreases, electrons and holes can diffuse into the p-region and n-region respectively. Therefore, there will be a net current flowing through the PN junction at forward bias [15]. With this biasing the PN junction can function as a diode. The current-voltage characteristics of the PN diode are discussed in the next section.
2.1.3 Current-Voltage characteristics
The forward-bias current density is the sum of the recombination current density Jrand the ideal diffusion current density JD. The recombination current density originates from electrons and holes that can recombine within the depletion region. Due to recombination, injected charge carriers in the depletion region are lost and additional charge carriers need to be injected to make up for this loss. The recombination current is thus the current flow of these additional injected carriers.
The recombination rate is not constant through the depletion region; it is at its maximum at the junction (the center of the depletion region). The ideal current-voltage relation is described with the ideal diode equation of equation (10). Here, V is the bias voltage [V], I0 is the saturation current [A] and VT = kTq . The saturation current is also known as the leakage current, describing the small current flow that is still possible in reverse bias. The saturation current is described with equation (11), with q as the elementary charge (1.602176634 · 1019C), A as the cross-sectional area, ni as the intrinsic carrier density, Dpand Dnas the diffusion coefficient for the holes and electrons respectively [cm2/s], ND and NA as the donor and acceptor doping concentrations respectively [cm−3] and at last τp and τn as the carrier lifetime of the holes and electrons [s] [9]. Also, the ideality factor n equals 1 if diffusion dominates and 2 if recombination dominates. Equation (10) is valid when the the series resistance of the diode is negligible, this is only true at low voltages.
At higher voltages where IRs is comparable to the bias voltage, equation (12) holds. Note that equation (12) is an implicit function.
I = I0
exp qV nVT
− 1
(10)
I0= qAn2i 1 ND
sDp
τp + 1 NA
r Dn
τn
!
(11)
I = I0
exp V − IRs
nVT
− 1
(12) Additionally, in reverse bias one also needs to account for non ideal characteristics. One of these non ideal characteristics is the breakdown voltage. In the breakdown region, the diode conducts a large current in reverse bias and the blocking ability of the diode is lost. This breakdown is caused by two main processes. The first is the avalanche process. The avalanche process occurs when the electric field is larger than the critical electric field. The critical electric field is directly related to the material’s bandgap. When the electric field is thus large enough to overcome the bandgap, charge carriers acquire enough kinetic energy from the large electric field to create electron-hole pairs upon colliding with bound atomic electrons. The generated electrons and holes move in the opposite direction and therefore contribute to the reverse bias current. The second process is the Zener effect. The Zener effect occurs within highly doped junctions. At this highly doped junction, the p-region and n-region are sufficiently close to cause tunneling through the thin potential barrier.
This tunneling also contributes to the reverse bias current [15].
The current-voltage (I-V) characteristics are shown in Figure 2.2. Additionally, Figure 2.2 also shows a second breakdown conduction. The second breakdown is a thermoelectric effect which happens at high current densities and generally causes damage to the device [16][17].
The Energy band diagram in forward and reverse bias is shown in Figure 2.3, it can be seen that in forward bias the depletion region is much smaller than in reverse bias. In addition, the quasi
Fermi-levels in the depletion region are assumed be constant because the current also remains constant in the depletion region. This follows from equation (13) and (14) [9].
J~p= µpp 5 EF,p (13)
J~n= µnn 5 EF n (14)
Figure 2.2: The I-V characteristics of the PN diode including the saturation current, avalanche conduction and second breakdown [17].
Figure 2.3: The energy banddiagram in forward bias (left) and reverse bias (right) [9].
2.1.4 Small signal model
In the previous sections, only the DC characteristics of the PN diode are discussed. However, in most circuit applications, such as the switch circuit, RF signals are imposed on the DC voltage and current. Therefore, it is important to highlight the small-signal characteristics of the PN diode.
Assume the diode is forward biased with a DC voltage and produces a DC current. If a small amplitude RF signal (compared to the DC voltage) is applied, a small RF current is superimposed on the DC current. With this RF voltage and current, the small signal conductance can be defined with equation (15). If the RF voltage and current are very small, the conductance is simply the slope of the DC I-V curve (Figure 2.2) at a certain operating point [15]. In the same manner, the small-signal resistance can be defined with equation (16).
gd= dID dVa
Va=V0
(15)
rd= dVa
dId
ID=IDC
(16)
Also, with imposing RF signals a capacitance becomes important in the forward bias impedance;
the diffusion capacitance. This diffusion capacitance is due to the change in hole/electron concen- tration over time upon a RF voltage. If the RF voltage increases during its positive/negative half cycle, the concentration of holes at the junction increases/decreases. The holes at the junction diffuse into the n-region where they recombine with the majority electrons. Therefore, the hole concentration as function of the distance in the n-region also varies over time upon a RF voltage.
The same holds for the electrons that diffuse into the p-region. This charging and discharging of holes and electrons in the n-region an p-region respectively induces the diffusion capacitance [15].
Equation (17) describes the diffusion capacitance as a function of current I [A], lifetime τ [s]. Note that the diffusion capacitance is only presence at low frequencies. At low frequencies the lifetime of the carriers is smaller than the period of the RF signal and the carriers can thus follow the signal.
When the lifetime is much greater than the period of the RF signal, the diffusion capacitance is not observed [18].
Cdif f = qIτ
2kT (17)
2.2 PiN diode
2.2.1 Characteristics
The PiN diode is very similar to the PN diode, it consists of a p+-type layer, a n+-type layer but has an intrinsic region in between. Therefore, the analysis of the PiN diode should include the built-in voltage across the intrinsic region and the two junctions. The intrinsic region is not perfectly intrinsic in practice, but rather lightly n-doped compared to the highly doped p- and n-region. Figure 2.4 shows the cross-section of the PiN diode and the corresponding typical doping profile [19][8]. Figure 2.5 shows the energy band diagram for the PiN diode with the intrinsic region from x = 0 to x = W [20]. The intrinsic region has advantages in forward and reverse bias.
Figure 2.4: Left: Cross-section of a typical PiN diode structure [19] Right: The typical doping profile along the cross-section [8]
Figure 2.5: The energy band diagram of the PiN diode [20]
In forward bias, the current conductance is due to three transport mechanism. Firstly, at very low current levels. The current is dominated by the recombination process at the two junctions.
Secondly, at medium current levels the current is governed by the diffusion process of the carriers into the i-region. Thirdly, at high current levels the concentration of injected carriers becomes higher than the background doping of the i-region. This high concentration contributes to the conductivity modulation of the i-region. The conductivity modulation enables a low on-state voltage drop in the PiN diode [7]. These three transport mechanism are shown in Figure 2.6 where the I-V curve of a PiN diode is shown.
Figure 2.6: Forward bias I-V curve for a silicon PiN diode [7]
In reverse bias, the intrinsic region is depleted of charge carriers and provides a high resistivity.
Also, the intrinsic region provides a high breakdown voltage [14][19]. This high breakdown voltage is dependent on the doping concentration N of the intrinsic region and the most dominating factor of the PiN diode; the width W of the intrinsic region. These two parameters influence the shape of the established electric field, shown in Figure 2.7. Figure 2.7a shows the expected triangular shape for the electric field, however; if N decreases the electric field penetrates the n+-layer and the shape of the electrical field becomes trapezoidal and eventually rectangular (Figure 2.7b,c).
When this phenomenon occurs, the diode structure is a Punch-Through (PT) type. The potential
distribution is the integral over the electric field distribution, as was described with the Poisson equation. This yields that, for a perfect rectangular electric field, the breakdown voltage is the product of critical electric field Ec and width W . The flattening of the electric field indicates that a higher breakdown voltage is achieved; at the same potential the maximum electric field strength for a rectangular field is lower with respect to the triangular field [8]. Also, the constant electric field and potential indicates that the capacitance saturates at a lower reverse bias voltage. This saturation is due to the limit of the expansion of the depletion region due to the punch through mechanism.
Figure 2.7: The electric field distributions in a PiN diode in reverse bias [8]
2.2.2 Process flow of the PiN diode
In reality, the cross-section of the PiN diode is more complicated than that of Figure 2.4. This section will explain the most important steps of the process flow of the PiN diode, designed by NXP Semiconductors.
The process starts with a substrate that consists of high resistive boron-doped silicon (≈ 1014cm−3).
The first step is to create a low resistive sub-collector and cathode connection, called buried-N.
This buried-N is arsenic-doped silicon (≈ 1019cm−3). The second step is to deposit a lower doped (n-type) epitaxial layer on top of the buried-N (≈ 1015cm−3). This epitaxial layer will become the
”intrinsic”-region of the PiN diode, which is thus not intrinsic but low n-doped. These two steps are shown in Figure 2.8a
After these two steps, the Shallow Trench Isolations (STI’s) are defined. This is done with shielding the regions that do not function as STI with a photoresist mask. A shallow trench is etched into the silicon and filled with SiO2. These shallow trench function as an isolation between the anode and the cathode in the PiN diode. The formation of the STI’s is shown in Figure 2.8b
After the formation of the STI, Deep Trench Isolations are defined by etching deep trenches of 6 µm into the silicon. After the etching, the bottom of the deep trench is implanted with Boron to prevent the activation of possible parasitic leakage paths. Then, SiO2 is grown on the side wall of the deep trench. At last, Poly-Si is used to fill the deep trench. Poly-Si is used because it has an expansion coefficient closer to silicon than the Oxide has. Therefore, filling with poly-Si helps reducing the mechanical stress in the silicon structure. The formation of the DTI is shown in Figure 2.8c.
Figure 2.8: The process flow of the first three steps for the PiN diode, simulated with TCAD Sentaurus 2D process simulation (Chapter 3). Here the colormap indicates the NetActive doping concentration (blue indicates p-doped and red indicates n-doped). a) the silicon substrate with a high n-doped buried-N layer and on top the low n-doped epitaxial layer. b) the formation of the Shallow Trench Isolation (STI). c) the formation of the Deep Trench Isolation (DTI).
Next is the definition of the connection to the buried-N layer. With this connection, a low- resistive path to the cathode of the PiN diode is created. Note that the cathode is located vertically down from the anode, however; the connections to the anode and cathode are in the plane of the wafer. This low resistive path is created by implanting Phosphorus onto the silicon with the use of a photoresist mask. Phosphorus is used because it diffuses faster than Arsenic and allows deeper profiles. This step is shown in Figure 2.9a.
The same procedure is used to implant the epitaxial layer partially with Boron. With this implan- tation, the p+-layer of the PiN diode is established and the so-called PPLUS PiN diode is created.
Additionally, the p+-layer can also be established by placing a layer of Poly-Si above the epitaxial layer and implant with Boron. With this, the so-called PSB PiN diode is created. The PPLUS and PSB variant are shown in Figure 2.9a and 2.9b respectively. The implantation process and the effect of using poly-Si or mono-Si will be further explained in section 2.3.
Figure 2.9: The process flow of the last steps for the PiN diode, simulated with TCAD Sentaurus 2D process simulation (Chapter 3). Here the colormap indicates the NetActive doping concentration (blue indicates p-doped and red indicates n-doped). a) The definition of the low-resistive path to the buried-N layer; making connection with the cathode of the PiN. b) The PPLUS PiN diode, the epitaxial layer is implanted with Boron to create the P+-layer. c) The PSB PiN diode, a poly-Si layer is placed on top of the epitaxial layer and implanted with Boron to create the P+-layer.
The last step is to connect the PiN diode to the outside world. This is done by creating a silicide layer (CoSi2) on the active areas that require low resistance. After this, via various metal layers, one can connect with the PiN diode via te meta contacts at the top layer of the wafer.
2.3 Doping profiles
In section 2.2.2 the implantation steps were mentioned in the process flow. After implantation, the charge carriers diffuse through the silicon and a doping profile is established. This section explains the diffusion after implantation and the effect of mono-Si or poly-Si on the doping profile. At last, the consequence of the doping profile on the junction capacitance is explained.
2.3.1 Diffusion after implantation
As stated before, dopants need to be introduced in silicon when creating the PiN diode. In modern IC fabrication this is done by ion implantation; impurity ions are bombarded onto the silicon.
These high energetic ions lose their energy upon colliding with the nuclei and electrons of the target. The energetic ions will come to rest after a certain range, this range depends on the energy of the implanted ions and the crystal structure. This high energetic ion beam also causes damage to the silicon crystal by sputtering, creating a distribution of vacancies and interstitials.
Therefore, implantation requires a thermal annealing to treat the damage to the crystal and to place the atoms at a lattice position [21]. With thermal annealing, impurities can diffuse through the silicon. This diffusion can occur via vacancy, interstitial or interstitialcy diffusion. Vacancy diffusion describes the impurity atoms exchanging lattice positions with a available vacancy. When an interstitial atom diffuses to a vacant interstitial position, the diffusion is called interstitial diffusion. Combining these two diffusion types results in interstitialcy diffusion; the self-interstitial atoms of silicon displaces substitutional impurity atoms to an interstitial position. Self-interstitials exist in high concentration with the implantation process, making interstitialcy diffusion dominant.
This diffusion type is also called Transient Enhanced Diffusion (TED) [22][23].
2.3.2 Diffusion in single-crystalline silicon and poly-crystalline silicon
The doping profile before and after annealing is dependent on the crystal structures of silicon. In this section, single-crystalline silicon (mono-Si) and poly-crystalline silicon (poly-Si) are explained.
Single-crystalline silicon consists of one continuous silicon crystal without grain boundaries. There- fore, the impurities can diffuse through the crystal by interacting with vacancies and interstitials.
[21][24].
Poly-crystalline is composed of different Si crystals, introducing grain boundaries. At the grain boundaries, disorder is present and the dopant atoms can move along the provided diffusive paths.
This diffusion along the grain boundaries increases the overall doping diffusion in poly-Si markedly compared to mono-Si. However, at the grain boundaries the dopant atoms are not electrically active, but after diffusion along the boundary the dopant atoms can move back into the crystal and contribute to the electrical properties. Figure 2.10 shows the doping profile after annealing for mono-Si and poly-Si and it is shown that after annealing the dopant atoms and carriers diffuse further in the poly-Si. For diffusion in poly-Si two different cases can be considered; diffusion within the poly-Si upon annealing or diffusion from poly-si into mono-Si [24][25].
Diffusion within poly-Si strongly depends on the poly-crystalline structure; random and columnar structure. For a random structure (Figure 2.11a), there is no vertical alignment and dopant atoms diffuse along a vertical boundary until they encounter an underlying boundary. When they en- counter the underlying boundary they will more likely diffuse along the horizontal boundary until they encounter another vertical boundary.
For a columnar structure (Figure 2.11b) the crystal consists of continuous vertical grain bound- aries. With this structure the diffusion will be an-isotropic and the effective diffusion perpendicular to the plane is enhanced with respect to the random structure [24].
Figure 2.10: The doping profile for mono-Si (named Single-Si in this figure) and poly-Si after annealing [25]
Figure 2.11: A random poly-crystalline structure (a) and a columnar poly-crystalline structure (b) [24]
Diffusion from poly-Si to mono-Si is important for the PiN diode when the p+-layer is made of poly-Si and the intrinsic region of mono-Si. When poly-Si is deposited on mono-Si the dopant atoms tend to accumulate at the interface due to the thin oxide that is often present between the poly-Si and mono-Si. Figure 2.12 shows the concentration profile along the poly-Si and mono-Si layers, note that the poly-Si concentration profile is almost uniform due to the high diffusion rate compared to mono-Si. The accumulation at the interface can be reduced if the interface is cleaned (upon for example HF etching), the poly-si layer can align epitaxially with the mono-Si layer.
However, when the oxide is removed, the dopant concentration entering mono-Si layer decreases because the dopants in the poly-si diffuse over a longer distance. Additionally, the oxide should not be too thick because it will block the diffusion [24][26].
Figure 2.12: The concentration profile for boron diffusing through a poly-Si and mono-Si layer [26]
This section about the difference between poly-Si and mono-Si demonstrates the advantages of using poly-Si as the p+-layer in the PiN diode; a more constant doping profile could have a positive influence on the on-resistance.
2.3.3 Junction capacitance for realistic doping profiles
In section 2.1 it was assumed that the doping near the junction is constant. However, the previous sections showed that in practice the doping profile is not constant. The doping profile will influence the built-in potential and electrical field distribution and thus also the capacitance. For arbitrary doping profiles, it is not possible to solve the Poisson equation analytically. The potential change at the junction (considering the n-side) is determined with integrating the total electrical field (following from the Poisson equation) across the depletion region [9]:
ψn = ψn0− V = − Z WD
0
E(x) dx =
Z E(WD) E(0)
xdE
dx dx = q
s
Z WD
0
xND(x) dx (18)
From this follows:
dV
dWD = − dψn
dWD = −qND(WD)WD
s (19)
Also , the general expression CD= s/WD still holds. With this equation (20) can be derived for an arbitrary doping profile.
d(1/CD2)
dV = d(1/CD2) dWD
dWD
dV =2WD
2s dWD
dV = − 2
qsND(WD) (20)
3 Experimental methodology
Knowledge about devices is acquired through studying the device’s characteristics upon various device or process parameters. At NXP, wafers are available where the properties of the device or process are varied with a certain split.
In this chapter, at first the measurement equipment and set-up is shown. Followed by discussing the measurement and analysis routine for the DC and RF measurement respectively. At last, the available test structures at NXP are discussed.
3.1 Measurement equipment and set-up
In order to characterize the PiN diode, various equipment and software is required and these are described in this section. First, the DC probe station and RF probe station are discussed that acquire signals from the small PiN diodes on the silicon wafer trough precisely placed contacts.
Secondly, the device and network analyzer to provide the current/voltage input and RF signals to the probes are described. At last, the software ICCAP discussed.
3.1.1 DC probe station
A probe station is used to acquire DC signals from the PiN diode on a silicon wafer. The probe station used in this research is the CM300 from CascadeMicrotech (Figure 3.1). This probe station acquires electrical signals from the wafer by needles (probes) that can make contact with the device under test (DUT). The microchamber with the wafer is connected to a thermal control system, keeping the temperature at an ambient temperature of 21◦C (294 K). When performing measurements with this probe station, the following procedure is taken. At first, the wafer is clamped on the wafer chuck by activating a vacuum beneath. Secondly, the wafer is loaded into the probe station and its position is set with the use of internal camera’s in such a way that it does not make contact yet with the probe needles. Thirdly, the location of the devices of interest on the wafer is determined with the internal microscope. At last, when the device is located, the probes are manually moved to make contact with the device and the measurement is driven by an external device analyzer and software. The measurement is performed after switching off the lights, to prevent optical recombination during the measurement. More information on the CM300 probe station can be accessed via reference [27].
Figure 3.1: The CM300 CascadeMicrotech probe station
3.1.2 RF probe station
For the RF measurements, a RF probe station is used that can perform measurements typically above 100 MHz. The probe station that is used is the semi-automatic 8-inch 12K Cascade prober (Summit 12000-AP) (Figure 3.2). This RF probe station is equipped with a device analyzer to apply the DC-voltages and measure the DC-currents. Additionally, a network analyzer is used to apply the small RF signals and measure the corresponding S-parameters. The S-parameters will be addressed in section 3.3. The DC and RF-signals are combined with bias tees and subsequently applied to the DUT. Figure 3.3 shows schematically the RF set up with the probe station, device analyzer and network analyzer. For the RF probe station, the procedure before measuring is very similar to the DC probe station. However, there are two main differences.
Firstly, in the RF probe stations a high frequency probe is used to measure above 100 MHz; the Infinity Probe of CascadeMicrotech [28]. This probe consists of the coaxial connector, the probe body and the probe tip with three contacts (Figure 3.4). With an ordinary probe contact, the contact is a signal (S) or ground (G) and thus only one contact is required per probe. However, when dealing with high frequencies, the ground is not an equipotential reference [28]. The ground is now a part of a transmission line that contains time varying electric fields. Therefore, the Ground- Signal-Ground (GSG) configuration is used and thus three contacts are required per probe [28].
The GSG configuration for both anode and cathode side consists of the anode and cathode contact surrounded by four patches for grounding purposes (Figure 3.5).
Secondly, when doing RF measurements it is important to calibrate the set-up and perform de-embedding at the RF probe tips. De-embedding is done to remove all parasitic resistances, capacitance’s and inductance’s of, for example, the leads and the wafer substrate. The calibration is done by a specialist at NXP before the start of every measurement day, because it is a complex and sensitive process. The de-embedding procedure is done after the measurements and is further explained in section 3.3.
Figure 3.2: The Summit 12000-AP CascadeMicrotech RF probe station
Figure 3.3: Setup used for I-V and small-signal measurements. The device analyzer used is a B1500A from Keysight. The network analyzer used is also from Keysight. The DC-signals from the device analyzer and RF-signals from the network analyzer are combined using bias tees.
Figure 3.4: The infinity probe with three contacts at the probe tip [28].
Figure 3.5: The Ground-Signal-Ground (GSG) configuration on the wafer. The configuration consists of an anode and cathode patch and four extra patches for grounding purposes.
3.1.3 Device analyzer, network analyzer and software
Both the DC and RF probe station are equipped with a device analyzer, B1500A from Keysight technologies. The device analyzer makes it possible to perform current-voltage by connecting with the probe station, by using Source-Measure-Units (SMU’s). This SMU allows sourcing and measuring at the same probe. The device analyzer provides the input for the probe station, this input can be set by external computer software.
The RF probe station is also equipped with a Network analyzer, the Agilent PNA, N5227A from Keysight. This network analyzer can supply small RF signals to the DUT with a frequency range of 100 MHz to 48 GHz [29]. The input for network analyzer is also set by external computer software.
The software used in this research is IC-CAP (Integrated Circuit Characterization and Analysis Program) by Keysight technologies. The IC-CAP software can also be used for extracting and analyzing the output of the measurements, although in most cases the output will be further analyzed with Matlab. More information on the B1500A device analyzer, the network analyzer and IC-CAP software can be accessed via references [30], [29] and [31] respectively.
3.2 DC measurement
The goal of this measurement is to study the I-V characteristics of different PiN diodes upon DC biasing. For this, the CM300 probe station is used. The biasing is voltage controlled and applied in two ways; anode biasing and cathode biasing. With anode biasing, the cathode is put at 0 V and the anode is put at a positive or negative voltage for forward or reverse bias respectively. With cathode biasing, the anode is put at 0 V and the cathode is put at a negative or positive voltage for forward or reverse bias respectively. These methods of biasing will influence the current that leaks through the substrate. Therefore, the anode-, cathode- and substrate current are measured for the two biasing methods. Table 1 shows the input for both biasing methods used in these measurements.
This input is provided to the probe station through IC-CAP and the device analyzer.
Table 1: The input for the DC measurement
Measurement Anode voltage sweep [V] Cathode voltage sweep [V] Step size [mV]
Anode biasing -6 ... 1.75 0 40
Cathode biasing 0 -1.75 ... 6 40
With the obtained I-V output, the series resistance, saturation current and ideality factor can be determined by fitting equation (12) through the data. However, this equation is implicit but can be made explicit with the Lambert w function. With the Lambert w function the current is expressed through equation (21) with VT = kTq [32][33]. By fitting equation (21) through the forward bias data Rs is determined. Note that I0 and n are first determined by fitting equation (10) through the voltage range that describes the ideal exponential diode characteristics. The determined Rsis corrected for the resistance of the leads by measuring a SHORT structure. This resistance is measured to be 1.42 ±0.08Ω.
I = −I0+nVT
Rs
lambertw I0Rs
nVT
exp V + I0Rs
nVT
(21)
3.3 RF measurement
The goal of this measurement is to determine Cof f and Ron as a function of frequency and bias.
With the obtained Cof fand Ronthe FOM can be determined and the most optimal diode structure can be determined. For this measurement, the RF probe station is used and the anode biasing is voltage controlled. The measurements are executed in two ways; keeping the frequency constant and sweeping the bias voltage from -2.5V to 1.75V or keeping the voltage constant and sweeping the frequency from 100 MHz to 48 GHz. However, before one can determine Cof f and Ron four important steps should be taken to interpret the measured output.
Firstly, one has to understand that the RF measurement system is measuring Scattering (S) parameters. The S-parameters describe the ratio between the reflected and incident waves at the
ports of the network. This scattering is related to the impedance of the power source (ZS) and the impedance of the load (ZL). The input ZS is connected to the output ZL via a transmission line with impedance Z0. If ZL= Z0 the waves are totally transferred from the source to the load, however if ZL6= Z0some power is reflected from the load to the source. Due to this reflection, the power from the source PA will be reflected and only a fraction |Γ|2 of PAwill be dissipated by the load. This reflection is described with the reflection coefficient Γ = ZZL−Z0
L+Z0. Thus, the reflection co- efficient depends on the impedance of the PiN diode in this case and thus on the equivalent circuit [34]. Figure 3.6 shows a two port network with incident waves a1 and a2 and reflected waves b1 and b2. Additionally, equation (22) shows the S-parameter matrix that describes the S-parameters of the incident waves. Note that in the PiN diode measurements, port 1 is the cathode and port 2 is the anode. The S11 and S22 parameters represent the reflection at the input and output.
The S12and S21 parameters represent the reverse and forward reflection coefficient. With the S21
parameter, one can thus determine the Insertion Loss (IL) or Isolation (ISO) in forward or reverse bias respectively with equation (24) in dB [10].
Figure 3.6: A two port network with incident waves a1 and a2 and reflected waves b1 and b2 [34]
b1 b2
=S11 S12
S21 S22
a1 a2
(22)
I1
I2
=Y11 Y12
Y21 Y22
V1
V2
(23) IL = ISO = 20 · log(|Γ|2) = 20 · log(S21) (24)
Secondly, these S-parameters have to be converted to Y-parameters. Y-parameters describe the admittance of a network, for a two port network equation (23) describes how the Y matrix relates to the current and voltage at the two ports [34]. The mathematical conversion from S-parameters to Y-parameters is already included within the software of ICCAP and can be consulted in literature [35].
Thirdly, the obtained Y-parameters have to be de-embedded at the probe-tips after the cali- bration of the measurement set-up. With this de-embedding, the measurements are corrected for external capacitance’s, series resistances of the cables and bias tees, external inductions and internal capacitance’s. This is done by using the generic open - generic short - dedicated open (OSO) de- embedding procedure [36][37]. The corresponding de-embedding equations are given by equation (25),(26) and (27). The background of the de-embedding equation is that the raw Y parameters (YDU T ,RAW) are first corrected with the generic open structure (YDU T ,RAW− YGO). Subsequently, the raw Y parameters are corrected with the Z-parameter of the generic short structure, which is also corrected with the generic open structure
ZGS−1− YGO−1
. These two steps are described with equation (25). In the final step, the partially de-embedded Y parameters (YDU T 1) are cor- rected with the dedicated open structure with equation (27), which is also corrected with the generic open and generic short structure with equation (26). After the OSO de-embedding the reference plane is at the contacts to the silicon.
YDU T 1=h
(YDU T ,RAW − YGO)−1− ZGS−1− YGO
−1i−1
(25) YDO =h
(YDO,RAW − YGO)−1− ZGS−1 − YGO−1i−1
(26)
YDU T = YDU T 1− YDO (27)
At last, the equivalent circuit of the PiN diode has to be understood. With this, one can interpret the real and imaginary part of the Y parameters. Figure 3.7 shows the equivalent circuit of the PiN diode, consisting of the depletion capacitance (Cdepletion), injection resistance (R), a series resistance (Rs) and induction (L) [38]. This induction is due to the metal contacts where the probe tips make contact with the wafer and cannot be de-embedded because a dedicated-short structure is not available. However, the equivalent circuit of Figure 3.7 does not represent the complete structure. There is not only an anode and cathode connection but also a grounded substrate connection. The connection to the substrate of the PiN diode represents a parasitic PN structure (Figure 3.8) and also influences the four Y parameters (ideally these should be the same).
However, in this research the focus is on the PiN structure between anode and cathode and thus the Y21parameter is used for the analysis.
To visualize the frequency dependent behavior of the diode the Real and imaginary part of the admittance is plotted with frequencies from 1 MHz to 1 THz, based on the combination of elements of Figure 3.7. Figure 3.9 shows the real and imaginary part versus frequency in forward bias, with Cdepletion= 6.77pF , R = 13Ω, Rs= 4Ω and L = 90pH. Figure 3.10 shows the real and imaginary part versus frequency in reverse bias from 1 MHz to 1 THz, with Cdepletion= 198f F , R = 1.5∗1014, Rs= 4Ω and L = 90pH. Note that, in reverse bias R is very high due to the low injection and thus not visible in this frequency range.
Now, Ronis determined with 1/Real(Y21) and consists of all four elements and thus is frequency and bias dependent. Ronis typically determined around 1−3mA because this will also be approximately the operating point in applications. To determine the 3 mA point for every diode, one has to interpolate around 3 mA because the biasing is voltage controlled and therefore not every diode has a measurement point at exactly 3 mA. Ron is determined at low frequencies (2-10 GHz) were the induction effect is not dominant. However, note that the application frequency is 20 GHz.
Then, Cof f is determined with Imag(Y21)/ω at low frequencies where the inductance L is not dominant and in reverse bias at −2.5V .
Figure 3.7: The equivalent circuit of the PiN diode, consisting of the depletion capacitance (Cdepletion), injection resistance (R), a series resistance (Rs) and the induction (L) due to the metal contacts [38]
Figure 3.8: The general structure of the PiN diode that shows the layers that make the PiN diode and the substrate p-layer that creates a PN diode with the n-layer.
Figure 3.9: The real part of the admittance (left) and the imaginary part of the admittance (right) with Cdepletion = 6.77pF , R = 13Ω, Rs = 4.17Ω and L = 90pH; this combination of values represents the forward bias.
Figure 3.10: The real part of the admittance (left) and the imaginary part of the admittance (right) with Cdepletion= 198f F , R = 1.5 ∗ 1014, Rs= 4.17Ω and L = 90pH; this combination of values represents the reverse bias.
3.4 Test structures
The previously discussed DC and RF measurement procedures are done for four categories of diodes that are available at NXP. These four categories are explained in this section.
Firstly, the diodes are varied in anode area. Increasing the anode area aims at decreasing Ron, but increasing Cof f. Table 2 shows an overview of the diodes that are varied in Anode width (WA) and Anode Length (LA). Additionally, the Cathode Width (CW), the STI width (SW) and number of DTI’s (DR) are listed.
Secondly, the number of parallel structures is varied. Using parallel PiN diodes aims at decreas- ing Ron with the factor of parallel diodes, whereas Cof f will increase with the factor of parallel diodes. NXP has proposed the so-called Multi-Finger diode to achieve a parallel structure. Figure 3.11 and 3.12 shows the difference between a single square diode and a multi-finger diode in the top view and cross section respectively. A multi-finger diode consist of multiple parallel cells and parallel fingers inside the cell, the effect of parallel fingers and parallel cells is evaluated separately.
Table 3 shows an overview of the diodes that are varied in the number of parallel fingers or cells.
Thirdly, the thickness of the epitaxial (EPI thickness) layer is varied. Increasing the EPI thickness aims at decreasing Cof f but increases Ron. The EPI thickness is by default 0.63 µm, but is varied to 0.73, 0.78, and 0.83 µm in these measurements. All diodes from Table 2 and 3 are increased in EPI thickness, however; one diode will be chosen for further evaluation. In the results will be explained which is chosen and why.
Fourthly, the difference between the PPLUS and PSB diode is of interest. The difference be- tween a PPLUS and PSB diode was explained in section 2.2.2; the PSB diode consists of a poly-Si anode and an effective thicker EPI. Table 4 shows an overview of the PPLUS and PSB diodes that are available. The PSB diodes are only available in the so-called PCM configuration, whereas the GSG configuration is required to perform RF measurements. Therefore, the PSB diodes can only be compared to the PPLUS diodes for DC measurements. Figure 3.13 shows again the GSG configuration but now compared to the PCM configuration.
In addition, also temperature measurements are done in DC to check the temperature depen- dent behavior of the diode compared to theory. This is done for a temperature range of -30◦C to 105◦C
Figure 3.11: A schematic top view of the square diode (left) and the Multi-finger diode (right), with the anode area in green, the cathode area in red and the STI area in grey
Figure 3.12: A schematic cross section of the square diode (left) and the Multi-finger diode (right), with the anode area in green, the cathode area in red.
Figure 3.13: The PCM (left) and GSG (right) structure. The GSG configuration consists of an anode and cathode patch and four extra patches for grounding purposes. The PCM configuration only consists of an anode and cathode patch.
Table 2: The parameters of the diodes that are used for analyzing the area scaling of the PiN diode.
With Anode Width (WA), Anode Length (LA), Cathode Width (CW), STI width (SW) and number of DTI’s (DR)
Layout WA [µm] LA [µm] CW [µm] SW [µm] DR
Square 10 10 1.5 0.8 3
Square 8 8 1.5 0.8 3
Square 7 7 1.5 0.8 3
Square 6 6 1.5 0.8 3
Square 5 5 1.5 0.8 3
Square 4 4 1.5 0.8 3
Square 2 2 1.5 0.8 3
Table 3: The parameters of the diodes that are used for analyzing the parallel structure of the PiN diode. With Anode Width (WA), Anode Length (LA), the Number of Fingers (NF), the Number of Cells (NC), Cathode Width (CW), STI width (SW) and number of DTI’s (DR)
Layout WA [µm] LA [µm] NF NC CW [µm] SW [µm] DR
Multi-Finger 0.5 5 5 1 1.5 0.8 3
Multi-Finger 0.5 5 4 1 1.5 0.8 3
Multi-Finger 0.5 5 3 1 1.5 0.8 3
Multi-Finger 0.5 5 2 1 1.5 0.8 3
Multi-Finger 0.5 5 1 1 1.5 0.8 3
Multi-Finger 0.5 10 1 10 1.5 0.8 3
Multi-Finger 0.5 10 1 8 1.5 0.8 3
Multi-Finger 0.5 10 1 6 1.5 0.8 3
Multi-Finger 0.5 10 1 4 1.5 0.8 3
Multi-Finger 0.5 10 1 2 1.5 0.8 3
Table 4: The parameters of the diodes that are used for comparing PPLUS and PSB diodes. With Anode Width (WA), Anode Length (LA), Cathode Width (CW), STI width (SW), number of DTI’s (DR), the number of fingers (NC) and number of cells (NC) if applicable.
Layout PPLUS or PSB WA [µm] LA [µm] NF NC CW [µm] SW [µm] DR
Square PPLUS 10 10 - - 1.5 0.8 1
Square PPLUS 6 6 - - 1.5 0.8 1
Square PPLUS 2 2 - - 1.5 0.8 1
Multi-Finger PPLUS 0.5 10 2 3 1.5 0.8 1
Multi-Finger PPLUS 0.5 6 2 3 1.5 0.8 1
Multi-Finger PPLUS 0.5 2 2 3 1.5 0.8 1
Square PSB 10 10 - - 1.5 0.8 1
Square PSB 6 6 - - 1.5 0.8 1
Square PSB 2 2 - - 1.5 0.8 1
Multi-Finger PSB 0.5 10 2 3 1.5 0.8 1
Multi-Finger PSB 0.5 6 2 3 1.5 0.8 1
Multi-Finger PSB 0.5 2 2 3 1.5 0.8 1
