2.2.1 Characteristics
The PiN diode is very similar to the PN diode, it consists of a p+-type layer, a n+-type layer but has an intrinsic region in between. Therefore, the analysis of the PiN diode should include the built-in voltage across the intrinsic region and the two junctions. The intrinsic region is not perfectly intrinsic in practice, but rather lightly n-doped compared to the highly doped p- and n-region. Figure 2.4 shows the cross-section of the PiN diode and the corresponding typical doping profile [19][8]. Figure 2.5 shows the energy band diagram for the PiN diode with the intrinsic region from x = 0 to x = W [20]. The intrinsic region has advantages in forward and reverse bias.
Figure 2.4: Left: Cross-section of a typical PiN diode structure [19] Right: The typical doping profile along the cross-section [8]
Figure 2.5: The energy band diagram of the PiN diode [20]
In forward bias, the current conductance is due to three transport mechanism. Firstly, at very low current levels. The current is dominated by the recombination process at the two junctions.
Secondly, at medium current levels the current is governed by the diffusion process of the carriers into the i-region. Thirdly, at high current levels the concentration of injected carriers becomes higher than the background doping of the i-region. This high concentration contributes to the conductivity modulation of the i-region. The conductivity modulation enables a low on-state voltage drop in the PiN diode [7]. These three transport mechanism are shown in Figure 2.6 where the I-V curve of a PiN diode is shown.
Figure 2.6: Forward bias I-V curve for a silicon PiN diode [7]
In reverse bias, the intrinsic region is depleted of charge carriers and provides a high resistivity.
Also, the intrinsic region provides a high breakdown voltage [14][19]. This high breakdown voltage is dependent on the doping concentration N of the intrinsic region and the most dominating factor of the PiN diode; the width W of the intrinsic region. These two parameters influence the shape of the established electric field, shown in Figure 2.7. Figure 2.7a shows the expected triangular shape for the electric field, however; if N decreases the electric field penetrates the n+-layer and the shape of the electrical field becomes trapezoidal and eventually rectangular (Figure 2.7b,c).
When this phenomenon occurs, the diode structure is a Punch-Through (PT) type. The potential
distribution is the integral over the electric field distribution, as was described with the Poisson equation. This yields that, for a perfect rectangular electric field, the breakdown voltage is the product of critical electric field Ec and width W . The flattening of the electric field indicates that a higher breakdown voltage is achieved; at the same potential the maximum electric field strength for a rectangular field is lower with respect to the triangular field [8]. Also, the constant electric field and potential indicates that the capacitance saturates at a lower reverse bias voltage. This saturation is due to the limit of the expansion of the depletion region due to the punch through mechanism.
Figure 2.7: The electric field distributions in a PiN diode in reverse bias [8]
2.2.2 Process flow of the PiN diode
In reality, the cross-section of the PiN diode is more complicated than that of Figure 2.4. This section will explain the most important steps of the process flow of the PiN diode, designed by NXP Semiconductors.
The process starts with a substrate that consists of high resistive boron-doped silicon (≈ 1014cm−3).
The first step is to create a low resistive sub-collector and cathode connection, called buried-N.
This buried-N is arsenic-doped silicon (≈ 1019cm−3). The second step is to deposit a lower doped (n-type) epitaxial layer on top of the buried-N (≈ 1015cm−3). This epitaxial layer will become the
”intrinsic”-region of the PiN diode, which is thus not intrinsic but low n-doped. These two steps are shown in Figure 2.8a
After these two steps, the Shallow Trench Isolations (STI’s) are defined. This is done with shielding the regions that do not function as STI with a photoresist mask. A shallow trench is etched into the silicon and filled with SiO2. These shallow trench function as an isolation between the anode and the cathode in the PiN diode. The formation of the STI’s is shown in Figure 2.8b
After the formation of the STI, Deep Trench Isolations are defined by etching deep trenches of 6 µm into the silicon. After the etching, the bottom of the deep trench is implanted with Boron to prevent the activation of possible parasitic leakage paths. Then, SiO2 is grown on the side wall of the deep trench. At last, Poly-Si is used to fill the deep trench. Poly-Si is used because it has an expansion coefficient closer to silicon than the Oxide has. Therefore, filling with poly-Si helps reducing the mechanical stress in the silicon structure. The formation of the DTI is shown in Figure 2.8c.
Figure 2.8: The process flow of the first three steps for the PiN diode, simulated with TCAD Sentaurus 2D process simulation (Chapter 3). Here the colormap indicates the NetActive doping concentration (blue indicates p-doped and red indicates n-doped). a) the silicon substrate with a high n-doped buried-N layer and on top the low n-doped epitaxial layer. b) the formation of the Shallow Trench Isolation (STI). c) the formation of the Deep Trench Isolation (DTI).
Next is the definition of the connection to the buried-N layer. With this connection, a low-resistive path to the cathode of the PiN diode is created. Note that the cathode is located vertically down from the anode, however; the connections to the anode and cathode are in the plane of the wafer. This low resistive path is created by implanting Phosphorus onto the silicon with the use of a photoresist mask. Phosphorus is used because it diffuses faster than Arsenic and allows deeper profiles. This step is shown in Figure 2.9a.
The same procedure is used to implant the epitaxial layer partially with Boron. With this implan-tation, the p+-layer of the PiN diode is established and the so-called PPLUS PiN diode is created.
Additionally, the p+-layer can also be established by placing a layer of Poly-Si above the epitaxial layer and implant with Boron. With this, the so-called PSB PiN diode is created. The PPLUS and PSB variant are shown in Figure 2.9a and 2.9b respectively. The implantation process and the effect of using poly-Si or mono-Si will be further explained in section 2.3.
Figure 2.9: The process flow of the last steps for the PiN diode, simulated with TCAD Sentaurus 2D process simulation (Chapter 3). Here the colormap indicates the NetActive doping concentration (blue indicates p-doped and red indicates n-doped). a) The definition of the low-resistive path to the buried-N layer; making connection with the cathode of the PiN. b) The PPLUS PiN diode, the epitaxial layer is implanted with Boron to create the P+-layer. c) The PSB PiN diode, a poly-Si layer is placed on top of the epitaxial layer and implanted with Boron to create the P+-layer.
The last step is to connect the PiN diode to the outside world. This is done by creating a silicide layer (CoSi2) on the active areas that require low resistance. After this, via various metal layers, one can connect with the PiN diode via te meta contacts at the top layer of the wafer.