In section 2.2.2 the implantation steps were mentioned in the process flow. After implantation, the charge carriers diffuse through the silicon and a doping profile is established. This section explains the diffusion after implantation and the effect of mono-Si or poly-Si on the doping profile. At last, the consequence of the doping profile on the junction capacitance is explained.
2.3.1 Diffusion after implantation
As stated before, dopants need to be introduced in silicon when creating the PiN diode. In modern IC fabrication this is done by ion implantation; impurity ions are bombarded onto the silicon.
These high energetic ions lose their energy upon colliding with the nuclei and electrons of the target. The energetic ions will come to rest after a certain range, this range depends on the energy of the implanted ions and the crystal structure. This high energetic ion beam also causes damage to the silicon crystal by sputtering, creating a distribution of vacancies and interstitials.
Therefore, implantation requires a thermal annealing to treat the damage to the crystal and to place the atoms at a lattice position [21]. With thermal annealing, impurities can diffuse through the silicon. This diffusion can occur via vacancy, interstitial or interstitialcy diffusion. Vacancy diffusion describes the impurity atoms exchanging lattice positions with a available vacancy. When an interstitial atom diffuses to a vacant interstitial position, the diffusion is called interstitial diffusion. Combining these two diffusion types results in interstitialcy diffusion; the self-interstitial atoms of silicon displaces substitutional impurity atoms to an interstitial position. Self-interstitials exist in high concentration with the implantation process, making interstitialcy diffusion dominant.
This diffusion type is also called Transient Enhanced Diffusion (TED) [22][23].
2.3.2 Diffusion in single-crystalline silicon and poly-crystalline silicon
The doping profile before and after annealing is dependent on the crystal structures of silicon. In this section, single-crystalline silicon (mono-Si) and poly-crystalline silicon (poly-Si) are explained.
Single-crystalline silicon consists of one continuous silicon crystal without grain boundaries. There-fore, the impurities can diffuse through the crystal by interacting with vacancies and interstitials.
[21][24].
Poly-crystalline is composed of different Si crystals, introducing grain boundaries. At the grain boundaries, disorder is present and the dopant atoms can move along the provided diffusive paths.
This diffusion along the grain boundaries increases the overall doping diffusion in poly-Si markedly compared to mono-Si. However, at the grain boundaries the dopant atoms are not electrically active, but after diffusion along the boundary the dopant atoms can move back into the crystal and contribute to the electrical properties. Figure 2.10 shows the doping profile after annealing for mono-Si and poly-Si and it is shown that after annealing the dopant atoms and carriers diffuse further in the poly-Si. For diffusion in poly-Si two different cases can be considered; diffusion within the poly-Si upon annealing or diffusion from poly-si into mono-Si [24][25].
Diffusion within poly-Si strongly depends on the poly-crystalline structure; random and columnar structure. For a random structure (Figure 2.11a), there is no vertical alignment and dopant atoms diffuse along a vertical boundary until they encounter an underlying boundary. When they en-counter the underlying boundary they will more likely diffuse along the horizontal boundary until they encounter another vertical boundary.
For a columnar structure (Figure 2.11b) the crystal consists of continuous vertical grain bound-aries. With this structure the diffusion will be an-isotropic and the effective diffusion perpendicular to the plane is enhanced with respect to the random structure [24].
Figure 2.10: The doping profile for mono-Si (named Single-Si in this figure) and poly-Si after annealing [25]
Figure 2.11: A random poly-crystalline structure (a) and a columnar poly-crystalline structure (b) [24]
Diffusion from poly-Si to mono-Si is important for the PiN diode when the p+-layer is made of poly-Si and the intrinsic region of mono-Si. When poly-Si is deposited on mono-Si the dopant atoms tend to accumulate at the interface due to the thin oxide that is often present between the poly-Si and mono-Si. Figure 2.12 shows the concentration profile along the poly-Si and mono-Si layers, note that the poly-Si concentration profile is almost uniform due to the high diffusion rate compared to mono-Si. The accumulation at the interface can be reduced if the interface is cleaned (upon for example HF etching), the poly-si layer can align epitaxially with the mono-Si layer.
However, when the oxide is removed, the dopant concentration entering mono-Si layer decreases because the dopants in the poly-si diffuse over a longer distance. Additionally, the oxide should not be too thick because it will block the diffusion [24][26].
Figure 2.12: The concentration profile for boron diffusing through a poly-Si and mono-Si layer [26]
This section about the difference between poly-Si and mono-Si demonstrates the advantages of using poly-Si as the p+-layer in the PiN diode; a more constant doping profile could have a positive influence on the on-resistance.
2.3.3 Junction capacitance for realistic doping profiles
In section 2.1 it was assumed that the doping near the junction is constant. However, the previous sections showed that in practice the doping profile is not constant. The doping profile will influence the built-in potential and electrical field distribution and thus also the capacitance. For arbitrary doping profiles, it is not possible to solve the Poisson equation analytically. The potential change at the junction (considering the n-side) is determined with integrating the total electrical field (following from the Poisson equation) across the depletion region [9]:
ψn = ψn0− V = −
Also , the general expression CD= s/WD still holds. With this equation (20) can be derived for an arbitrary doping profile.
3 Experimental methodology
Knowledge about devices is acquired through studying the device’s characteristics upon various device or process parameters. At NXP, wafers are available where the properties of the device or process are varied with a certain split.
In this chapter, at first the measurement equipment and set-up is shown. Followed by discussing the measurement and analysis routine for the DC and RF measurement respectively. At last, the available test structures at NXP are discussed.
3.1 Measurement equipment and set-up
In order to characterize the PiN diode, various equipment and software is required and these are described in this section. First, the DC probe station and RF probe station are discussed that acquire signals from the small PiN diodes on the silicon wafer trough precisely placed contacts.
Secondly, the device and network analyzer to provide the current/voltage input and RF signals to the probes are described. At last, the software ICCAP discussed.
3.1.1 DC probe station
A probe station is used to acquire DC signals from the PiN diode on a silicon wafer. The probe station used in this research is the CM300 from CascadeMicrotech (Figure 3.1). This probe station acquires electrical signals from the wafer by needles (probes) that can make contact with the device under test (DUT). The microchamber with the wafer is connected to a thermal control system, keeping the temperature at an ambient temperature of 21◦C (294 K). When performing measurements with this probe station, the following procedure is taken. At first, the wafer is clamped on the wafer chuck by activating a vacuum beneath. Secondly, the wafer is loaded into the probe station and its position is set with the use of internal camera’s in such a way that it does not make contact yet with the probe needles. Thirdly, the location of the devices of interest on the wafer is determined with the internal microscope. At last, when the device is located, the probes are manually moved to make contact with the device and the measurement is driven by an external device analyzer and software. The measurement is performed after switching off the lights, to prevent optical recombination during the measurement. More information on the CM300 probe station can be accessed via reference [27].
Figure 3.1: The CM300 CascadeMicrotech probe station
3.1.2 RF probe station
For the RF measurements, a RF probe station is used that can perform measurements typically above 100 MHz. The probe station that is used is the semi-automatic 8-inch 12K Cascade prober (Summit 12000-AP) (Figure 3.2). This RF probe station is equipped with a device analyzer to apply the DC-voltages and measure the DC-currents. Additionally, a network analyzer is used to apply the small RF signals and measure the corresponding S-parameters. The S-parameters will be addressed in section 3.3. The DC and RF-signals are combined with bias tees and subsequently applied to the DUT. Figure 3.3 shows schematically the RF set up with the probe station, device analyzer and network analyzer. For the RF probe station, the procedure before measuring is very similar to the DC probe station. However, there are two main differences.
Firstly, in the RF probe stations a high frequency probe is used to measure above 100 MHz; the Infinity Probe of CascadeMicrotech [28]. This probe consists of the coaxial connector, the probe body and the probe tip with three contacts (Figure 3.4). With an ordinary probe contact, the contact is a signal (S) or ground (G) and thus only one contact is required per probe. However, when dealing with high frequencies, the ground is not an equipotential reference [28]. The ground is now a part of a transmission line that contains time varying electric fields. Therefore, the Ground-Signal-Ground (GSG) configuration is used and thus three contacts are required per probe [28].
The GSG configuration for both anode and cathode side consists of the anode and cathode contact surrounded by four patches for grounding purposes (Figure 3.5).
Secondly, when doing RF measurements it is important to calibrate the set-up and perform de-embedding at the RF probe tips. De-embedding is done to remove all parasitic resistances, capacitance’s and inductance’s of, for example, the leads and the wafer substrate. The calibration is done by a specialist at NXP before the start of every measurement day, because it is a complex and sensitive process. The de-embedding procedure is done after the measurements and is further explained in section 3.3.
Figure 3.2: The Summit 12000-AP CascadeMicrotech RF probe station
Figure 3.3: Setup used for I-V and small-signal measurements. The device analyzer used is a B1500A from Keysight. The network analyzer used is also from Keysight. The DC-signals from the device analyzer and RF-signals from the network analyzer are combined using bias tees.
Figure 3.4: The infinity probe with three contacts at the probe tip [28].
Figure 3.5: The Ground-Signal-Ground (GSG) configuration on the wafer. The configuration consists of an anode and cathode patch and four extra patches for grounding purposes.
3.1.3 Device analyzer, network analyzer and software
Both the DC and RF probe station are equipped with a device analyzer, B1500A from Keysight technologies. The device analyzer makes it possible to perform current-voltage by connecting with the probe station, by using Source-Measure-Units (SMU’s). This SMU allows sourcing and measuring at the same probe. The device analyzer provides the input for the probe station, this input can be set by external computer software.
The RF probe station is also equipped with a Network analyzer, the Agilent PNA, N5227A from Keysight. This network analyzer can supply small RF signals to the DUT with a frequency range of 100 MHz to 48 GHz [29]. The input for network analyzer is also set by external computer software.
The software used in this research is IC-CAP (Integrated Circuit Characterization and Analysis Program) by Keysight technologies. The IC-CAP software can also be used for extracting and analyzing the output of the measurements, although in most cases the output will be further analyzed with Matlab. More information on the B1500A device analyzer, the network analyzer and IC-CAP software can be accessed via references [30], [29] and [31] respectively.