Parameter extraction of superconducting integrated circuits

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(1)Parameter Extraction of Superconducting Integrated Circuits by. Pierre Lötter. Thesis presented in partial fulfilment of the requirements for the degree of Master of Science in Engineering at the University of Stellenbosch. Supervisor: Dr. C.J. Fourie Prof. W.J. Perold. December 2006.

(2) Declaration I, the undersigned, hereby declare that the work contained in this thesis is my own original work and that I have not previously in its entirety or in part submitted it at any university for a degree.. Signature: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P. Lötter. Date: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. i.

(3) Abstract Parameter Extraction of Superconducting Integrated Circuits P. Lötter Thesis: MScEng (Electric and Electronic) December 2006 Integrated circuits are expensive to manufacture and it is important to verify the correct operation of a circuit before fabrication. Efficient, though accurate, parameter extraction of post-layout designs are required for estimation of circuit success rates. This thesis discusses electrical netlist and fast parameter extraction techniques suited for both intraand inter-gate connections. This includes the use of extraction windows and look-up tables (LUTs) for accurate inductance and capacitance estimation. These techniques can readily be implemented in automated layout software where fast parameter extraction is required for timing analysis and gate placement.. ii.

(4) Uittreksel Parameter Extraction of Superconducting Integrated Circuits P. Lötter Tesis: MScEng (Electric and Electronic) Desember 2006 Geïntegreerde stroombane is duur om te vervaardig en die korrekte werking van ’n stroombaan moet voor vervaardiging verifieer word. Doeltreffende, dog akkurate, parameter onttrekking van na-uitleg ontwerpe word vir die bepaling van stroombaansukses verlang. Hierdie tesis fokus op elektriese skakellys en effektiewe parameter onttrekkingtegnieke, geskik vir gebruik vir beide intra- en inter-hek konneksies. Dit sluit die gebruik van onttrekkingvensters en opsoektabelle vir akkurate induktansie and kapasitansie in. Hierdie tegnieke kan sonder moeite in outomatiseerde uitlegsagteware, waar vinnige parameter onttrekking vir die doel van tydanalise en hekplasing verlang word, geïmplementeer word.. iii.

(5) Contents Declaration. i. Abstract. ii. Uittreksel. iii. Contents. iv. List of Figures. vii. List of Tables. ix. List of Abbreviations. xi. List of Symbols. xiii. 1 Introduction 1.1 Historical background of superconductivity 1.2 Superconducting integrated circuits . . . . 1.3 Circuit parameters and extraction . . . . . 1.4 Problem statement and thesis overview . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. 2 Layout extraction 2.1 VLSI structures and circuit models . . . . . . . . . . . . 2.2 Polygon decomposition and structure recognition . . . . 2.2.1 Polygon decomposition . . . . . . . . . . . . . . . 2.2.2 Structure identification and recognition . . . . . . 2.3 Structure connectivity and netlist extraction . . . . . . . 2.3.1 Node identification and path segment connectivity iv. . . . .. . . . . . .. . . . .. . . . . . .. . . . .. . . . . . .. . . . .. . . . . . .. . . . .. . . . . . .. . . . .. . . . . . .. . . . .. . . . . . .. . . . .. . . . . . .. . . . .. . . . . . .. . . . .. 1 1 2 3 4. . . . . . .. 6 6 8 8 9 11 12.

(6) v. CONTENTS. 2.3.2. Netlist extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3 Inductance extraction 3.1 Overview of inductance in superconducting ICs 3.2 3D inductance extraction . . . . . . . . . . . . . 3.2.1 Improved segmentation of 3D structures 3.2.2 An adaptive segmentation framework . . 3.3 Partial inductance . . . . . . . . . . . . . . . . 3.4 Inductance extraction via windowing . . . . . .. 13. . . . . . .. 15 15 19 19 21 24 24. . . . . . . . . .. 29 29 30 32 32 32 34 40 40 41. 5 Look-up tables and interpolation 5.1 Multi-dimensional interpolation . . . . . . . . . . . . . . . . . . . . . . . . 5.2 LUTs and interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 44 45 46. 6 Software implementation and results. 49. 7 Conclusion 7.1 Thesis overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Recommendations for future research . . . . . . . . . . . . . . . . . . . . .. 52 52 54. Bibliography. 55. A Mathematical derivations A.1 Two-dimensional computational geometry . . . . . . . . . . . . . . . . . . A.1.1 Area of a simple polygon . . . . . . . . . . . . . . . . . . . . . . . . A.1.2 Centroid of a simple polygon . . . . . . . . . . . . . . . . . . . . . .. 64 64 65 68. . . . . . .. . . . . . .. . . . . . .. . . . . . .. . . . . . .. . . . . . .. 4 Capacitance extraction 4.1 Introduction to capacitance . . . . . . . . . . . . . . . . . 4.2 Capacitance calculation techniques . . . . . . . . . . . . . 4.3 3D capacitance extraction . . . . . . . . . . . . . . . . . . 4.3.1 Structure segmentation and 3D capacitance models 4.3.2 Non-uniform discretisation . . . . . . . . . . . . . . 4.3.3 Method of images . . . . . . . . . . . . . . . . . . . 4.4 Capacitance extraction via windowing . . . . . . . . . . . . 4.4.1 Partition size and conductor shielding . . . . . . . . 4.4.2 Border extension . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . . . . . . .. . . . . . .. . . . . . . . . .. . . . . . .. . . . . . . . . .. . . . . . .. . . . . . . . . .. . . . . . .. . . . . . . . . .. . . . . . .. . . . . . . . . .. . . . . . .. . . . . . . . . .. . . . . . .. . . . . . . . . ..

(7) vi. CONTENTS. A.1.3 Line intersection and collinearity . . . . . . . . A.1.4 Point-in-polygon strategies . . . . . . . . . . . . A.2 Two-dimensional spatial transformations . . . . . . . . A.2.1 Matrix representation of spatial transformations A.2.2 Translation . . . . . . . . . . . . . . . . . . . . A.2.3 Scaling . . . . . . . . . . . . . . . . . . . . . . . A.2.4 Rotation . . . . . . . . . . . . . . . . . . . . . . A.3 Inter- and extrapolation . . . . . . . . . . . . . . . . . A.3.1 Polynomial interpolation . . . . . . . . . . . . . A.3.2 Rational function interpolation . . . . . . . . . A.4 Gaussian distribution . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . .. 69 70 72 73 73 73 78 79 79 80 81. B Algorithms and data structures B.1 Matrix data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.2 Geometry description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 84 84 85.

(8) List of Figures 1.1. Circuit extraction as part of a CAD framework for superconductor VLSI . .. 4. 2.1 2.2 2.3 2.4 2.5. 7 7 9 9. 2.7. Common microstrip structures in superconducting VLSI layout . . . . . . . . Equivalent lumped-element representation of commonly used VLSI structures Decomposition of a structure into its constituent parts . . . . . . . . . . . . Associative identification of corner and tee-junction structures . . . . . . . . BSD of CCW arranged tee-junction and corner. Anchor vertices are marked with asterisks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dimensions that uniquely define a right-angled corner and tee-junction microstrip structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Placement of sub- and IO nodes . . . . . . . . . . . . . . . . . . . . . . . . .. 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8. FastHenry segment with 3x5 filaments . . . . . . . . . . . . . . . . . . . . . Polygon segmentation with normal cake slicing . . . . . . . . . . . . . . . . . Improved cake slicing on angled polygons . . . . . . . . . . . . . . . . . . . . Cake slice mesh of a circular via . . . . . . . . . . . . . . . . . . . . . . . . . Special slicing to limit the creation of unnecessarily fine discretisations . . . Non-uniform mesh of a cake slice segment . . . . . . . . . . . . . . . . . . . Placement of X- and Y-directed FastHenry segments ( 31 of their actual width) Four conductors used to illustrate inductance extraction with windows . . .. 19 20 20 21 22 23 23 25. 4.1 4.2 4.3 4.4 4.5. 2D line-to-ground capacitance comparison . . . . . . . . . . . . . . . . . . . Non-uniform discretisation of a structure . . . . . . . . . . . . . . . . . . . . Uniform and non-uniform discretisation on panel requirement . . . . . . . . FastCap configurations for a two body problem . . . . . . . . . . . . . . . . Conductor-over-ground and it’s equivalent method of images formulation for capacitance calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 31 33 33 34. 2.6. vii. 10 11 12. 36.

(9) viii. LIST OF FIGURES. 4.6 4.7 4.8 4.9 4.10 5.1 5.2. Conversion of a 2n × 2n to a n × n capacitance matrix . . . . . . . . . . . . Two co-planar conductors and their respective mirror images . . . . . . . . . Percentage deviation from total capacitance as an consequence of neighbouring conductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Percentage deviation from S1 ’s total capacitance due to removal of S3 . . . . Length of border and deviation from true capacitance . . . . . . . . . . . . . Variation of cornered microstrip inductance with respect to width, thickness and height above ground plane (L1 , L2 = 18µm) . . . . . . . . . . . . . . . . Scatter plot of percentage deviation of rational function and polynomial interpolation to true simulated inductance values of a cornered microstrip (L1 , L2 = 18µm, t = 0.3µm and h = 0.585µm) . . . . . . . . . . . . . . . . . . . . . . .. 38 39 41 42 42. 46. 47. 6.1 6.2 6.3. Program flow for parameter extraction . . . . . . . . . . . . . . . . . . . . . JTL and its equivalent extracted netlist . . . . . . . . . . . . . . . . . . . . . Comparative simulation results for extracted and designed values . . . . . .. 49 50 51. A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 A.10 A.11 A.12 A.13. Some polygonal types . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallelogram method for area calculation . . . . . . . . . . . . . . . Trapezoidal method for area calculation . . . . . . . . . . . . . . . . . Intersection of two line segments . . . . . . . . . . . . . . . . . . . . . Winding number crossings . . . . . . . . . . . . . . . . . . . . . . . . Winding number example . . . . . . . . . . . . . . . . . . . . . . . . Polygon scaling by a positive distance . . . . . . . . . . . . . . . . . . Distance translation calculation . . . . . . . . . . . . . . . . . . . . . Cartesian quadrant placement of guide points . . . . . . . . . . . . . 2D spatial rotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . Representation of Neville’s recursion algorithm . . . . . . . . . . . . . Density function of a Gaussian random variable Y . . . . . . . . . . . Geometric representation of Gaussian density trigonometric functions. . . . . . . . . . . . . .. 65 66 67 69 71 72 75 75 76 78 80 82 83. B.1. 2D representation of a matrix storage scheme . . . . . . . . . . . . . . . . .. 84. . . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . . ..

(10) List of Tables 3.1. 4.1 4.2 4.3 5.1. A.1 A.2 A.3 A.4. Tolerance on Hypres’s 3.0µm process. Positive values represent over etching (area is larger on the wafer) . . . . . . . . . . . . . . . . . . . . . . . . . . . The effect of finite dielectric layers on capacitance calculations . . . . . . . . Four configurations to solve a two-conductor image problem, with a one volt source connected in turn to all conductors, keeping the rest at zero potential. Capacitance deviation using the method of images . . . . . . . . . . . . . . . Physical parameters of a cornered microstrip in µm. L1 and L2 are kept constant at 18µm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Truth Truth Truth Truth. table table table table. for for for for. placing dX . . . placing dY . . . horizontal edges vertical edges .. . . . .. . . . .. . . . .. . . . .. ix. . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. 18 32 37 40. 47 77 77 77 77.

(11) List of Programs B.1 B.2 B.3 B.4 B.5 B.6. Templated C++ class C++ class C++ class C++ class Templated. C++ class for 4D matrix construction for implementing 3D vertices . . . . . for representing arbitrary polygons . . for representing graph vertices . . . . . for representing weighted graph edges C++ class for representing graphs . .. x. . . . . . .. . . . . . .. . . . . . .. . . . . . .. . . . . . .. . . . . . .. . . . . . .. . . . . . .. . . . . . .. . . . . . .. . . . . . .. . . . . . .. . . . . . .. . . . . . .. 86 87 87 88 88 88.

(12) List of Abbreviations 2D. Two dimensional. 3D. Three dimensional. ANN. Artificial neural network. BSD. Binary shape descriptor. COSL. Complementary output switching logic. CCW. Counter-clockwise. CW. Clockwise. GP. Ground plane. HTS. High temperature superconductor. IC. Integrated circuit. JTL. Josephson transmission line. MPI. Message passing interface. LUT. Look-up table. MQM. Macroscopic quantum model. MVTL. Modified variable threshold logic. PEEC. Partial element equivalent circuit. PVM. Parallel virtual machine. xi.

(13) LIST OF ABBREVIATIONS. RSFQ. Rapid single-flux quantum. SBSD. Standardized binary shape descriptor. STL. Standard Template Library. VLSI. Very large scale integration. xii.

(14) List of Symbols π. 3.141 592 653 589 793 238 462 643 383 279 5. βc. Stewardt-McCumber parameter. βl. One-junction SQUID parameter. e. Elementary charge (1.602 177 33×10−19 C). 0. Permittivity of free space (8.854 187 817×10−12 F·m−1 ). r. Relative permittivity. ~. Plank’s constant (1.054 572 66×10−34 J·s). Hc. Critical field. Jc. Critical current density. λ. London penetration depth. λef f. Effective penetration depth of a thin-film superconductor. Φ0. Magnetic flux quantum (2.067 834 61×10−15 Wb). Tc. Critical temperature. xiii.

(15) Chapter 1 Introduction Although superconductors are practically limited by its temperature requirements, superconductivity has found applications in almost every technological field. No wonder with applications ranging from small scale applications, such as digital electronics and sensitive measuring equipment, to large scale applications that include very fast, magnetically levitated (maglev) trains, superconductors are considered by many to be the technology of the future.. 1.1. Historical background of superconductivity. Superconductivity is a physical quantum phenomenon first noted in 1911 by Dutch physicist H. Kamerlingh-Onnes, when he tried to measure the electric resistance of mercury at very low temperatures. His experiments demonstrated that, below a certain critical temperature (Tc ), mercury exhibits no resistance to the flow of electricity. Further experimentation revealed that superconducting materials revert to its normal conducting state when either the applied current density, or magnetic field rises above their respective threshold values, respectively known as critical current density (Jc ) and critical field (Hc ). Superconductivity is more than just perfect conductivity. For small applied magnetic fields, perfect conductors have been found to conserve flux. In 1933, however, W. Meissner and R. Ochsenfeld observed superconductors’ ability (given Hc is not violated) to expel flux, forcing a situation where the magnetic flux density in itself is zero. This perfect diamagnetic property is known as the Meissner effect. Mathematicians and scientists were compelled to find explanations for the superconducting phenomenon. In 1934 C. Gorter and H. B .G. Casimir proposed the two-fluid 1.

(16) CHAPTER 1. INTRODUCTION. 2. model when they realised that superconductors compose of two carrier types: normal electrons and super-electrons. A year later Heinz and Fritz London released their theoretical explanation of zero resistivity and the behaviour of superconductors in magnetic fields. Later Fritz London realised that superconductivity exhibits quantum mechanical properties and introduced the macroscopic quantum model (MQM) in 1948. MQM addresses, inter alia, flux quantisation in type-II superconducting materials and is of importance in understanding Josephson tunneling in Josephson junctions. In 1950 Vitaly Ginzburg and Lev Landau formulated the Ginzburg-Landau theory, that, apart from uniting the electromagnetic and quantum mechanical properties of superconductivity (like the MQM), it also includes thermodynamic properties. All these models are phenomenological and does not describe how superconductivity occur. In 1957 John Bardeen, Leon Cooper and Robert Schreiffer proposed the BCS-theory [1] that explains the microscopic behaviour of superconductivity. Weak superconductivity was discovered in 1962 by B. Josephson with his research into superconductor contacts. He noticed that current move spontaneously (without any applied voltage) from one superconductor to the next through a thin film of isolation. His discovery had led to numerous technological advances in superconductivity, id est sensitive magnetic flux detection through superconducting quantum interference devices (SQUIDs) and very fast digital electronics, such as complementary output switching logic (COSL) [2] and rapid single flux quantum (RSFQ) [3].. 1.2. Superconducting integrated circuits. Integrated circuits are a small scale application of superconductors and consist of Josephson junctions and thin superconductive film. Superconductor electronics are renowned for low noise levels, low energy consumption and high speed operation. Early development in digital superconductor electronics were based on a device called the cryotron. The cryotron consists of two magnetically coupled thin superconductive films, designed in such a way that a control current in the one would create a magnetic field that exceeds the Hc of the other line. Cryotron development was abandoned in the earlier 1960s due to its instability and the rather slow switching times (10 ns) obtained. The discovery of the Josephson effect encouraged new research into digital superconducting circuits, and in the 1970s IBM led the way in the design of a voltage-state logic Josephson junction computer. The project was dropped in 1983 but research into voltage-state logic.

(17) CHAPTER 1. INTRODUCTION. 3. continued. Modified variable threshold logic (MVTL) [4] in 1988 and COSL [2] in 1996 are of the few successful implementations of voltage-state digital circuits and were designed to operate at up to 2 GHz for MVTL and 10 GHz for COSL. In 1991 K.K. Likharev and V.K. Semenov presented a pulse-based logic known as rapid single flux quantum (RSFQ) [3]. This logic family is based on the fast (a few pico seconds) intrinsic switching speed of Josephson junctions. A T flip-flop has been shown to operate at 770 GHz [5] and more recently a 5000 gate 8-bit RSFQ microprocessor operating at 20 GHz (with a dynamic power consumption not exceeding 1 mW) was demonstrated [6, 7]. Fabrication of thin film circuits had evolved over the years. Lead (Pb) alloy films (used in the IBM project) were eventually replaced by more stable niobium (Nb) films. Non-planar multi-layered Nb circuits are currently produced by means of photolithography and etching [8]. Non-planar circuits are, however, prone to isolation faults between layers and strict layout rules are consequently enforced. On the other hand, planar fabrication processes allow for better isolation thereby allowing the fabrication of higher density superconductor circuits [9, 10, 11]. Y Ba2 Cu3 O7−x is mainly used in the fabrication of high temperature superconductor (HTS) circuits [12]. Although promising, this fabrication process is not as well defined as that of established Nb processes.. 1.3. Circuit parameters and extraction. Superconducting ICs are sensitive to current variation and distribution, and parameters that influence this must be calculated accurately. These parameters include Josephson junction critical current (Ic ), inductance, capacitance and resistance Circuit functionality and success rate (yield) can be evaluated through Spice simulation and Monte Carlo analysis [13, 14], and it is up to the designer to ensure that the physical layout is a true reflection of the simulated values. The lack of suitable computer-aided (CAD) tools for superconductor ICs force designers to do circuit layout be hand. Possible layout errors can result in unsatisfactory circuit performance, and even circuit failure, and must be identified by means of accurate post-layout parameter extraction. Circuit parameters are subject to fabrication tolerance that must be accounted for during the extraction and verification processes..

(18) 4. CHAPTER 1. INTRODUCTION. 1.4. Problem statement and thesis overview. This thesis focuses on layout-to-circuit extraction of post-layout superconducting ICs and forms part of the framework (Figure 1.1) proposed by Gerber [15]. Accurate and time efficient parameter extraction is required for routing and placement of interconnects (intraand inter-gate). Thanks to previous research efforts, gate elements are well defined and optimised to deliver the highest possible yield [16], but little is known of long interconnections between these gates. This thesis investigates established techniques to efficiently extract inductance and capacitance from VLSI circuits. The extracted parameters can then be used to calculate transmission line properties such as signal propagation speed and attenuation. Behavioural capture. Logic synthesis. Technology. Circuit management. Timing optimizer. Routing and placement. Circuit extraction. Figure 1.1: Circuit extraction as part of a CAD framework for superconductor VLSI. Chapter 2 presents an overview of commonly found structures in superconductor ICs with their corresponding lumped circuit element representations. Methods to recognise these structures, for purpose of netlist extraction and use in look-up tables, are discussed. In Chapter 3 an overview of previous research and findings into inductance extraction of superconducting ICs are presented. Furthermore, an improved meshing technique for FastHenry models is discussed, whereafter the chapter is concluded with a discussion of efficient inductance extraction by means of partial elements and extraction windows. Chap-.

(19) CHAPTER 1. INTRODUCTION. 5. ter 4 introduces the reader to capacitance extraction with reference to non-uniform discretisation of structures, the method of images and extraction windows. Look-up tables and multi-dimensional interpolation techniques are discussed in Chapter 5 whereas Chapter 6 provides an overview of a C++ computer program for use in parameter extraction. Parameters from a Josephson transmission line (JTL) is extracted..

(20) Chapter 2 Layout extraction Accurate layout-to-circuit extraction relies on knowledge of the type of structures to be analysed, fabrication process variation and the use of appropriate parameter extraction techniques. This chapter presents the reader with techniques to handle non-rectangular shapes, recognise key structures and ultimately assemble a netlist for simulation purposes. Additionally, a technique to recognise structures in look-up tables is presented.. 2.1. VLSI structures and circuit models. Before a discussion of layout extraction, it is appropriate to present six commonly found VLSI structures (Figure 2.1) and their equivalent circuit representations (Figure 2.2). These circuits consist of passive lumped elements, specifically inductors and capacitors. In creating the equivalent circuit representations, a few assumptions regarding layout structures are made. Firstly, all microstrip lines are assumed to be uniform in width. Secondly, in the case of crossing lines (Figure 2.1 (c)), an electrical node is placed such that the centroid of the line-overlap area is also the centroid of both lines. In conjunction with the uniform width assumption this results in the Figure 2.2 (c), where line inductance is halved at the overlap node.. 6.

(21) 7. CHAPTER 2. LAYOUT EXTRACTION. (a) Uniform. (b) Parallel. (c) Crossing. (d) Corner. (e) Tee-junction. (f) Via-connected. Figure 2.1: Common microstrip structures in superconducting VLSI layout. 1 2C .... 12 . 1 2 Cg1 ... ...... ..... ... L. ........ ......... ......... ........ .... ........ ........ ........ .... .. ..... .... ......... .... ... ... ... ... .... ... ...... ..... ... r. 1 2 Cg. ........ ...... ........ r. r. 1. ... ............... 1 2 Cg1. ...... .... .... ................. .. .......... .... ................ ............. ..... ... ......... ................. . ..... .... ........ ........ ... . .. ............................. ... . . ............................. ... . . .............................. . .. . . .......... ................. ..... .. ... ... ... ... ... .... ... ... ..... ... .... 1 2 Cg2. 1. ......... ...... ...... 2. 1 ................... 2 Cg1... Cg1. ... ...... ...... ... 1 2 L1. 1 2 L1. ... ...... ...... ... r. ....... ........ ........ ....... ..... ....... ........ ........ ..... .. .... .... ........ .... ... ... .... .... ..... ................................................................ ..... .... ........ .... .... ... ... ... .... r. ... ...... ...... ... .............. ..... r. 12 .................... .... ..... ..... ... ..... ...... ...... .... ...... ........... ........... ............ ....... ..... .......... .......... .......... ...... ... .... .... ......... ..... .... ... ... ..... .... .... ... .... ... ... .... .... .... ... .... ..... r. .............. ..... r ...... C. L2. r. r. r. r. r. r. L1. Cg. ..... ................... .. ... ...... ...... ... ......... ...... ...... 2. ... . ... ... ..... ..... .................. r. ... ...... ...... ... .................. ...... 1 2 Cg2. r. 1 2 L2. 1 2 L2 1 ........... ..... ..... 2. 1 ................ 2 Cg2... ... Cg2. 1 2 C12. (a) Uniform. L1. .............. ..... ....... ........ ........ ....... ..... ........ .......... ........ ..... ... ..... ... ......... ..... ... ... .... ... ..... L2. Cg r ......... ... .. ........................... .. .. . . . . . . . . . . . . . .............. .. .. ........................... .. ... .......... .............. ..... (a) Corner. (c) Crossing. (b) Parallel. .. ... ..... ... ... ............. ..... L2. Cg. La. ................................................................. .... .... ........ .... .... ... ........... ..... .... ... .... r ...... L. ................. b ..... . .......... ........... ........... ......... .......... ........... ........... .......... .... ........... ........... .......... ....... .... ........... .......... .......... ...... ... ... ... ... ... ... ... ... ... .. ... .. ... ... . . .... .... .... .... .... .... ......... ... .. ............................... .. .. . ................. 2 ............... . . ............................ .. . ... .......... r. ... ...... ...... ... ......... ... .. ........................... .. ... .......................... .. ... ............................ . 1 .. . . . ... .... ..... ..... ... ...... ........... ............ ............. ....... .... ... .... .... ........ .... .... ... .... .... ..... Lv. L. L. ..... .............. r. .............. ..... (b) Tee-junction. (c) Via-connected. Figure 2.2: Equivalent lumped-element representation of commonly used VLSI structures.

(22) CHAPTER 2. LAYOUT EXTRACTION. 2.2. 8. Polygon decomposition and structure recognition. The use of Manhattan-shaped structures in VLSI layouts are popular for the ease with which they can be implemented. The designer may, however, not always find it appropriate to implement such structures. Chamfered (mitred) bends, for instance, can reduce reflections in sensitive parts of the layout and recently Hypres recommended the use of circular Josephson junctions [8]. As the shapes introduced in VLSI layouts are becoming more complex, methods to efficiently recognise layout structures are required.. 2.2.1. Polygon decomposition. Layout structures are often composed of a combination of simple convex polygons. To ensure structure uniformity for recognition and node placement purposes, all these polygons first need to be combined into a single structure. A complex layout structure is presented in Figure 2.3. This structure is made up of two basic structures; an unsymmetrical teejunction and a right-angled corner. Although these structures are easily recognisable by humans, computers require complex algorithms to characterize such structures. Complex, non-Manhattan geometries can easily be broken up into simpler convex polygons to form path segments [17]. Firstly, the polygonal structure is analyzed and concave inner angles are identified. Angles are formed by two edge vectors that join at a vertex. The cross product of these vectors results in whether the angle is convex or concave. This characteristic is assigned to the corresponding vertex. Subsequently, virtual break lines are created by extending the edges of a concave corner to opposite polygonal edges. These virtual lines are illustrated as dotted lines in Figure 2.3(a). Notice that virtual break lines 1, 2, 3 and 6 cross each other. These crossings are unwanted and may result in multiple parallel connected path segments, consequently complicating netlist extraction. Assuming quasi-static circuit behaviour, and therefore that current flows only down the length of a conductor, the longest crossing virtual break line is removed. As an example, assume the polygon vertices are arranged in a counter-clockwise (CCW) direction. Break lines 1 and 2 are compared for intersection to those extending from the following concave vertex. 1 intersects with both 3 and 6. The longest break line is removed (3, not 6). Virtual break line 2 is now considered and found that it does not intersect with any of the virtual break lines from the current concave vertex. The following concave vertex (origin of break lines 5 and 6), however, yields an intersection with 2. In the same way as above, 6 is deleted when compared to virtual break line 2. The eight virtual break.

(23) 9. CHAPTER 2. LAYOUT EXTRACTION 4...... 1. 6. ....... .... ....... ...... .. ....... .. .. .. .. .. .. .. .. .... . . . . . ...... . . . . . . . . . . . . . . .......... ... ..... ..... . ..... ............... . .. ....... ..... ........ . ..... ..... . ..... ..... . ..... .... .. .. .. .. ........... ... 4. 3. 2. 2. 5. 5. . . . . . ............... . . . . ....... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... .. ..... ..... ..... ..... ..... ..... ..... .. .. .. ..... ..... ..... ..... ..... ..... ..... ..... ..... ... .............. ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ... 1. ....... ........ . ..... . ..... .. . .. . .. .. .. .. . .... .. ...... . . . . . ...... . . . . . . . . . . . . . . . . ..... ..... ..... .. ... ............ . .. . . ..... ..... . ..... ..... . ..... ...... ..... .. . .. .. .. .. ...... ......... . . . . . ............... . . . . ........ .... 8. 8. 7. 7. (a). (b). (c). Figure 2.3: Decomposition of a structure into its constituent parts. lines are reduced to six (Figure 2.3(b)) and the polygon is decomposed along the break lines (Figure 2.3(c)).. 2.2.2. Structure identification and recognition. Polygon decomposition provides for a common structure recognition framework. Structures are identified by analysing associative polygonal connectivity. Structure identification A uniform framework for polygon identification is created by first decomposing a complex structure into path segments. Uniform microstrip (including parallel and crossing combinations) are easily identifiable because of their single polygonal representation after decomposition. Corners and tee-junctions, on the other hand, compose of respectively three and four path segments. s 1. ..... ........ ..... ..... ..... ..... ..... .. .............. ..... .... ..... . .............. ..... ..... ..... . .............. ..... .... .. .. .............. ... .. ....... ..... ..... ..... ........ .... .......... ..... .......... ..... ..... ..... ..... .. .......... . ..... ... ..... .. ..... .... ... . ..... . ..... ...... ..... ... ss. 2. ss ss. 3. s. 4 s s. s. 7. 5 s.. ..... ... ..... ...s . .. . . . s..s 6 ..... ... . ..... ..... ..... ... Figure 2.4: Associative identification of corner and tee-junction structures.

(24) 10. CHAPTER 2. LAYOUT EXTRACTION. With reference to Figure 2.4, a corner is formed by a segment (6) that has two consecutive edges connected to two other segments (5 and 7); a tee-junction (2) , three consecutive edges (1, 3 and 4). Intuitively this structure consists of a tee-junction (2) and a corner (6). With closer inspection 4 is also found to form a corner (two consecutive connected edges and a discontinuity, albeit very small). Structure recognition Structure identification provide enough information to successfully extract a connectivity netlist from physical layout, however, it proves not to be sufficient for matching structures to a look-up table. Exact vertex and edge matching are required and achieved with a twostage framework for recognizing structures [18]. This framework uses a model approach to first identify a structure based on its shape, where after a data approach matches its dimensions. The model approach employs the Binary Shape Descriptor (BSD) which maps a polygon to an equivalent binary string. The binary string is a representation of the convexity and concavity of polygon vertices. A ’0’ denotes a convex vertex, a ’1’ a concave vertex (Figure 2.5). This approach is scale and orientation invariant, but the bit sequence relies on an anchor vertex. The tee-junction in Figure 2.5 can be represented by eight BSDs, depending on the anchor vertex. The Standardised BSD (SBSD) is introduced [19] in order to obtain an unique BSD for a given shape. This is achieved by selecting the smallest binary magnitude as the SBSD. The SBSD for the tee-junction then becomes “00001001”. 0 0 1. 1. 0∗. 0. BSD=00100001. 0. 0. 0. 0. 0. 1. 0∗. 0. BSD=000001. Figure 2.5: BSD of CCW arranged tee-junction and corner. Anchor vertices are marked with asterisks. BSDs only record the concavity and convexity of polygon vertices. This is sufficient to uniquely describe right-angled (Manhattan) structures, but may fail where structure.

(25) 11. CHAPTER 2. LAYOUT EXTRACTION. descriptions require finer interior angle descriptions. The N -ary Shape Descriptor (NSD) generalize the BSD to include more interior angle divisions. Let NSDk denote a NSD where k is the number of discrete angle divisions and ∆i the interior angle of the ith vertex. Now NSDk = a1 a2 . . . an−1 an where n is the number of vertices of the polygon and ai = j, j ∈ {0, 1, . . . , k − 1} ,. jπ (j + 1)π ≤ ∆i ≤ k k. The second stage handles matching queries. Structures are uniquely defined by their vertex and edge descriptions. LUTs, however, only keep information that uniquely describe a structure, as illustrated in Figure 2.6. The different dimensions (l1 , w1 , et cetera) are each associated with a column in the LUT. For successful LUT searches it is imperative that these dimensions are associated with their corresponding columns. Column mapping for a SBSD representation of a tee-junction, for example, is represented as “0wb 00wa 0la 10w2 01lb ”. .................. . . . . .. . . . . . ......... .. .. wa. .. ... .. ..... ...... la. .................. . . . . . . . . . . . . . . . .. .......... ....... . . . . . . . . . . . . . . . .. lb. .......... ....... . . . . . . . . . . . ...... ... ... ... wb. ... .. .... . . . . . . ..... .................. . . . . .. . . . . . ......... .. .. l1. ........... ....... . . . . .. w1. .. ... .. ..... ...... . . . . .. ...... .. ... .... l2 * .... . . . .................. . . . . . ........... ........ * .... . . . .................. w2. (a). ... ... ... . . . . . ...... . . . . ........... ........ w2. (b). Figure 2.6: Dimensions that uniquely define a right-angled corner and tee-junction microstrip structures. 2.3. Structure connectivity and netlist extraction. Effective and realistic layout-to-circuit extraction relies partly on identifying structure connectivity. This section lends itself in describing how connected netlists are extracted from physical layouts. We first consider path segment connectivity and node identification, whereafter the use of graphs structures, to represent netlists, is discussed..

(26) 12. CHAPTER 2. LAYOUT EXTRACTION. 2.3.1. Node identification and path segment connectivity. As complex structures are composed of different combinations of convex polygons, it is foremost important to first combine and then decompose these structures into its elemental polygonal description as described in Section 2.2.1. The reason for this is twofold: firstly to establish common ground from where node structures can be identified, and secondly, to constitute current path segments whose individual edges connect to, at most, one other path segment. With investigation into a typical RSFQ circuit and its physical layout, four types of electrical nodes are identified: via, junction, sub, and input/output (IO) nodes. Via nodes connect different physical layers (usually different elements, id est, resistor and inductor), whereas junction nodes identify Josephson junctions. Sub nodes, on the other hand, are assigned to path segments that initiate directional change and include corners and tee-junctions (see Figure 2.7 (a)). Furthermore, sub nodes are also defined where electromagnetic coupling to other segments occur. Identification of IO nodes may, at first, not be obvious. Whereas all previously discussed nodes are spatially defined to be at their respective path segment’s centroid, IO nodes are situated on segment edges (Figure 2.7 (b)). In Chapters 3 and 4 it will become clear that parameter extraction, especially 3D extraction, results in computational intensive calculations and because of this, big layout structures need to be segmented into smaller parts. IO nodes are defined at these segmentation cuts and establish a connection between the different sub structures.. (a) Sub nodes. (b) IO nodes. Figure 2.7: Placement of sub- and IO nodes. Nodes are connected by consecutive path segments, segments which are obtained by means of polygon decomposition (as described in the previous section). Segment connectivity is determined by obtaining polygons in close proximity to each other (on the.

(27) CHAPTER 2. LAYOUT EXTRACTION. 13. same physical layer) and testing for overlap collinearity between the edges of the different polygons (see Section A.1.3). Pointers to polygons are consequently assigned to collinear edges, with every polygonal edge having no more than one pointer to another polygon (Program B.3 line 10). From here a netlist, that describes path segment interconnectivity, can be generated.. 2.3.2. Netlist extraction. Graph theory provides an efficient and logical method to represent netlists. A graph consists of a set of edge connected vertices, mathematically expressed as G = (V, E). The nodes defined in the previous section are implemented as vertices; path segments connecting these nodes, as edges. An edge can only connect two vertices, the edge being directed or undirected. If a directed edge leads from vertex A to vertex B, A is called the predecessor of B, and B, in turn, the successor of A. Furthermore, graphs can be represented in different ways, with adjacency matrices and adjacency lists being the most popular. For this purpose, a variation on adjacency lists will suffice. By storing graphs purely as adjacency lists, if care is not taken, multiple edges may be created during graph construction. These multiple edges may present compatibility problems with known graph algorithms as two vertices are normally connected by a single edge. To retain compatibility, successors to vertices, in conjunction with their associated edge values, are stored in a STL map data structure. This data structure allows a edge value to be assigned to a single instance of the successor vertex, so prohibiting the creation of multiple edge connections between two vertices. A templated C++ class of the adjusted adjacency list graph representation is presented in Program B.6. In electric circuits, however, one often finds parallel connected elements. For example, in niobium RSFQ technology, Josephson junctions are normally damped by a parallel connected resistor to ground. To allow these parallel connections in a graph, weights are assigned to the connecting edges. These weights are implemented using the STL’s multimap data structure (Program B.5). The calculated element value, as well as a vector of pointers to associated polygonal structures between the two pre-determined nodes, are indexed by an integer representation of the element type (id est resistor, junction, inductor, et cetera). A multimap allows for multiple instances of an element type, thereby making a representation of parallel connected elements possible. Graph vertices are furthermore defined to be spatial sensitive, in that it is assigned physical coordinates, as well as pointers to the polygons where these coordinates reside. Program B.4 illustrates the vertex definition..

(28) CHAPTER 2. LAYOUT EXTRACTION. 14. Netlist generation and component identification provide a framework from where electrical parameters can be extracted.. Chapter review Polygon decomposition and current path identification provide a means for accurate accurate netlist extraction. The Binary Shape Descriptor (BSD) allows for structure descriptions for use in look-up tables..

(29) Chapter 3 Inductance extraction Previous research into superconductor inductance extraction has concluded that 3D extraction methods are required to accurately model complex structures [16]. 3D extraction requires copious amounts of computing resources, and as a result mostly smaller intragate inductances were previously investigated. For automatic routing and placement of structures for VLSI, full 3D inductance extraction is not viable. This chapter presents an improved segmentation framework for FastHenry structures, whereafter efficient inductance extraction are discussed with reference to PEEC and window techniques.. 3.1. Overview of inductance in superconducting ICs. Unlike in semiconductor digital circuits where voltage effects are important, superconductor circuits are current controlled. Accurate modelling of inductance is of interest as inductance influences bias current distribution throughout the circuit. Chang presents an analytical solution for a stripline-above-ground problem [20] and follows it up with a numerically approach for modelling mutual inductance [21]. The 2D nature of these formulations only allow for accurate modelling where stripline length is much larger than width. For small length-to-width ratios, end-of-line magnetic fringing have a prominent effect on self inductance, and 2D techniques overestimate the inductance. It is furthermore difficult to predict inductance of line discontinuities such as corners and vias using 2D calculations. In pulse logic superconducting (RSFQ) circuits, inductance is in the order of a few pico henry. To attain such low values, wide superconducting structures are implemented, resulting in a low length-to-width ratios. 3D numerical modelling is as a result required for accurate self and mutual inductance estimation. 15.

(30) 16. CHAPTER 3. INDUCTANCE EXTRACTION. Mutual inductance Mutual inductance is of importance in current controlled circuits where a control current induces current into a victim loop through inductive coupling. Mutual inductance in terms of self inductance is M =k. p L1 L2. (3.1). where M is the mutual inductance, k the coupling factor and L1 , L2 the self inductance of two conductors [22]. Chang’s 2D numerical formulation allows for mutual inductance calculation, but usually overestimates the coupling factor Josephson junction integrated circuits. This can be ascribed to sections close to Josephson junctions that do not contribute to inductive coupling [23]. Mutual inductance is best calculated with 3D methods.. Josephson junction damping RSFQ logic is based on slightly overdamped Josephson junctions. The Stewardt-McCumber parameter βc =. 2e ~. . 2 Ic Ref C. (3.2). −1 with Ref = Rn−1 + Rs−1 , is chosen close to 1. Ic is the critical current, C the capacitance and Rn is the normal resistance of the Josephson junction. Rs is the impedance connected to the junction [24]. Rs is included as a resistor in parallel with the junction. In physical circuit layout, damping resistors also account for additional inductance to ground. The one-junction SQUID parameter. βl = 2π. LIc Φ0. (3.3). is recommended to be smaller than 0.3, but never bigger than 0.8 [3]. L is the damping resistor’s inductance, Ic the junction critical current and Φ0 the magnetic flux quantum. Numerical extraction of damping inductance from layout reveals that L is very close to the upper limit and this attributes to oscillations (underdamping) when the junction switches. A method is proposed to minimize L during layout by creating a direct short-circuit from the damping resistor to ground. This is in contrast to the conventional method where the resistor connects through a via to ground [25]. Monte Carlo yield estimation proves that L does not have a noticeable influence on circuits success rate, provided that the circuits.

(31) CHAPTER 3. INDUCTANCE EXTRACTION. 17. are not clocked close to their maximum operating frequency [26].. Moats SQUIDs are very sensitive to magnetic flux. A SQUID is formed when one or two Josephson junctions are inserted in a superconducting current loop, as is the case in superconducting ICs. During the cooling process, flux may be trapped, not allowing the circuit to function correctly. The etching of rectangular channels (moats) in the GP close to Josephson junctions are claimed to capture unwanted magnetic flux [27]. It was later verified that moats indeed trap magnetic flux [28]. From numerical simulation it is found that moats do not significantly influence inductance of nearby structures [23]. Moats that cross underneath transmission lines however, increase its inductance as current is diverted from the shortest return path [29].. Method of images 3D numerical inductance estimation often requires large meshed ground planes (GPs). The method of images (where the ground plane is replaced by a reflection plane) is a technique often used in numerical computation to reduce the number of segments required in simulations. This is achieved by creating a mirror image of the structure, evenly spaced about a reflection plane, so avoiding the need for large segmented superconducting GPs. An earlier publication assumes the reflection plane to be at the upper boundary of the GP [30]. With the assumption that only surface currents flow on the GP (and thereby ignoring the effect of penetration depth), this formulation only holds true for superconducting geometries much larger than the penetration depth. For integrated circuits, however, all geometries (including isolation layers and GPs) are of the same magnitude as the penetration depth. [31] tried his hand at numerically calculating the position of the reflection plane but did not publish any results. A more recent paper [32] shows that for thin film structures the plane should be placed at the effective penetration depth below the upper boundary of the GP defined by λef f. d = λ coth λ. (3.4). with d the thickness of the superconducting film and λ the London penetration depth. The accuracy of (3.4) has been numerically verified for superconducting structures with length-to-width ratios larger than 1 [33]. For small length-to-width ratios excessive mag-.

(32) 18. CHAPTER 3. INDUCTANCE EXTRACTION. netic field fringing results in the underestimation of inductance [20], leading to large discrepancies when the method of images is used.. Parameter variation Inaccuracies in mask dimension and layer thickness (as a result of fabrication process tolerance) allow for a certain amount of variation in component values. The variations in turn may have an adverse impact on circuit success rate and need to be taken into consideration during the design process. A previous study has shown fabrication tolerance account for about 2% in inductance variation for realistic layout line widths [23]. Monte Carlo fabrication tolerance models can predict success rate (yield) of circuits by randomly varying global and local parameters [14]. Variation in layout dimensions can also be modelled directly with 3D extraction tools. This requires repetitive simulations that are time consuming to execute, but provide insight into inductance spreads as a result of fabrication tolerance. Throughout this thesis reference is made to Hypres’s fabrication process [8]. Table 3.1 contains a summary of the different metal and isolation layers used. Process variations are also tabulated. Table 3.1: Tolerance on Hypres’s 3.0µm process. Positive values represent over etching (area is larger on the wafer). Layer M0 I0 M1 I1A R2 I1B M2 I2 M3 R3. Thickness (nm) 100 ± 10 150 ± 15 135 ± 10 45 ± 5 100 ± 20 100 ± 10 300 ± 20 500 ± 40 600 ± 50 350 ± 60. Mask offset (µm) 0.2 ± 0.25 0.2 ± 0.25 −0.3 ± 0.25 −0.27 ± 0.05 0.0 ± 0.25 −0.1 ± 0.25 −0.2 ± 0.25 0.1 ± 0.25 −0.3 ± 0.25 0.0 ± 1.0. Layer properties N b, λL = 100nm ± 5% fF Si O2 , 0.277 µm ± 20% N b, λL ≈ 100nm Radius offset for circular junctions Ω ± 20% M o, 1.0 Contact hole to M1,I1A and R2 N b, λL = 90nm ± 5% Contact hole to M2 N b, λL = 90nm ± 5% Ω T i/P dAu, 0.02 .

(33) CHAPTER 3. INDUCTANCE EXTRACTION. 3.2. 19. 3D inductance extraction. FastHenry is a 3D inductance extraction tool developed at Massachusetts Institute of Technology [34], and makes use of a volume-discretised magneto-quasistatic PEEC formulation and a rapid converging iterative technique. Superconductor support for FastHenry [35] allows for accurate extraction of inductance. Due to the integral formulation used by FastHenry, layout structures must be segmented to accurately model current distribution in all axial directions. Additionally, filaments are used to allow for non-uniform current distribution due to penetration depth (see Figure 3.1).. Figure 3.1: FastHenry segment with 3x5 filaments. Segmented 3D models have previously been investigated and described in detail [16]. These models were created with the so called cake slice method. This section is aimed at introducing an improved cake slice method that incorporates adaptive meshing and eliminates the unnecessarily fine segments created as a result from normal cake slicing.. 3.2.1. Improved segmentation of 3D structures. InductEx is a tool developed to provide an interface to FastHenry [23] and creates the required segmented models by means of the cake slice method. This method involves dividing structures by means of horizontal and vertical slices, spaced according to a user-defined distance. Mesh segments are defined by the areas contained between two consecutive horizontal, and vertical, edges. Only segments that overlap the structure are retained. This technique is illustrated in Figure 3.2. Although InductEx presents an effective interface to FastHenry, it is limited in only accepting Manhattan-shaped structures. The cake slice method is refined to present a framework for non-Manhattan and adaptive meshing. The following explanation into meshing angled structures is illustrated in Figure 3.3. Initially the same procedure apply as that for meshing Manhattan-shaped structures. Slices.

(34) 20. CHAPTER 3. INDUCTANCE EXTRACTION. (a) Horizontal and vertical edge extensions. (b) Add additional horisontal and vertical slices. (c) Generate rectangles. Figure 3.2: Polygon segmentation with normal cake slicing. are created along all horizontal and vertical oriented polygonal edges, extending to the structure boundary. Angled edges are then divided horizontally (by means of vertical slices), limited by the maximum allowable segment size (a). Horizontal slices are created through the intersection points of the angled edge and previously created vertical slices (b). Only segments that completely overlap with the structure are retained (c). This type of meshing allows aligned segments to be created, ideally suited for placement of FastHenry’s electrical nodes. Figure 3.4 illustrates the effectiveness of cake slices, as a meshing technique, on a circular via. All segment overlaps are discarded to create the hole. The via is approximated by twelve vertices.. 0000000000000000000000000000000000 1111111111111111111111111111111111 1111111111111111111111111111111111 0000000000000000000000000000000000. (a) Divide angled edge with vertical slices. (b) Create horizontal slices through edge intersection points. (c) Create segments from enclosed areas. Figure 3.3: Improved cake slicing on angled polygons.

(35) CHAPTER 3. INDUCTANCE EXTRACTION. 21. Figure 3.4: Cake slice mesh of a circular via. Cake slicing, as a segmentation technique, has another shortcoming. Slices are created to extend the total bounding area of the structures to be meshed and may lead to the creation of unnecessarily fine discretisations. These small segments may not as much influence the accuracy of the answer obtained through simulation, as it does simulation time. Figure 3.5 (a) depicts a scenario where unnecessary segments (shaded areas) are created. A possible solution to this problem is presented whereby directional changes, as well as inter-connectivity between the constituent convex polygons of the structure, are considered. The shaded areas in (b) are defined as corners and represent directional changes. Tee-junctions also attribute to intra-layer directional change and the following procedure apply to them as well. Take a corner (2) and traverse through all connected, and not previously visited, polygons until another corner (4) or the end of the structure (1) is found. All traversed polygons are flagged as visited. Polygons 1, 2, 3 and 4 now constitute the new bounding area. Slices are only created parallel to the direction of traversals, that is horizontal slices for polygons 1 and 2 and vertical slices for 2, 3 and 4 (Figure 3.5(c)). The only exception to this rule is angled edges, and they should be handled as previously described, by creating both vertical and horizontal slices. Polygon 4 is the next corner and has only one direction of traversal because polygon 3 has already been visited. Only horizontal slices are created for polygons 4, 5 and 6 (Figure 3.5(d)). The same procedure applies for corner polygons 6 and 8, and 8 and 9, ultimately resulting in (e). Subsequently the created segments can individually be refined according to the segmentation specification.. 3.2.2. An adaptive segmentation framework. In corner structures, for example, current is not evenly distributed throughout the conductor. Current density tends to peak at the inside vertex of a corner. Structures should.

(36) 22. CHAPTER 3. INDUCTANCE EXTRACTION. 1. 2. 8. 3. 7. 4 (a). 1. 8. 7. 3. 7. 6. 4. 8. 3 4. 5. (c). 9. 6. (b). 2. 2. 5. 9. 1. 5. (d). 9. 6. (e). Figure 3.5: Special slicing to limit the creation of unnecessarily fine discretisations. be sufficiently segmentized at high current density areas to ensure accurate modelling. A non-uniform mesh is proposed. A structure is first segmentized by means of cake slices. The resulting segments are not directly used as input to FastHenry, but rather serve as reference for electrical node placement (Figure 3.1) and are from hereon referred to as cake slice segments. Electrical nodes are placed at the centre of every edge, as well as a single node at the centroid of the cake slice segment (Figure 3.6(a)). Additionally the segment is divided into three equally spaced horizontal and vertical segments (b). This way of division (rather than just dividing it in two) allows for the correct alignment of nodes for FastHenry segment placement, and establishes a means for non-uniform segmentation as illustrated in (c) and (d). Every segment in (c) is a cake slice segment which, in turn, serves as a framework for placing FastHenry segments..

(37) 23. CHAPTER 3. INDUCTANCE EXTRACTION. (a) Place electrical nodes. (b) Divide the segment into nine parts, appropriately placing new nodes. (c) Left bottom corner is divided to create a non-uniform mesh. (d) Non-uniform mesh with nodes removed for clarity. Figure 3.6: Non-uniform mesh of a cake slice segment. To model current flow correctly, FastHenry introduces X-, Y- and Z-directed segments. These segments are referred to as FastHenry segments. X- and Y-directed segments account for non-uniform current flow across the structure, whereas Z-directed segments model current flow through via structures. Figure 3.7 illustrates how X- and Y-directed FastHenry segments are defined with reference to a cake slice segment, which is denoted by a dotted line. FastHenry segments actually cover the complete cake slice segment, but are, for visualization purposes, illustrated to be one third ( 13 ) of their actual width.. (a) Place X-directed FastHenry segments. (b) Then place Y-directed FastHenry segments. Figure 3.7: Placement of X- and Y-directed FastHenry segments ( 13 of their actual width).

(38) 24. CHAPTER 3. INDUCTANCE EXTRACTION. 3.3. Partial inductance. Unlike that of capacitance, the accurate modelling of inductance is very difficult. The problem is twofold. Firstly, inductance is a property of closed current loops and the current path needs to be known beforehand. In complex integrated circuits these loops are difficult to determine or typically not known a priori. Secondly, inductance is along range effect. In other words, unlike electric field lines that terminate on neighbouring conductors, magnetic fields lines do not. This makes it difficult to accurately model the effect of mutual inductance in integrated circuits. Ruehli addresses the issue of unknown current paths by proposing a technique to model large interconnected circuits using lumped elements. This is known as partial equivalent element circuits (PEEC) [36] in which the current path is divided into smaller segments. All segments are defined as forming its own current loop with infinity. The self inductance on each segment and the mutual inductance between segments are calculated and combined into a dense partial inductance matrix. The loop inductance is equivalent to the accumulated partial self and mutual inductances of a segment [37], and is illustrated with the following relation Lab,loop =. XX i. sij Lij,partial. with sij = ±1. (3.5). j. where Lab is the mutual inductance between loops a and b, with i and j their respective segments. sij = −1 if one of the currents in either segments i or j is flowing in an opposite direction originally assumed when the partial inductance matrix was calculated. Laa is the self inductance of loop a.. 3.4. Inductance extraction via windowing. Partial inductance only addresses the issue of unknown current paths. The slow decay of mutual inductance introduced by the dense partial inductance matrix makes it inefficient to analyse. A localised extraction technique is required to sparsify the partial inductance matrix. Devgan et al. introduce a new circuit element K (called partial reluctance) which has capacitance-like locality [38]. [K] is defined as the inverse of a partial inductance matrix [L].

(39) 25. CHAPTER 3. INDUCTANCE EXTRACTION. [K] = [L]−1. (3.6). The locality of K is illustrated in the following example. Consider four conductors in Hypres’s M2 layer, each with width and spacing of 2.5µm (Figure 3.8). Current flows down the length of the conductors, injected at the electrical nodes illustrated.. Figure 3.8: Four conductors used to illustrate inductance extraction with windows. The partial inductance matrix of the interconnect structure is    L=  . 9.257 4.908 4.060 3.490. 4.908 9.152 4.789 4.024. 4.060 4.789 8.945 4.693. 3.490 4.024 4.693 8.995.     × 10−12 H  . The partial reluctance matrix, K, is the inverse of L    K=  . 161.480 −62.636 −29.727 −19.124. −62.636 184.590 −54.833 −29.669. −29.727 −54.833 186.880 −61.463. −19.124 −29.669 −61.463 163.920.     × 109 H −1  . The locality of partial reluctance can be demonstrated by removing conductors S2 and S3 . Based on the definition of partial inductance, this will have little or no effect on mutual inductance l14 . On the other hand, mutual reluctance k14 should be much higher to support the claim of locality. " # 9.240 3.484 L0 = × 10−12 H 3.484 9.240.

(40) 26. CHAPTER 3. INDUCTANCE EXTRACTION. " K0 =. 126.160 −47.570 −47.570 126.160. # × 109 H −1. Whereas the mutual partial inductance of S1 and S4 differs only by 0.7%, their mutual partial reluctance is 250% higher. This illustrates that S2 and S3 act as shields for partial mutual reluctance k14 . This relation between K and L allows the use of windows to extract partial inductance. Although K reveals some similarity to a capacitance matrix concerning locality, shielded conductors cannot be discarded before inductance extraction. This is because K does not shield the effect of the magnetic field completely. Adaptive window sizing [39] and hierarchical shielding [40] are proposed to address this issue. Adaptive window sizing includes all conductors with a specific shielding level m (with m − 1 shields between the aggressor and victim). Hierarchical shielding extends the previous idea by introducing adaptive meshing of included conductors. Fine meshes are used for conductors in level 0 and 1, whereas less fine meshes define conductors in higher levels. An example illustrates the accuracy of windowed partial inductance. Hierarchical shielding with m = 2 is used on the four conductor problem (Figure 3.8). Partial inductance matrices are generated for all aggressors and victims in the defined window..  . L123. .  l11 l12 l13    =  l21 l22 l23  L1234 =    l31 l32 l33. l11 l21 l31 l41. l12 l22 l32 l42. l13 l23 l33 l43. l14 l24 l34 l44.     l22 l23 l24    L234 =   l32 l33 l34    l42 l43 l44. (3.7). These matrices are individually inverted to form partial reluctance sub matrices. An extraction window with three conductors and conductor 4 as the aggressor, for example, has the form  k22 −k23 −k24   =  −k32 k33 −k34  −k42 −k43 k44 . K234. (3.8). where all off-diagonal elements (k23 , k42 , et cetera) are positive quantities. A nconductor problem results in a n × n matrix, and the K sub matrices therefore need.

(41) 27. CHAPTER 3. INDUCTANCE EXTRACTION. to be appropriately zero-padded before assembling the complete partial reluctance matrix (3.9).  K234.   =  . 0 0 0 0 0 k22 −k23 −k24 0 −k32 k33 −k34 0 −k42 −k43 k44.      . (3.9). A single partial reluctance matrix is created by inserting all aggressor partial self reluctance (kii ). The smallest, non-zero value for off-diagonal elements are selected to ensure a symmetric and stable partial reluctance matrix (3.10) [41]..  Kc.   =   .  k11 −min(k12 ) −min(k13 ) −min(k14 )  −min(k21 ) k22 −min(k23 ) −min(k24 )   −min(k31 ) −min(k32 ) k33 −min(k34 )   −min(k41 ) −min(k42 ) −min(k43 ) k44. (3.10). The combined partial K matrix of the four conductors is now    Kc =   . 162.500 −62.970 −29.580 −18.250. −62.970 187.470 −56.930 −29.250. −29.580 −56.930 192.780 −63.390. −18.250 −29.250 −63.390 174.230.     × 109 H −1  . and the inverted matrix results in a partial inductance matrix that approximates the magnetic interaction for the complete interconnect system.    Lc =   . 8.986 4.645 3.767 3.091. 4.645 8.825 4.505 3.607. 3.767 4.505 8.489 4.239. 3.091 3.607 4.239 8.211.     × 10−12 H  . The answer obtained is very similar to the L matrix above. All deviations are less than 11% (compared to 50% for m = 1). This example is too small to illustrate the effect of additional shielding levels, however, keeping in mind that K exhibit strong locality properties, by adding additional shielding levels the error obtained with windowed partial.

(42) CHAPTER 3. INDUCTANCE EXTRACTION. 28. inductance will be reduced.. Chapter review In this chapter the importance of accurate inductance extraction was highlighted by introducing the reader to previous findings in this research field. It was found that 3D numerical simulations are required to simulate structures where the length-to-width ratio are small and where discontinuities in layout structures occur. Additionally, an improved cake slicing method is presented to provide for adaptive meshes and more accurately defined meshed segments. Thus far inductance had only been a concern with small structures with which 3D simulation software could easily cope. Inductance extraction using the PEEC formulation is presented whereby long inter-gate connections can be investigated. An efficient inductance windowing formulation is also presented, whereby the locality of the inverse partial inductance matrix is illustrated..

(43) Chapter 4 Capacitance extraction Research into the transfer of SFQ pulses along transmission lines [42, 43] initiated the study of capacitive effects on signal propagation. Capacitance modelling of interconnect structures is required to determine signal attenuation through dielectric losses, pulse propagation along, and characteristic impedance of, transmission lines.. 4.1. Introduction to capacitance. Capacitance, C, between two parallel plates is a measure of the accumulated charge, Q, on each plate per volt potential difference, Φa − Φb , between them and is mathematically expressed as C=. Q Φa − Φb. (4.1). For ideal parallel plates the total capacitance is a function of overlap area (A) and distance between the plates (d) 0 r A (4.2) d where 0 is the permittivity of free space and r the relative permittivity of the dielectric between the plates. For multi-conductor geometries, capacitance consists of overlap, lateral, fringe and self capacitance. Overlap capacitance CA is due to overlap of structures in different planes, lateral capacitance CL between conductors in the same plane, and fringe capacitance CF between non-overlapping structures in different planes. Self capacitance CS is usually very C=. 29.

(44) 30. CHAPTER 4. CAPACITANCE EXTRACTION. small and is attributed to electric fields that form and terminate on the same conductor. The total capacitance of a conductor is CT = CS + CM. (4.3). where CM = CA + CL + CF . The matrix representation for a three-conductor system is  c11 c12 c13   C =  c21 c22 c23  c31 c32 c33 . (4.4). c11 is the total capacitance of conductor 1 and consists CS + c21 + c31 , where c21 and c31 are the mutual capacitance between conductors 1 and 2, and 1 and 3 respectively. The potential of each conductor can be calculated using the superposition integral for surface charge density. Z Φ(r) =. σ(r0) surf aces. 1 da0 4π0 k r − r0 k. (4.5). Φ(r) is the known conductor surface potential, k r − r0 k the Euclidean distance and σ(r0) the charge density to be solved. Throughout this chapter an r of 5.45 is assumed for SiO2 . This is higher than that of bulk SiO2 (r = 3.9) and is an indication of oxygen depletion during sputter deposition of IC fabrication [44]. From Hypres’s design rules a nominal r of 4.7 is calculated, and may vary between 3.4 and 6.2 due to process variations. 5.45 is within variation bounds.. 4.2. Capacitance calculation techniques. The parallel plate formulation is easy to implement but constantly underestimates capacitance by ignoring the contribution of electric fringe fields. Several 2D capacitance formulations have been proposed to accurately estimate the capacitance of a single conductor over a ground plane (GP). These analytic formulas, except for Chang’s [45], were derived from curve-fitted numerical simulation data [46, 47, 48, 49, 50]. Chang’s capacitance formula was derived using approximate conformal mapping techniques and is claimed to be accurate to within 1% for metal line widths not exceeding the dielectric thickness. As a result, Chang’s equations are used as datum to compare the accuracy of the other formulas. Figure 4.1(b) illustrates deviation from Chang’s formula for realistic layout line.

(45) 31. CHAPTER 4. CAPACITANCE EXTRACTION. widths, line thickness of 0.3µm and a dielectric thickness of 0.485µm. It must be noted that capacitance in VLSI layouts cannot be approximated by a simple parallel plate capacitor. True capacitance is always higher and narrow line capacitance is poorly estimated.. Per unit capacitance [C/pF/um]. 200. Deviation from Chang’s analytical formulation [%]. 250. Delorme. Elmasry. 150 Sakurai. Chang. 100 Yuan 50. 0. Parallel plate. 0. 5. 10 Width of microstrip [um]. 15. 20. (a) Length-specific capacitance versus width. 20. Delorme Sakurai. 0. −20. v.d. Meijs Elmasry. −40. Yuan Parallel plate. −60. Average deviation from Chang 0.46%Van der Meijs 6.30%Sakurai −6.40%Elmasry 7.90%Delorme −18.99%Yuan −22.55%Parallel plate. −80 2. 4. 6. 8 10 12 14 Width of microstrip [um]. 16. 18. 20. (b) Percentage error versus microstrip width with Chang’s formulation as datum. Figure 4.1: 2D line-to-ground capacitance comparison. Although these 2D formulations allow for fringe capacitance, the effect of multiple conductors on total capacitance is not addressed. Delorme [49] and Wong [51] make an effort to analytically describe lateral capacitance, but their formulas are based on curve fitting capacitance obtained from sub-micron structures, structures smaller than those currently used in superconducting ICs. No reference are made to how high the dielectric-to-air plane is placed as this also have an influence on capacitance calculations. Chang assumes an infinite uniform dielectric layer. Table 4.1 illustrates the relative error made with this assumption. A dielectric-toair plane is placed at 1.985µm above the GP. For direct comparison to Chang’s formulation, end-of-line fringing was removed with appropriate border extensions (§4.4.2). Answers are obtained for a conductor with dimensions 30 × 5µm using FastCap [52]. First of all it is noted that FastCap provides excellent comparative answers to that obtained from Chang’s formulation, and is therefore considered to be accurate enough to extract capacitance in a 3D environment. It is furthermore apparent that Chang’s formulation is inaccurate for conductors close to the dielectric-to-air interface (layer M3)..

(46) 32. CHAPTER 4. CAPACITANCE EXTRACTION Table 4.1: The effect of finite dielectric layers on capacitance calculations. Layer. Layer thickness [µm]. Height above GP [µm]. M1 M2 M3. 0.100 0.300 0.600. 0.135 0.485 1.385. 4.3. FastCap deviation from Chang - Diel. plane at 1.985µm [%] 1.890 4.680 14.124. FastCap deviation from Chang - Diel. plane at 200µm [%] 1.502 1.530 0.756. 3D capacitance extraction. The integral formulation for surface charge density (4.5) requires structures to be segmented into evenly sized panels. This section addresses methods to reduce the amount of panels required by FastCap to produce sufficient accurate answers, as well as methods to extract capacitance with the use of windows.. 4.3.1. Structure segmentation and 3D capacitance models. Panels are divided in the X-Y Cartesian plane where after the edge panels are extrapolated in the Z direction. The improved cake slice method (§3.2.1) is used to sufficiently segmentize the structure. The resultant panel segments are divided in quarters for finer discretisation. FastCap input requirements are more leniently specified than that of FastHenry and quadrilaterals and triangles are allowed.. 4.3.2. Non-uniform discretisation. Charge density tends to be higher near conductor edges. Non-uniform discretisation allows for sufficient capture of edge charges and deliver more accurate answers for less panels than obtainable from normal discretisation (Figure 4.2). The effect of non-uniform discretisation on capacitance calculation is illustrated in Figure 4.3. A 30 × 5µm conductor above a segmented GP is simulated using FastCap, with subsequent increase in the number of panels. From numerical simulations it is known that, for effective capture of charge distribution, the non-uniform boundary should be between 10% and 13% of the internal segments’ width. With a 10% border, the capacitance stabilizes at 57.36 fF with the use of 14 000 panels. An uniform mesh requires 19 000 panels to only come within 1% of the true value, and does not even completely converge with 75 000.

(47) 33. CHAPTER 4. CAPACITANCE EXTRACTION. Figure 4.2: Non-uniform discretisation of a structure. panels. −14. 7. x 10. 6.8 6.6. Capacitance [C]. 6.4 6.2. Chang’s equation Non−uniform. 6 5.8 5.6 5.4 5.2 4.1 10. Uniform. 4.3. 10. 4.5. 10 log(FastCap panels). 4.7. 10. 4.9. 10. Figure 4.3: Uniform and non-uniform discretisation on panel requirement.

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