4.2.1 input independent bootstrapping
eq 4.3 The input voltage dependency ofVgs can be reduced by using a higher Vgate. If for example Yin (=Vs) varies between 0.6V and 1.2V, with Vg= 1.8V, this means the relative change ofVgs (b.VgsNgsaverage) is 2/3.
R I . C'l. V _.1 Vgs V _ 1.2-0.6 2
e atIve flange gs - -j- - ) gs - 1
\ Vgs -(1.2+0.6) 3 2
Making Vgate 3/2 times as large (2.7V) decreases this relative change ofVgs to 1/3 R I . C'l. V .1 Vgs 2.1-1.5 1
e atIve flange gs
=
-j- - )=
13"
\ Vgs -(2.1 + 1.5) 2
eq 4.4
However, there are limitations to how high Vgate can be made without damaging the switch. In [6]
chapter 4 it is suggested that in order to have reliable switch with reasonable lifetime, Vgs should not exceed Vdd •
Figure 4.2 illustrates the input independent bootstrapping. The higher gate voltage is represented by the extra voltage source Vx • There is no need to use an extra supply voltage, the higher Vgate can be made from Vddwith a special circuit.
= vsource =
+ V
Signal
Figure4.2input independent bootstrapping
4.2.2 input dependent bootstrapping
Input voltage dependency of Ron can theoretically be eliminated using input voltage dependent bootstrapping. When the switch must be on, a constant dc voltage source is connected betweenYin
(= Vs) and Vg which causes Vgs and thus Ron to also be constant. This connecting is done with MOS switches, so one is reducing the problems of a non ideal switch using even more non ideal switches.
This approach is illustrated by figure 4.3.
In order to create this voltage source Vxthat is connected between gate and source when the switch should be on, another special circuit is needed. Such a circuit is described in [6]. This circuit will be further explained in chapter 5 of this thesis.
"gate
=
"in + "x= "
.ouree=
+ "signal
Figure4.3input dependent bootstrapping
4.2.3 transmission gate
A transmission gate is depicted in figure 4.4. A transmission gate does not require additional voltage sources, which makes it attractive. When the switch is "on", the gate of the NMOS is connected to Vdd , and the gate of the PMOS to ground. When the switch is "off', the gate of the NMOS will be connected to ground, and the gate of the PMOS to Vdd • In "on" state, ideally the voltage across the switch (Vds)would be zero. For a real switch this is not the case, however Vdswill be small and Vd ~ V s. As the input voltage increases, V gs of the NMOS decreases due to the fixed gate voltage, thus increasing Ron N. At the same time, Vsg of the PMOS increases, therefore decreasingRonP.This is illustrated in figure 4.5.
As stated before,V ds will be small andV ds2even more so. Inthe approximation in equation 4.2, V ds2
is neglected. When one calculates the resistance of a NMOS and PMOS switch in parallel, using this approximation, one finds the resistance will be constant when !-LnWn= !-LpWp. This is illustrated in figure 4.5. There is an "asymmetry" in figure 4.5, the point where RonN= RonP lies above 0.5 Vdd.
This is caused by a difference in threshold voltages.
By using the exact form of equation 4.2, substituting Vds
=
Ron I, and subsequently solvingRon from this expression, one getsR~~.!.I-l+.ir-l+[ -21-]2)
I\ ~ ~C~~(V,,-V,)
J eq4.5+ "signal
Figure 4.4transmission gate
The result of connecting a NMOS and PMOS with this Ron characteristic in parallel is given in figure 4.6. This demonstrates Ron of a transmission gate will not be constant as input voltage changes.
RonI,SY;using aproximation
Figure 4.5Ron oftransmission gate using approximation
RonI,SY;using exact equation
;"
Figure4.6Ron oftransmission gate using exact equation
4.3 simulations
In order to investigate which switch techniques are applicable to the flexible track & hold, simulations were performed.Insection 4.3.1 it is examined howRon changes as function of the input voltage. Section 4.3.2 gives performance of a basic track & hold using the various switch techniques.
4.3.1 Ron vs input voltage
Figure 4.7 shows the circuit used for this test. The switch is in it's ON position, and the input voltage is changed from it's minimum of Vern - Va
=
0.9 - 0.3=
0.6 V to Vern+Va=
D.9 + 0.3 = 1.2 V. By measuring the voltage across the switch and dividing it by the current, the switch's Ron is found. Both 8 - and 12 bit cases are tested, using the switch widths as indicated in table 3.9.Switch (ON)
Figure 4.7 circuit for testingRon vs input voltage
Figures 4.8 and 4.9 show the simulation results. These figures shows that input dependent bootstrapping results in the most constant Ron. Due to the bulk effect, Ron still varies a little, even though Vgs is kept constant. But this variation is much smaller than with the other two approaches.
The relative change of the resistance values was calculated according to equation 4.6. Values found with this equation are in tables 4.1 and 4.2.
. L1Ron
Relatzve Change Ron
=-/--)
eq 4.6\Ron
input independent input dependent transmission gate bootstrapping bootstrapping
AverageRon 369.9 361.9 328.6
Relative ChangeRon 0.4300 0.0595 0.4417
Table4.1Ron vs V;n results for8bit
input independent input dependent transmission gate bootstrapping bootstrapping
AverageRon 8.563 8.374 7.799
IRelative ChangeRon 0.4317 0.0578 0.4039
Table4.2Ron vs Vin results for12bit
250 450
400
300 ;'
; ' ,/
//""
,./
"
"
./.,r'''/
; '
-0.25 -0.2 -0.15 -0.1 -0.05 0 Vi
Figure4.8RonVS Vinfor8bit
0.05 0.1 0.15 0.2 0.25
111 -.---.---.---.---.---,----,---,-r=======>1
10
9
.~.-'
_.-
--5'---,,-J:-:---,-'---'---'---'---'---'---'---'---'---':~---'
-0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25
Vi
Figure4.9Ron vs Vinfor12bit
4.3.2 performance with various switches
In order to quantify the influence of the non constantRonon the achievable accuracy, a basic track &
hold circuit was simulated. This was done in both 8 and 12 bit configuration (capacitor sizes, switch widths, sampling speeds). The circuit used is illustrated by figure 4.10. Like the final circuit will be, this circuit is in differential mode. Advantage of using a differential circuit is the reduction of even order harmonics. Input sources Vin+and Vin- are sine waves with amplitudeVa and frequency!J.I fsand Y2 fs•The accuracy is calculated by observing the frequency spectrum of VOU!'From this spectrum the SDR is calculated.
+ ~v+
out+
Figure 4.10 basic differential track& hold circuit
input independent 67.72 dB 10.96 62.95 dB 10.16
8 bit input dependent 73.07 dB 11.85
64.82~
transmission gate 36.47 dB 5.77 36.65 dB 5.80
input independent 75.36 dB 12.23 70.09 dB
I ~35
112
bit input dependent 82.52 dB 13.42 76.54 dB 12.42transmission gate 52.59 dB 8.44 51.40 dB 8.25
Table4.3 simulation results
4.4 conclusion
Table 4.3 shows that the input dependent bootstrapping switch is the only one which reaches the required 12 bit accuracy. Choosing this solution has the penalty that every bootstrapped switch needs its own bootstrapping circuit.
The transmission gate, which would not require any additional circuitry, can be further optimized by tuning the ratioWPMOS!WNMOS to reach a higher accuracy. This procedure is described in [7]. But then, his conclusion is: "However, the optimum sizing of the transistors of the CMOS switch can suppress the third harmonic to a very low level as seen in the plot (d). Unfortunately this minimum is quite narrow and its location depends on the parameter variations as well as the temperature and the supply voltage".
The input dependent bootstrapping switch performance is close to that of the input independent bootstrapping circuit. But it does not have the potential to reach 12 bit accuracy. So it is an obvious choice to go for the input independent bootstrapping switch.
5 Realization
Inthe previous chapters track & hold architectures were discussed, values for elements of the basic track & hold circuit were determined, and techniques to create linear switches were investigated.
This chapter will describe the bootstrap circuit that is used to implement a linear switch, the opamp which is used in the circuit, and the realization of a flip around track & hold.
So far, all circuits were given in single ended form. This was done to illustrate their operation more clearly. However, the realization of the track & hold will be in fully differential form. This reduces even order distortion components.