MASTER
Design of flexible track & hold
van Zon, R.
Award date:
2005
Link to publication
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TU/e
Design of a Flexible Track & Hold
R. van Zon
March 29, 2005
Master of Science thesis
Proj ect period: April 2004 - March 2005
Department of Electrical Engineering
Capacity group: Information and Communication Systems Chair: Mixed-signal Microelectronics
Supervisors:
A. Zanikopoulos M.Sc.
Dr.Jr. 1.A.Hegt
Prof. Dr. Jr. A.H.M. van Roermund
The Department of Electrical Engineering of the Eindhoven University of Technology accepts no responsibility for the contents ofM.Sc. thesis or practical training reports
Abstract
In this master thesis a flexible track& hold circuit is presented which was designed for usage in a flexible AID converter. This flexible AID converter is part of the "STW Mixed - signal SoC platform" project.
Flexibility means that speed and accuracy specifications are not fixed, but can be varied over a range. This range was chosen to be:
accuracy
sampling speed
=:=40=M==H=Z===I=:2=0=M==H=Z==~...L~_~_0_M_H_z3-MH-z--bffi-z--
First several track & hold architectures found in literature were examined. Some architectures are more focused on speed, others more on accuracy. An architecture was selected which can cover the entire range of speed an accuracy. This specific architecture is commonly used and is suitable for implementation in CMOS technology.
Next step was researching the basic components of a track & hold circuit. A flexibility theory was developed, which gives a mathematical relation between speed I accuracy demands and dimensions of circuit elements. The theory was tested and proved correct by simulation.
A special subject of interest in track& hold circuits are switches. Various techniques for optimizing switches were examined. A technique which proved to be usable over the entire range was chosen.
Subsequently circuits were designed to implement the chosen solutions in the UMC 0.18 ~m
process. These circuits are the optimized switch, and a fully differential opamp which is needed in the selected track & hold architecture. Finally, a track & hold made up from the several sub circuits was simulated.
Contents
Abstract. 2
1 Introduction 4
1.1 project background 4
1.2 project definition 4
1.3 structure of thesis 4
2 Track& Hold definitions and architectures 5
2.1 track& hold definitions 5
2.1.1 symbol definitions 5
2.1.2 system defini tion 5
2.2 track& hold architectures 8
2.2.1 open loop track& hold 8
2.2.1.1 standard open loop 8
2.2.1.2 alternative open loop 9
2.2.1.3 Miller open loop 9
2.2.2 closed loop track & hold 10
2.2.2.1 traditional closed loop 10
2.2.2.2 switched capacitor closed loop ll
2.2.3 architecture of choice 12
3 Flexibility 13
3.1 introduction 13
3.2 capacitor size versus accuracy 13
3.3 resistor size versus accuracy 15
3.3.1 step input settling 15
3.3.2 sine input settling 17
3.3.3 resistor size overview 21
3.4 simulation 22
4 Switches 24
4.1 introduction 24
4.2 switch techniques 25
4.2.1 input independent bootstrapping 25
4.2.2 input dependent bootstrapping 25
4.2.3 transmission gate 26
4.3 simulations 28
4.3.1 Ron vs input voltage 28
4.3.2 perfonnance with various switches 30
4.4 conclusion 31
5 Realization 32
5.1 bootstrap circuit. 32
5.2 opamp 35
5.3 flip around track& hold 36
5.4 opamp design 40
6 Conclusions 41
7. Recommendations 42
7.1 brute force approach 42
7.2 flexible flip around 42
References 43
Appendix A: Symbol definitions 45
1 Introduction
1. 1 project background
In 100 years of electrical engineering, two distinctive technologies have evolved to implement systems. These are analogue and digital technologies. As digital technology is more robust, easier to design and improving IC technology allows to create larger and larger systems, the trend is in favor of digital technology. However, naturally occurring signals and human senses are more of the analogue kind. So there will always remain a need for some analogue circuitry. In order to bridge the gap between the analogue and digital domain, analogue I digital - and digital I analogue converters were developed.
A popular platform for implementing digital systems are Field Programmable Gate Arrays (FPGAs).
Like microprocessors, these devices are programmable. Big difference is that algorithms in FPGAs are implemented in hardware, which is much faster. In practical applications FPGAs are often surrounded by AID andD/A converters, as they frequently take input from the analogue world for digital processing and I or deliver results of digital processing to the analogue world. Target of the STW Mixed - signal SoC platform project is to integrate converters and FPGA on a single chip.
There is a wide range of converters, each having a different speed I accuracy performance. When examining converters, one encounters a speed I accuracy trade off. More accurate devices will be slower, and faster devices will be less accurate. As it is unfeasible to implement a wide range of converters in the FPGA, of which only a few will be used, it was chosen to develop flexible converters. When programming the FPGA, the user can select the converter's required accuracy I speed.
1.2 project definition
In an AID converter two distinctive actions take place, these are sampling and quantization.
Sampling reduces a time continuous signal to certain points in time (samples). Quantization measures the amplitude of a signal and translates this to the closest match from a set of sizes.
Sampling is done by a flexible track & hold circuit. Quantization will be done by a pipeline of blocks which each add 1 bit to the accuracy.
Target of this master thesis project is the design of a track & hold circuit for usage in the flexible AID converter.
1.3 structure of thesis
This master thesis is structured as follows:
In chapter 2 architectures of existing (non flexible) track & hold circuits are analyzed. Furthermore there is a list of definitions and concepts that are used throughout this thesis.
Chapter 3 develops theory which relates values of basic track & hold circuit elements to speed and accuracy.
Switches are basic elements in track & hold circuits. Chapter 4 investigates how to implement switches in CMOS technology.
Chapter 5 describes realizations of an opamp, a bootstrapping circuit and a complete flip around track& hold circuit which uses the mentioned parts.
Conclusions and recommendations are given in chapter 6.
2 Track & Hold definitions and architectures 2.1 track
&hold definitions
2.1.1 symbol definitions
Throughout this work numerous symbols and definitions are used. A table introducing all symbols can be found in appendix A
2.1.2 system definition
As indicated in the introduction, the track and hold described in this thesis is a part of a flexible AID converter, as illustrated in figure 2.1. The quantizer is a pipeline with a flexible number of blocks.
The converter's accuracy depends on the number of blocks used.
In an ideal ideal converter, the intermediate signal vx would be an ideally sampled version of input signal Vi. Signal Vx is subsequently quantized by an ideal quantizer. As the quantizer maps the continuous amplitude of the sampled input vx onto a limited set of values, it introduces quantization errors. Under certain assumptions these errors can be represented as a white noise source at the converter's output with power:
- q -2 1 2 -2n 2 1
P NQuant-12-"3va2 eq .
However, due to non idealities of the track & hold, intermediate signalVx will represent input signal
Vi with only a limited accuracy. Errors introduced by the track & hold can be seen as noise sources at the track & hold's output. As the quantizer has a gain of 1, these noise sources can be moved to the converter's output.
AID converter
(
Vi
~l
VI
H ~"""'''-.(
V" 0
... ~ ... ..
1\
.... .... ....
Track & Hold Quantizer
~
~/
\
I II I II
\
~. " " " ... " .... ,
Figure2.1 Track& Hold as part ofAID converter
Signal Desired accuracy fbit} Achieved accuracy fbit}
Vi 00 00
Vx 00 n+x
Vo n <n
~
I
Table2.1 accuracies at various points in the AID converter
Noise sources introduced by the track& hold are thermal noise and distortion.
Thermal noise
Thermal noise is generated in the input resistor and the on resistance of the track & hold switch.
This power will be "filtered" by the track and hold circuit (see paragraph 3.2). The resulting power will be:
PNtherm=ckT eq 2.2
where k is Boltzmann's constant, T is absolute temperature and C is the hold capacitance.
Distortion
eq2.3 Due to non linearity of circuit elements, higher order harmonics of the input signal will be generated, which cause distortion. The distortion power is a sum of the powers of the distorting components:
( ) 2 ()2
" , , 1 ~ 1 2 " Vm
PD=~P=~ -y2V =-V~-
m;t! m m;t! 2 m 2 am;t! Va
eq2.4 whereVa is the amplitude of the first harmonic, Pm is the power of the m'th harmonic and Vmis the amplitude of the m'th harmonic.
The signal power, the power of the first harmonic, is
(
1
)2
12
Ps
= "i
fiva="2
vaeq 2.5 1
1 1 1
- - - + +--
SN quant R SN therm R SDR
By relating the signal power to the noise powers found at the converter's output, the signal to noise and distortion ratio (SNDR) can be calculated. This is a measure for accuracy and can be expressed in a number of bits.
SNDR= Ps
P Nquant
+
P Ntherm+
P DEquation 2.5 reveals that the output accuracy does not only depend on quantization noise, as would be the case in an ideal converter, but also depends on the noise produced by the track & hold. The accuracy of the output will be less than the desired accuracy n of an ideal converter. In order to approximate an ideal converter (with only quantization noise), additional noise sources, such as thermal noise and distortion, should be smaller than quantization noise. This means quantizer's input accuracy should be higher than n.
Let's assume v" approximates Vi with an accuracy of n+x bits (table 2.1). Here x is the "extra accuracy", the difference between accuracy of v" (n+x) and the desired converter accuracy (n). Let's investigate what is the achievable output accuracy as function of "extra accuracy" x.
eq2.6
! !
10(SNDRdB,"P") 1O(6.02(n+x)+ 1.76)
SNDR,nput=10 =10 eq 2.7
eq 2.9 eq2.8
\ T0 6.02x
10
+
1...!...(6.02n+ 1.76)
1010 1
SNDRoutput
=
1+
1SNDRinput SNRdesired
1
...!...(6.02n+ 1.76)
. 1 1010
SNDRbltSoutput=-60 10Iog--\---
. 2 T06.02x
10
+
1SNDRbitsoutpulw"extra accuracy x"
13
12 .::::::::::::::::::::::::::::::::::::::::::::::::::::': ; :::::::::::::::::::::::::: .
11.:::::::::::::::::::::::::::::::::::::::::::::::::::::
+ :::::::::::::::::::::::::::::::.:::.::.: .
10 .:::::::::::::::::::::::::::::::::::::::::::::::::::::: :::::::::::::::::: ..
9 .:::::::::::::::::::::::::::::::::::::::::::::::::::: ; ::::::::::::::::::::::::::...•...••...
8 .::::::::::::::::::::::::::::::::::::::::::::::::::::: ; ::::::::::::::::::::::::::::: ..
70~---::-0.'::-5---'---'--:-'-1.5=---:---:2:':.5,---~3
"extra accuracy" x
Figure2.2output accuracy vs extra accuracy at input/or various desired accuracies
Figure 2.2 illustrates equation 2.9 for various values of desired converter accuracy n. It clearly shows, as "extra accuracy" x increases, the output will more and more approximate the desired accuracy n. This is as expected, because as x increases, the converter more and more approximates an ideal converter.
The dotted lines indicate that an "extra accuracy" x= 1.375 bits results in an output accuracy which is 0.1 bit less than the desired accuracy.
2.2 track & hold architectures
A wide range of track &hold architectures have emerged over the years. They are commonly split up into two groups:
1. open loop: track & hold system contains no "global" feedback loop.
2. closed loop: track &hold system contains a "global" feedback loop.
They will be discussed in detail in the next two paragraphs.
All track & hold architectures contain switches. For switches MOS transistors will be used.
Difficulties related to the MOS transistor switches are charge injection and clock feedthrough.
When a MOS transistor switches on, a channel is formed from source to drain. When it switches off, the channel disappears. The charges by which the channel was formed, move out of the transistor and some are "injected" on CH, causing an error voltage. This effect is called charge injection. Due to capacitive coupling between gate source and gate drain, clock transitions on the gate will also be seen at source and drain. A fraction of the clock transition will reach CH• This effect is called clock feedthrough. When using multiple switches, controlled in a specific order, it can occur the feedthrough gets "rectified". This can cause dc offset errors.
2.2.1 open loop track
&hold
2.2.1.1 standard open loop
Figure 2.3 illustrates the standard open loop architecture. In fact it is the basic track &hold circuit (S and CH) to which input and output buffers are added. The basic track & hold circuit operates as follows: While tracking, switch S is on, and the voltage on CHfollows Vi. At the moment switch S turns off, the last value ofVi remains on CH• During the hold period, as there is no path for charge displacement, the voltage onCHwill remain constant.
The necessity of buffers Bland B2 depends on the application. If the input signal source possesses a large output impedance, this will gravely limit the speed with which CH is charged. Using input buffer B1 resolves the effect of the input source's output impedance. The output buffer B2 prevents loading of CH. If CH is loaded with a "low" impedance, it will discharge trough this impedance, which leads to changes in the held voltage on CH •
Figure2.3standard open loop track& hold
Although an open loop architecture does not contain a "global" feedback loop, buffer Bland B2 can contain "local" feedback loops. This would be the case when implementing buffers Bland B2 using an opamp in unity gain configuration. The alternative solution for implementing the buffers is by using some sort of "source follower". Such a circuit is described in [1]. A limitation of source followers is their linearity. They do not reach the required 12+x bit linearity, where x stands for the
"extra accuracy" as described in 2.1.2. When using an opamp, the speed of the track &hold will be limited by the unity gain bandwidth of the opamp.
2.2.1.2 alternative open loop
An alternative open loop configuration, which is described in [15], is shown in figure 2.4. The advantage of this configuration is that it offers bottom plate sampling. When tracking, both switches S1 and S2 are on, making the voltage across CH equal to the input voltage. Inhold mode, S1 and S2 are off and S3 is on. Without S3, the voltage held on CH would be floating. Switch S3 refers the held value to Vdd. Note that this configuration causes an "inversion" of the input signal. If for instance during tracking the input voltage is v;=vem+Va where vem=0.5 vdd ,the output during hold will be vo=vdd-v;=vem-va .So componentVagets a negative sign.
The principle of bottom plate sampling works as follows ([10]):
At the moment the configuration changes from track to hold mode, first S2 and then S1 tum off, and S3 turns on. As S2 turns off, it will inject charge on CH. Because it switches a constant voltage (ground), this will be a constant error. Switch S I switches a non constant voltage (Vi) and would produce an input signal dependent error, which results in distortion. But as S2 is already off at the moment S1 is switched off, the current path is blocked so no charges will flow to CH.
Figure2.4alternative open loop track& hold
2.2.1.3 Miller open loop
A special version of the open loop track & hold is the Miller track & hold, as described in [2].
Figure 2.5a shows this track & hold. Itreduces effects of charge injection and clock feedthrough by using a large Miller capacitor during hold mode. In track mode it uses a smaller capacitor, otherwise the achievable sampling speed would be reduced, as charging a big capacitor takes longer.
In track mode both S1 and S2 are closed. The opamp is in voltage follower mode, so the output follows the grounded positive input. Bottom plates of C1 and C2 will both be at ground so the circuit behaves like the equivalent circuit shown in 2.5b.
Inhold mode both switches are open. This is illustrated in figure 2.5c. As no current will flow into the opamp's inverting input, C1 will have no capacitive effect and can be ignored. In this configuration the amplifier and C2 are connected in parallel. Due to the Miller effect, seen from the node marked Vo, C2 will behave like a capacitor of (1 +A)C2. When transferring from track to hold mode, first S2 tuns off. As subsequently S1 switches off, it injects its charge on this big Miller capacitance.
---./:
v
Sl-:::r::::---'--:::r::::"""'--V
1 0
C2
a
v.1
:::r:::: :::r::::
v0bnr-~
c
(1 +A) C2
eq2.10
Figure2.5a) Miller track& hold b) in track mode c) in hold mode
2.2.2 closed loop track & hold
2.2.2.1 traditional closed loop
The traditional closed loop configuration is shown in figure 2.6. The two amplifiers can be two stages of a single amplifier, as illustrated in [3] figure 7.21. As the switch is on, the circuit will have a transfer function of:
H(s)= C1 s-+l
G
mwhere C is the hold capacitor CH. As portrayed in paragraph 3.2, the size of the hold capacitor is related to the desired accuracy, thus can not be chosen arbitrarily small. The bandwidth of this circuit is:
G
mwcl=c eq 2.11
Due to the relative large C, the achievable bandwidth will be small. This is the major drawback of this circuit.
An advantage of the traditional closed loop is that it uses only one switch. As the switch is closed, the voltage at the negative input of Ao will be close to zero due to the feedback. Thus the voltage across the switch is independent of the input voltage, which avoids the distortion problems caused by switches carrying changing voltages.
vo
Figure 2.6 traditional closed loop track& hold
2.2.2.2 switched capacitor closed loop
s3
r
a b slFigure2.7switched capacitor closed loop track& hold circuits a) charge redistribution b) flip aroundc)combination ofprevious two
Another class of closed loop track &hold circuits are the switched capacitor track & hold circuits.
Three variations on this principle are illustrated by figure 2.7. What they have in common is the usage of multiple switches. In the figure the switches are drawn in the tracking position. When the switches are in the holding position, the circuits form non inverting amplifiers with feedback factor
~.The closed loop gain and bandwidth will be:
Adc 1 Acl= 1
+
13Adc
RO13 eq 2.12
eq 2.13 Configurations a and c can provide gain to the signal. This gain is a different gain than the closed loop gain Act, and is based on charge redistribution occurring as the circuit changes from track to hold mode. The various gains and feedback factors are listed in table 2.2.
cOllfiguratioll gaill feedback factor
figure 2.6a C H CF
CF CH+CF
figure 2.6b 1 1
figure 2.6c C CF
1+~CF CH+CF
Table2.2gain and feedback factor for various closed loop switched capacitor configurations
Advantage of the switched capacitor track & hold is that its bandwidth is not dictated by the hold capacitor (equation 2.13). As the hold capacitor is not part of the opamp, the opamp's pole frequency(t).3dB can be high. Together with a large gainAleit will provide higher bandwidth than the traditional closed loop configuration.
This will be illustrated with an example: using a folded cascode opamp will give
eq 2.14 eq 2.15
eq 2.16
When comparing equation 2.16 and 2.11 one must realize thatCo« CHas one can design an opamp to have a small output capacitor, but the hold capacitor can not be reduced because it is related to accuracy.
Disadvantage of the switched capacitor configurations is that the changing voltage over input switch 81 will cause distortion. However, this can be diminished by using "bottom plate sampling". Switch 82, which during tracking provides a virtual ground at the "bottom plate" (the right plate ofCH),will open before S1 does. By doing so, it blocks the path of the charges that are inj ected by S1 as it turns off. Switch S2 itself will inject some charges when switching off, but as the voltage switched by S2 is constant, this will only cause an offset type of error. More about switched capacitor track & hold circuits can be found in [4] paragraph 2.3.2.
In [4] figures 7, 8 and 9, during tracking, S2 connects the inverting input of the opamp to ground, instead of to the opamp's output as illustrated in 2.7. Due to the non-zero on impedance of S2, CH 82 will act as voltage divider, resulting in a voltage on the negative input. This will give large voltages on the opamp's output, as there is no feedback path. By connecting 82 between negative input and output, feedback will provide virtual ground on the inverting input, resolving the influence of the on resistance of S2.
2.2.3 architecture of choice
Due to its limited bandwidth, the traditional closed loop (figure 2.6) can be eliminated as candidate architecture for usage in the flexible track &hold.
The flexible track & hold does not have to provide gain. Regarding the unity gain bandwidth,
Wug=(1+I3Adc}w_3dB eq2.17
the conclusion is that from the switched capacitor variants, the flip around (figure 2. 7b) is favorite as it provides maximum bandwidth.
Although the Miller open loop architecture contains an opamp, this does not provide buffer functionality to the output. In figure 2.5c this is illustrated. Any load connected connected to the output will decharge the hold capacitor. Of course an output buffer can be added, but that requires an additional opamp.
Drawback of the standard open loop (figure 2.3) is that it does not offer a mechanism to reduce errors caused by the switch. As it switches the input voltage, it will cause distortion.
Two architectures that are very similar are the alternative open loop configuration (figure 2.4) and the flip around closed loop configuration (figure 2. 7b). They both provide bottom plate sampling, use 3 switches, and have an opamp in voltage follower configuration. Their bandwidths are equal.
However, there is a mayor difference. In tracking mode, let's observe the circuits that charge CH •
For the alternative open loop this is a series connection of Rons1 RonS2and CH•For the flip around this isRonSl' CHand a fraction ofRonS2,because feedback of the opamp decreases the impedance ofS2 by Adc. As Ronlimits the settling speed of the output, the flip around configuration is preferable and will be used in the flexible track & hold.
3 Flexibility
3. 1 introduction
Traditionally AID converters, and track & hold circuits used in these, are designed to meet a certain speed/accuracy demand. When designing such a circuit, a relation between speed and accuracy called "speed/accuracy trade off' is found. This relation is illustrated in [5], figure 1. Over 150 converters, designed for various speed/accuracy, were analyzed. The conclusion was that accuracy drops 1 bit when doubling the sampling frequency, meaning "minus 1 bit per octave".
Unique of the STW Flex project is that various speed/accuracy combinations are to be met by the same circuit. The rule of "minus 1bit per octave" is used as a design target. When assuming a target sampling speed of 640MHz at 8bit accuracy, this means the sampling rate will drop to 40MHz at 12 bit accuracy.
This chapter analyzes what the consequences are of sustaining the minus 1 bit per octave rule and how this relates to needed values of circuit elements.
RIn
~
V.
ITVo
v.IC'Tvo
-- -- -- --
a b
Figure 3.1 basic track &hold a) when holding b) when tracking
3.2 capacitor size versus accuracy
Figure 3.1 shows a basic track & hold circuit. During tracking phase the switch will be conducting and thus behave as a finite resistance Ron. Inthis simple model, Ron is assumed to be constant and independent ofVi. The validity of these assumptions is related to the choice of switch technique, see chapter 4. As the resistance of the input source (500) and the resistance of the switch are in series, they can be combined into one resistance. This resistance will produce thermal noise with power spectral density of
Snitherm=4k T R eq 3.1
The resistor together with the capacitor forms a low pass filter with the following transfer function
H(w)- 1 eq32
l+jwRC .
The input noise is filtered by this filter, leading to an output power spectral density of Sno therm
= I
H (w )I
2Sni thermThe output noise power can be found by integrating the output power spectral density
00
Pno therm
= (T~o
therm=
2~ !
Sno therm d w=
kfeq 3.3
eq 3.4 The thermal output noise voltage can be assumed to be Gaussian. For a Gaussian distribution we have a probability to find a noise voltage smaller than 3(jof
Pr(-3u<vno Iherm<3U}=0.9973
At the output, the maximum allowable error is equal to half a quantization step 1 2-n
vMax Error=
'2
q= Vaeq 3.5
eq 3.6
Relating maximum error to output noise power gives an expression for the required value of C.
3Uno Iherm=2-nVa
~ 3~kT
C =Tnva~
C=J...- kT22n2 eq3.7Va
Except thermal noise in the track & hold, there will also be thermal noise in the quantizer. And there are several other noise sources in both track & hold and quantizer. A design choice was to allocate a "noise budget" of 1/3 PMax Errorfor thermal noise produced in the track& hold. This gives
PMax Error=3 Pno Iherm eq 3.8
In order to reduce the output thermal noise power 3 times, C needs to grow with a factor 3. This gives the final relation between capacitor size C, accuracy n and input signal amplitudeVa
C= 2; k T22n
eq 3.9
Va
From equation 3.9 one can derive that increasing accuracy by one bit increases the capacitance by 4 eq 3.10 Table 3.1 gives the required values of C, using input signal amplitude Va = 0.3V, at various accuracies. The output noise power due to thermal noise is calculated, and based on this signal to thermal noise ratio and the number of bits represented by this SNR.
11 C PliOtileI'm SNtlwomR,m SMIII',omRbils
8 81.45 iF 50.86 nW 59.47 dB 9.586
9 325.8iF 12.72 nW 65.49 dB 10.59
10 1.303 pF 3.179 nW 71.51 dB 11.59
c---
11 5.213 pF 794.7 pW 77.53 dB 12.59 I
L12 20.85 pF 198.7 pW 83.55 dB 13.59
Table 301 Capacitance at various accuracies
These calculated values agree with the range of values presented in (4] figure 5.
It seems that the SNthermRbits are 1.59 too high. This is not the case, as all error sources will be added together. The most dominant error source should be the quantization noise that will be added in the block following the track & hold. When using the calculated values for C at the end of the AID converter one can expect an error of 0.076 bits due to thermal noise (see 2.1.2).
3.3 resistor size versus accuracy
As shown in figure 3.1 b, during tracking phase the circuit consists of an R C circuit. Equation 3.9 gives the required value of the hold capacitor.In this paragraph expressions are derived which relate the size of Ron (which corresponds to the switch's width) to speed and accuracy. This derivation is 'based on a time domain analysis. The result depends on the type of input signal that is used.
First analysis is done using a full scale step input. Even though this is not a very likely signal to encounter at the input of an AID converter, it clearly illustrates the line of thought behind this time domain analysis.
Subsequently a full scale sine input is used. This type of input signal is more realistic. According to Foumer's theory, complicated periodical signals (such as music) can be seen as compositions of sine waves. When using this type of input signal, the resulting Ron does not only depend on the required track & hold speed and accuracy, but also on the frequency of the input signal.
In tracking phase, the combination ofR and C form a low pass filter with -3 dB frequency of 1
W- 3dB
=
RC eq3.11However, this attenuation will cause a linear error and can be compensated later on in the digital domain.
3.3.1 step input settling
The track & hold circuit in tracking mode, as illustrated in figure 3.1 b, can be represented by a differential equation
1 d 1
-vi(t)=-d vo(t)+-vo(t) eq 3.12
T t T
As input signal a step input voltage from-Vato Vais used vj(t )=va(E(t)-E(-t) )=va(2E(t)-1)
The output voltage can be calculated to be v0(t)=va
(1 -2
e-~
)eq 3.13
eq 3.14 Figure 3.2 illustrates input and output signals. As time passes, the output will approach the input (which after the step is Va)asymptotically.
There are demands on both speed and accuracy with which the output should approximate the input.
The speed demand is related to the sampling frequency fs• Half of the sample time Ts (=1/[.), the circuit is in track mode, and the other half in hold mode. The required accuracy should be reached within one track time, so when t = Y2 Ts•
The precision with which the output needs to approach the input depends on the required accuracy n. Quantization means the full scale range from -Va to Va gets split up in 2n regions. The frontiers between these regions are the "decision levels". In order to approximate the input with sufficient accuracy, the output needs to end up in the most upper region. So at t = Y2 Ts the output needs to have crossed the most upper decision level, which is Va - q.
Combining these two demands gives equation 3.15.
v,(~
T,)=vJ1-2e -t~ )=v,(
1-21-,) eq3.150.2
Responce on step input 0.4
f - - - = : = = = - - - -,~---_.,.__
.----_.,
..".,.-'"
~ /""....
~o 0 /"
;-- /,/
-0.2 / /
-0.40~----::0':-.2---:-0.":-4---='0.-=-6---:'0.-=-8----'----J.'.2=--'
x10.10
• • • • • • • • • • • • • • • • • • • • • • • • • • • u• • • • • • • • • • _ • • • • • • • • • •~==:::.=:::=:.:::.:.::::.~.:.~;.:.~Il,..._-~:~·~.-:::-:;·::-:: .
0.295
.....-.,..._....-,..
__
._..~o ,-
....- 0.29 _ / /
;-- -
0.285
0.8 0.85 0.9 0.95
time
1.05 1.' 1.15 1.2 '.25
x10.10
eq 3.17
Figure 3.2 Response o/track&hold circuit on step input
From 3.15, n can be solved. Both Ts and 'trepresent times, by introducing a time ratio <p= Ts /'tthe equation can be further simplified
Ts cp
n= T2ln2=2ln2 eq 3.16
As in this paragraph the interest is in finding a value for R, this formula is rewritten, giving R as function of£S,n and C. With this equation the values in table 3.2 were calculated
R
1fsn C2ln2
8 9 10
III
12640 MHz 320 MHz 160 MHz 80 MHz 40 MHz
81.45 fF 325.8iF 11.303 pF 5.213 pF 20.85 pF
1730 768.8 346.0
1572 -1:~:~8
1680 718.8 296.0 1107.2 22.08
Table 3.2 resistor values at various accuracies according to step input criterion
3.3.2 sine input settling
As this track and hold will be used as front end of an AID converter, one can encounter a diversity of input signals. It is more likely to encounter periodical input signals rather than the step input described in 3.3.1. Inthis paragraph it is examined how the circuit's output behaves when applying a sinusoid input voltage.
This time domain analysis will use a worst case situation, the tracking period starts at the zero crossing of the input signal. This specific case will lead to a maximum swing of the output voltage.
The initial value of vo(t
=
0) is exactly the opposite of the input value viet=
Y2 Ts). The average swing of the output voltage will be smaller.The input signal will be
v,( t)=v,
sin (00,'
)=v,sin (~ 00,,) eq
3.18where 11 represents the frequency ratio 11
=
fsI ii. Nyquist condition means 11=
2. Assume the tracking period starts at t=
0 and finishes at t=
Y2 Ts. At the end of the tracking time the input signal reachesv,( ~
T,)=v,Sin(~oo,~
T,)=v'Sin(;) eq
3.19As sine is an odd function, the initial condition vo(O), the previous held value, will be
v,(O)=-v,Sin(;) eq
3.20Combining the circuit's equation (eq 3.12) with this sine wave input (eq 3.18) gives an output voltage of
eq 3.21
Figure 3.3 illustrates input and output signals. Again, at t= Y2 Tsthe output must approach the input signal with a certain accuracy. However, now the limit to be reached is more complicated than for step input settling. The limit to be reached is a decision level close to viet = Y2 Ts). As viet = Y2 Ts) can have various values, dependent on the frequency ratio 11 (equation 3.19), there is no longer a fixed limit to be reached. Equation 3.22 finds the appropriate decision level.
Strict Limit=
v,21
-'floor (2,-1 :,
v,(~ T,)) v ,i-' ceil (
2,-1 :,v,( ~ T,))
when vi (
~
Ts)is rising whenVi (~
TJ
is fallingeq 3.22
By equating 3.21 to 3.22 at t= Y2 Ts, and substituting frequency ratio 11= fsI ii and time ratio
<p= TsI'tone gets
2TT17CfJ2 2
(-T
e - cos -(TT)+ -17CfJ . (TT)]sm - - sm -. (TT)e-T =
floor(
2n-lsm -. (TT))2l-n eq 3.23(2TT) +(17CfJ) 17 2TT 17 17 17
Output \Oltage with sinoid input, n=8 Is =400MSamples/s
0.4, - r - - - - , - - - , - - - , - - - , - - - , . - - - - , . - - - - , . - ,
0.2 _..._ .•.--...- •...- ..._ -
-02'"",_..---.1--···..···-·-·
'"-'--- \.
-0.4 '--'-_ _--'-_ _--'-_ _--'-_ _--'-_ _--'-_ _--'-_ _--'-,---J
O.g 1.1 1.2 1.3 1.4 1.5 1.6
x10"
0.212
!:o~~~;~ ••••••.••..•••••••••...••.••••:••.•••.•.••.•
/
/
,1.368 1.37 1,372 1,374 1.376 1,376
Time [sJ x10"
Figure3.3Response of track& hold circuit on sine input
-
...IIIf0-
-
Il° 2 ' - - - 4 L . - - - 6L . - - -
8' - - - 1LO - - 1L2 - - 1L4 - - 1L6--,La---"20
11=fsIfj Figure3.4rp as function of,., using strict limit for n= 8
By substituting n = 8 in equation 3.23, and numerically solving q> as a function of 11, the characteristic shown in figure 3.4 is obtained. A peak ofq> = 00 means the time constant'!= O. So for certain frequency ratios 11 a track & hold with infinitely small time constant'! is needed. This is because Vi(Yz Ts) is a continuous function of 11, see equation 3.19. For certain values of 11 it is at a decision level. In those cases there is no room for the output to lag behind the input, which translates in a demand for an infinitely fast circuit. This problem is of the same kind as the comparator ambiguity problem.
160
140
120
.... 100
-
'"~ II
0$- 80
60
40
20
2 6 8 10 12 14 16 18 20
11=f
SI fj
Figure3.5 rpasfunction of" using relaxed limitfor n= 8
However, as decision levels are introduced by the comparators in the quantizer, which is succeeding the track & hold, one can consider the decision levels to be a problem of the quantizer, and not of the track & hold. In this line of thought, a relaxed limit is introduced. According to this limit, the output is accurate enough when it approaches the input within an error band of one quantization step. Equation 3.24 gives a formal definition ofthe relaxed limit.
Vi (
~
T s)-q=v
i (~
T s)-V
a21-
n forvi (t
Ts)risingRelaxedLimit= eq 3.24
Vi(~
T s)+q=v
i (t
T s)+V
a21 -n forvi( t
T s)fallingBy equating 3.21 to 3.24 at t
=
Yz Ts,and substituting frequency ratio 11=
fs / [; and time ratio<p= Ts / 'tone gets
2TT'7CfJ
f -T
(TT) '7CfJ,(TT)l . (TT) -T .
(TT) l-n(2TT
t
+ ('7CfJt l
e - cos -;; +2TT SIn -;;J-
SIn -;; e =SIn -;; - 2 eq 3.25By substituting n = 8 in equation 3.25, and numerically solving <p as a function of 11, the characteristic shown in figure 3.5 is obtained. Itdemonstrates the envelope as encountered in figure 3.24. Intuitively, one would expect to find a maximum value for <p (corresponding to a minimum't)
for the Nyquist situation (11 = fs / [; = 2), as this corresponds with the fastest occurring input signals.
However, this maximum occurs at 11= 3.65, which is about half the Nyquist rate.
As can be observed in figure 3.6, for 11 = 3.65 the input signal has the maximum rate of change at the sampling moment. Sampling moments are indicated by the vertical lines. Close to the sampling moment, the difference between input and output becomes so small, that the output does not come nearer to the input, but can only follow it. In order to follow a faster input, a faster circuit is needed.
···,~···;···n··
: .
0.2 .f : '" I : i
i '. i
J11=~ .... \ : j \ !
oj $=~5.37'\ i i \ l I
"C=4.4176••01~ 1 ~\
i
jO2 : \ : : :
- . : ~: : :
, , , 't '
...~... ···t···
0.302 . , - - - , - - . - - - . ,
O. 3 •..~
2···..
~:~':.::;:;:
,~,--1'-" "".'.':.: .
0298 11 . / :
. ·<!r·~35:a7..·....· ·""'.---!
0.296
.~~.~:~.~:.~~.~O.~ j .
0.294
8.65
X10.9 8.6
8.55
..
0.228
.,t.< .
0226 11 =3.65 /j
. ·<!r·..1-45-:&3....j.·r:- - - f 0.224 "C=1.072ge-011Y/j
--_···--·l'···· ...~_.---_.. _... _-._ ... _...-...-
0.222 ;' i
/ :
10
X10.9 8 9
7 5 6
.
,0.2 ...·j..·..·...
f·....·....···; /
11=~.65 j :
o =~45.63
i ; i
"C~.072re.01~/
i
-0.2 f'.~:
..
:~;-' j : ..
5 6 7 8 9 8.55 8.6 8.65
x10.9
0 . 2 : : : . / j
...n -~: ~. ~.: / I .:. ..
o ~ =~3.23
! / ; i
..'e·;:;t,67~'O~. :/ .'
+ + .
- 0 . 2 : : : :
:
~~./'! 1 15 6 7 8 9 10
n=8, relaxed quantization limit x10.9
. . .
0.116 : /
0.114·~·~~...· ·....
)T....·..··..··....·...·..
:/0112'41'"93:2-a ..· ; ..!. ....·r.-:- - - j
oo,:;,~167~?;/< ...
8.55 8.6 8.65
n=8, relaxed quantization limit,zo0"'lr9~
Figure3.6Maximum rate ofchange at17= 3.65
eq 3.26 The maximum of<p at T] = 3.65 can also be proven analytically. The rate of change of the input signal at the sampling moment is
[dUJt)]
- d - 1 =[d {
-d Asin(wJ)}]
1 =-Acos -W s (rr)t I=-T t I=-T n n
2 ' 2 ' ' f ' f
Equation 3.26 shows the rate of change of the input voltage as function ofT] at t
=
Y2 Ts•Extreme values can be found by differentiating to T] and equating to O. Doing so reveals there is a maximum at T]=
3.65 (equation 3.27).~[[dVi(t)] d'1 dt
t='21T,J1=A~s
'1l J
-cos(rr)+ rr sin(rr))=o'1 '1 '1~
'1=3.65 eq 3.27eq 3.28 Figures 3.4 and 3.5 demonstrate <p as function ofT] for accuracy n
=
8. Higher accuracies result in similar graphs. The maximum is at the sameT] (confirmed by the fact equation 3.27 does not contain n). Only the values found for <pare larger.For various accuracies, both at Nyquist (T] = 2) and at worst case situation (T]
=
3.65), <p was calculated. Using Ts=
<p1, an expression for R can be found (3.28). Tables 3.3 and 3.4 give values of<pandR for various accuracies.R= 1
cpC
Is
8 9 10 11 12
640 MHz 320 MHz 160 MHz 80 MHz 40 MHz
81.45 fF 325.8fF 1.303 pF 5.213 pF 20.85 pF
35.44 50.18 70.98 100.45 142.16
542.3 192.2 67.73 23.84 8.414
492.3 142.2 17.73 -26.16 -41.586
Table3.3 resistor values at various accuracies according to sine input (Nyquist) criterion
8 9 10 11 12
640 MHz 320 MHz 160 MHz 80 MHz 40 MHz
81.45 fF 325.8 fF 1.303 pF 5.213 pF 20.85 pF
- -
145.6 289.3 576.6 1151 2300
131.8 33.16 8.319 2.083 0.5213
81.80 -16.84 -41.68 -47.92 -49.48
Table3.4 resistor values at various accuracies according to sine input (worst case) criterion
3.3.3 resistor size overview
In order to give an overview of the resistor values dictated by the various criteria, the resistance values found in the last 2 paragraphs are put together in table 3.5.
II
R step input settling Rsille input settling (Nyquist)
Rsine illput settling (worst case)
8 9 10 11 12
1730 768.8 346.0 157.2 72.08
542.3 192.2 67.73 23.84 8.414
131.8 33.16 8.319 2.083 0.5213
Table3.5R= Rin+Ronat various accuracies for different criteria
Itis interesting to see the size of the steps in resistance between the various accuracies according to the different criteria. Table 3.6 gives the average R(n)lR(n+1) over all n's for the different criteria.
The switches will be implemented as MOSFET switches. The resistance of these is proportional to l/width. So the listed factors show the grow factor of the switch width.
criterioll
R step size
step input settling sine input settling sine input settling
(Nyquist) (worst case)
2.21 2.83 3.99
Table3.6resistance step size for different criteria
By subtracting the 50
n
input resistance Rin from R, the values for Ron are found. These are listed in table 3.7. Notice that the negative resistances are unfeasible, it is impossible to create a switch with a negative Ron resistance.n
ROilstep input settling ROilsine input settling (Nyquist)
ROilsine input settling (worst case)
8 9
1680 718.8
492.3 142.2
81.80 -16.84
10 11 12
296.0 107.2 22.08
17.73 -26.16 -41.586
-41.68 -47.92 -49.48
Table3.7Ronat various accuracies for different criteria
Using Cadence, the Ron versus W characteristic was found. From this, the widths corresponding to the resistor values listed in table 3.5 where obtained. So the 50
n
input resistance Rin is neglected.Simulation will show how big is the influence of this neglection.
_4_.8_9_51_Il
_m_---'---1_7_.7_0_1l
__m_-,-6_9_.8_7_Il
_m_---'_2_99_.2_ll
m_ _11750!1Il1 n
W step input settling W sine input settling (Nyquist)
W sine input settling (worst case)
8
0.6985 Ilm 1.541 Ilm
9
1.197 Ilm 3.525 Ilm
10 2.176 Ilm
18.978 Ilm
11
4. 192 1lm 24.41 Ilm
12
8.469 Ilm 69.07 Ilm
Table3.8 Wat various accuracies for different criteria
3.4 simulation
In order to verify the validity of the developed theory and to check if required accuracy can be achieved with the calculated values of R and C, simulations were performed. The simulation done was a transient analysis over 150 sample times. The input signal was a sine with amplitude Va and frequency close to Nyquist, fi = is (50/101). The first 50 sample times are ignored (for transients), and the last 100 sample times are used for anfft. From the obtained spectrum the signal to distortion ratio was calculated.
As switch a NMOS transistor was used. Ideal input voltage dependent bootstrapping was applied to make the Ron independent of the input voltage. This gives the most linear switch. More about this switch technique can be found in chapter 4.
10.00 68.01 11.00 73.93 11.99 78.60 12.76 84.28 13.71
10.96
1
66.17 10.70 77.87 12.64 79.71 12.95 77.45 12.57
Table3.9 simulation results, achieved accuracies for different criteria
The simulation demonstrates that when using the widths based on "sine wave settling (Nyquist)"
criterion the target accuracies are reached. Regarded the simulation's input signal is a sine wave near Nyquist, this does not come as a surprise. Itproves the theory about factor<pbeing correct.
According to table 3.9, using the widths calculated for the "sine wave settling (Nyquist)" criterion always results in sufficient extra accuracy. This will assure that quantization noise will be the accuracy limiting factor of the AID converter.
As thermal noise and distortion and the quantization noise (that will be added by the block following the track& hold) are uncorrelated noise sources, their powers can be added. Tables 3.1 0 and 3.11 show what happens for the 8 and 12 bit case, and give the maximum achievable number of bits.
49.92 dB 59.47 dB 61.98 dB 49.23 dB
Table 3.10 noise and distortion in8 bit case and it's consequence
74.00 dB 83.55 dB 84.28 dB 73.19 dB
Table3.11noise and distortion in12bit case and it's consequence
98.17103 885.1 103 1578 103 83.68 103
25.12 106 226.5 106 267.9 106 20.86 106
4.58410-7W 5.08410-8W 2.852 10.8W
1.791 10-9W 1.987 10-10W 1.679 10-10W
4 Switches
4. 1 introduction
As illustrated in chapter 2, track & hold circuits utilize switches. Because the track & hold circuit will be implemented in CMOS technology, it is an obvious choice to use MOS transistors for switches. This can be a single NMOS, a single PMOS or a combination of both. Due to the higher mobility of electrons, NMOS transistors are preferred. Figure 4.1 demonstrates a NMOS transistor used as switch.
= vsource =
+ VSignal
T
eq 4.1
Figure4.1 NMOS transistor used as switch
When a switch is closed, it should have a very low (ideally zero) impedance, leading to a low (ideally zero) voltage across the switch. The voltage across the switch corresponds with the drain source voltage. In case of a very low drain source voltage the transistor will operate in its linear region.Inthat region the drain current will be
. W ( VdS ) 1 W { ( ) 2 }
Id=J1CoxL VgS-V/-
T
Vds="2J1CoxL 2 VgS-Vt Vds-V dseq 4.2
The switch is controlled by applying a voltage to Vgate. If Vgate> Vt+Vsource the switch will be on. If Vgate<Vt+Vsource, the switch will be off.
The most simple method is to control Vgate with fixed voltages, like for example Vddwhen the switch should be on, and ground when the switch should be off. As can be seen in figure 4.1, the input voltage will be connected to the transistor's source. So Vgs will change as the input voltage changes.
According to equation 4.2 this means the resistance of the switch changes as Vgs changes. This will cause distortion at the output, becauseRonis a function of the input signal.
Three techniques for cutting back effects of this non constantRon are investigated:
1. input independent bootstrapping: by applying a large Vgate, the relative change of Vgs due to the input voltage becomes smaller.
2. input dependent bootstrapping: if the gate voltage is made to be a sum of the input voltage and a fixed value, Vgs and thusRonwill be independent ofVin •
3. transmission gate: If a NMOS and a PMOS transistor are connected in parallel, than these can be made so that the increase of one'sRonis compensated by the decrease of the other'sRon.
4.2 switch techniques
4.2.1 input independent bootstrapping
eq 4.3 The input voltage dependency ofVgs can be reduced by using a higher Vgate. If for example Yin (=Vs) varies between 0.6V and 1.2V, with Vg= 1.8V, this means the relative change ofVgs (b.VgsNgsaverage) is 2/3.
R I . C'l. V _.1 Vgs V _ 1.2-0.6 2
e atIve flange gs - -j- - ) gs - 1
\ Vgs -(1.2+0.6) 3 2
Making Vgate 3/2 times as large (2.7V) decreases this relative change ofVgs to 1/3 R I . C'l. V .1 Vgs 2.1-1.5 1
e atIve flange gs
=
-j- - )=
13"
\ Vgs -(2.1 + 1.5) 2
eq 4.4
However, there are limitations to how high Vgate can be made without damaging the switch. In [6]
chapter 4 it is suggested that in order to have reliable switch with reasonable lifetime, Vgs should not exceed Vdd •
Figure 4.2 illustrates the input independent bootstrapping. The higher gate voltage is represented by the extra voltage source Vx • There is no need to use an extra supply voltage, the higher Vgate can be made from Vddwith a special circuit.
= vsource =
+ V
Signal
Figure4.2input independent bootstrapping
4.2.2 input dependent bootstrapping
Input voltage dependency of Ron can theoretically be eliminated using input voltage dependent bootstrapping. When the switch must be on, a constant dc voltage source is connected betweenYin
(= Vs) and Vg which causes Vgs and thus Ron to also be constant. This connecting is done with MOS switches, so one is reducing the problems of a non ideal switch using even more non ideal switches.
This approach is illustrated by figure 4.3.
In order to create this voltage source Vxthat is connected between gate and source when the switch should be on, another special circuit is needed. Such a circuit is described in [6]. This circuit will be further explained in chapter 5 of this thesis.
"gate
=
"in + "x= "
.ouree=
+ "signal
Figure4.3input dependent bootstrapping
4.2.3 transmission gate
A transmission gate is depicted in figure 4.4. A transmission gate does not require additional voltage sources, which makes it attractive. When the switch is "on", the gate of the NMOS is connected to Vdd , and the gate of the PMOS to ground. When the switch is "off', the gate of the NMOS will be connected to ground, and the gate of the PMOS to Vdd • In "on" state, ideally the voltage across the switch (Vds)would be zero. For a real switch this is not the case, however Vdswill be small and Vd ~ V s. As the input voltage increases, V gs of the NMOS decreases due to the fixed gate voltage, thus increasing Ron N. At the same time, Vsg of the PMOS increases, therefore decreasingRonP.This is illustrated in figure 4.5.
As stated before,V ds will be small andV ds2even more so. Inthe approximation in equation 4.2, V ds2
is neglected. When one calculates the resistance of a NMOS and PMOS switch in parallel, using this approximation, one finds the resistance will be constant when !-LnWn= !-LpWp. This is illustrated in figure 4.5. There is an "asymmetry" in figure 4.5, the point where RonN= RonP lies above 0.5 Vdd.
This is caused by a difference in threshold voltages.
By using the exact form of equation 4.2, substituting Vds
=
Ron I, and subsequently solvingRon from this expression, one getsR~~.!.I-l+.ir-l+[ -21-]2)
I\ ~ ~C~~(V,,-V,)
J eq4.5+ "signal
Figure 4.4transmission gate
The result of connecting a NMOS and PMOS with this Ron characteristic in parallel is given in figure 4.6. This demonstrates Ron of a transmission gate will not be constant as input voltage changes.