-145.6 289.3 576.6 1151 2300
131.8 33.16 8.319 2.083 0.5213
81.80 -16.84 -41.68 -47.92 -49.48
Table3.4 resistor values at various accuracies according to sine input (worst case) criterion
3.3.3 resistor size overview
In order to give an overview of the resistor values dictated by the various criteria, the resistance values found in the last 2 paragraphs are put together in table 3.5.
II
1730 768.8 346.0 157.2 72.08
542.3 192.2 67.73 23.84 8.414
131.8 33.16 8.319 2.083 0.5213
Table3.5R= Rin+Ronat various accuracies for different criteria
Itis interesting to see the size of the steps in resistance between the various accuracies according to the different criteria. Table 3.6 gives the average R(n)lR(n+1) over all n's for the different criteria.
The switches will be implemented as MOSFET switches. The resistance of these is proportional to l/width. So the listed factors show the grow factor of the switch width.
criterioll
R step size
step input settling sine input settling sine input settling
(Nyquist) (worst case)
2.21 2.83 3.99
Table3.6resistance step size for different criteria
By subtracting the 50
n
input resistance Rin from R, the values for Ron are found. These are listed in table 3.7. Notice that the negative resistances are unfeasible, it is impossible to create a switch with a negative Ron resistance.n
Table3.7Ronat various accuracies for different criteria
Using Cadence, the Ron versus W characteristic was found. From this, the widths corresponding to the resistor values listed in table 3.5 where obtained. So the 50
n
input resistance Rin is neglected.Simulation will show how big is the influence of this neglection.
_4_.8_9_51_Il
Table3.8 Wat various accuracies for different criteria
3.4 simulation
In order to verify the validity of the developed theory and to check if required accuracy can be achieved with the calculated values of R and C, simulations were performed. The simulation done was a transient analysis over 150 sample times. The input signal was a sine with amplitude Va and frequency close to Nyquist, fi = is (50/101). The first 50 sample times are ignored (for transients), and the last 100 sample times are used for anfft. From the obtained spectrum the signal to distortion ratio was calculated.
As switch a NMOS transistor was used. Ideal input voltage dependent bootstrapping was applied to make the Ron independent of the input voltage. This gives the most linear switch. More about this switch technique can be found in chapter 4.
10.00 68.01 11.00 73.93 11.99 78.60 12.76 84.28 13.71
10.96
1
66.17 10.70 77.87 12.64 79.71 12.95 77.45 12.57
Table3.9 simulation results, achieved accuracies for different criteria
The simulation demonstrates that when using the widths based on "sine wave settling (Nyquist)"
criterion the target accuracies are reached. Regarded the simulation's input signal is a sine wave near Nyquist, this does not come as a surprise. Itproves the theory about factor<pbeing correct.
According to table 3.9, using the widths calculated for the "sine wave settling (Nyquist)" criterion always results in sufficient extra accuracy. This will assure that quantization noise will be the accuracy limiting factor of the AID converter.
As thermal noise and distortion and the quantization noise (that will be added by the block following the track& hold) are uncorrelated noise sources, their powers can be added. Tables 3.1 0 and 3.11 show what happens for the 8 and 12 bit case, and give the maximum achievable number of bits.
49.92 dB 59.47 dB 61.98 dB 49.23 dB
Table 3.10 noise and distortion in8 bit case and it's consequence
74.00 dB 83.55 dB 84.28 dB 73.19 dB
Table3.11noise and distortion in12bit case and it's consequence
98.17103 885.1 103 1578 103 83.68 103
25.12 106 226.5 106 267.9 106 20.86 106
4.58410-7W 5.08410-8W 2.852 10.8W
1.791 10-9W 1.987 10-10W 1.679 10-10W
4 Switches
4. 1 introduction
As illustrated in chapter 2, track & hold circuits utilize switches. Because the track & hold circuit will be implemented in CMOS technology, it is an obvious choice to use MOS transistors for switches. This can be a single NMOS, a single PMOS or a combination of both. Due to the higher mobility of electrons, NMOS transistors are preferred. Figure 4.1 demonstrates a NMOS transistor used as switch.
= vsource =
+ VSignal
T
eq 4.1
Figure4.1 NMOS transistor used as switch
When a switch is closed, it should have a very low (ideally zero) impedance, leading to a low (ideally zero) voltage across the switch. The voltage across the switch corresponds with the drain source voltage. In case of a very low drain source voltage the transistor will operate in its linear region.Inthat region the drain current will be
. W ( VdS ) 1 W { ( ) 2 }
Id=J1CoxL VgS-V/-
T
Vds="2J1CoxL 2 VgS-Vt Vds-V dseq 4.2
The switch is controlled by applying a voltage to Vgate. If Vgate> Vt+Vsource the switch will be on. If Vgate<Vt+Vsource, the switch will be off.
The most simple method is to control Vgate with fixed voltages, like for example Vddwhen the switch should be on, and ground when the switch should be off. As can be seen in figure 4.1, the input voltage will be connected to the transistor's source. So Vgs will change as the input voltage changes.
According to equation 4.2 this means the resistance of the switch changes as Vgs changes. This will cause distortion at the output, becauseRonis a function of the input signal.
Three techniques for cutting back effects of this non constantRon are investigated:
1. input independent bootstrapping: by applying a large Vgate, the relative change of Vgs due to the input voltage becomes smaller.
2. input dependent bootstrapping: if the gate voltage is made to be a sum of the input voltage and a fixed value, Vgs and thusRonwill be independent ofVin •
3. transmission gate: If a NMOS and a PMOS transistor are connected in parallel, than these can be made so that the increase of one'sRonis compensated by the decrease of the other'sRon.