SWITCHING THEORY

SWITCHING THEORY

course 5A050

september-november 2004 Twan Basten

Ralph H.J.M. Otten

Eindhoven University of Technology

overview

you have read in “introduction to logic design":

chapter 1.1: number systems

chapter 5: arithmetic circuits, multiplexers, gate arrays

part five:

positional number notations

negative-number representations

addition, subtraction

overflow conditions

part six:

arithmetic circuits

arithmetic logic units

motivation

time vs. space trade-offs

doing things fast requires more logic and thus more space

example: carry lookahead logic

arithmetic logic units

critical component of processor datapath

core of most computer instructions

arithmetic circuits are excellent examples of combinational logic design

we need to understand number systems

positional number notation

nbase 10 (decimal)

154 = 1 x 100 + 5 x 10 + 4 x 110

= 1 x 10 + 5 x 10 + 4 x 10^{2 1 0} nbase 2 (binary)

10011010 = 1 x 2 + 0 x 2 + 0 x 2 + 1 x 2 + 1 x 2 + 0 x 2 1 x 2 + 0 x 22

= 128 + 16 + 8 + 2 = 154

2 1 0

4 3 6 5

7

nbase 8 (octal; 0, 1, 2, 3, 4, 5, 6, 7) 232 = 2 x 8 + 3 x 8 + 2 x 88

= 2 x 64 + 3 x 8 + 2 x 1 = 128 + 24 + 2 = 154

2 1 0

nbase 16 (hexadecimal; 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F) 9A = 9 x 16 + 10 x 1616

= 144 + 10 = 154

1 0

nbase 3 (ternary; 0, 1, 2)

12201 = 1 x 3 + 2 x 3 + 2 x 3 + 0 x 3 + 1 x 33

= 1 x 81 + 2 x 27 + 2 x 9 + 0 x 3 + 1 x 1 = 81 + 54 + 18 + 1 = 154

1 0

2 4 3

binary 2 octal 2 hexadecimal

bit grouping remember: 154 = 10011010 = 232 = 9A _{10 2 8 16}

10011010 2 3

2 ₈

10011010 A ₁₆ 9

why does this work?

assume n = 4k bits binary number k digits hex number

20 1 0 12 22 3 2 32 ...

2 4 3 4

32 2 2

1 2 12

a a a a

n n n a an n n

n a an

+ + + + +

− −

− + + −

− −

− +

−

) 0 ( 24 0) 02 21 2 1 22 23 ( 3 ...

) 1 ( 24 0) 42 21 2 3 22 23 ( 1

a a a a

n k n a

n a n a

a

+ + + + +

− −

− +

− +

− +

=

160 ... 0 16 1

1 k b

bk− − + +

= with b created with bit groupingi

reverse transformation works as well

) 1 k (

2

=

octal 2 hexadecimal vv

2

2328

9A16 010 011 10

base 10 to base X: successive division

154 / 3 = 51 remainder 1 51 / 3 = 17 remainder 0 17 / 3 = 5 remainder 2

5 / 3 = 1 remainder 2 1 / 3 = 0 remainder 1

1 0 2 2

1 ₃

= 1 + 18 + 54 + 81 = 154 15410

why does this work?

0 remainder 0

... 1 2 3

1 2

0 an Rn an Rn aR a

R

Q =N= − − + − − + +

1 remainder 2 0

4 ...

3 2 0 1

1 an Rn an Rn a R a

R

Q =Q = − − + − − + +

1 remainder

2 0

1= − = −

− an

R Qn Qn

...

0 0 1 1 2 ...

1 2 1

0) ... 1 2 ( 1

R a R n a

n R n a n R a

a R n a n a a N

+ +

− + + −

− −

=

−

= −

Assume ?

overview conversions

base 2

base 8

base 16 base 10

base 3

positional conversion

bit grouping successive division

via base 2

addition / subtraction

addition base 3

1 2 2 0 1 2 1 2 0 +

1 carry

2 1 1

0 1

2

(154 + 23 = 177)

subtraction base 3

1 2 2 0 1 -2 -1 -2 2 + 1 1 2 1

(154 - 23 = 131) -1

borrow 3

-1 3

-1 3

(= 6 + 9 + 162 = 177)

(= 2 + 3 + 18 + 27 + 81 = 131) 2 1 2

- 1 2 2 0 1

representation of negative numbers

representation of positive numbers same in most systems

major differences are in how negative numbers are represented

three major schemes:

sign and magnitude

ones complement

twos complement

assumptions:

4 bit machine words

16 different values can be represented

roughly half are positive, half are negative

sign and magnitude representation

0000

0111 0011 1011

1111 1110 1101 1100

1010 1001

1000

0110 0101

0100 0010 0001

+0 +1

+2 +3 +4 +5 +6 -0 +7

-1 -2 -3 -4 -5

-6 -7

0 100 1 100

nhigh order bit is sign: 0 = positive (or zero), 1 = negative nthree low order bits is the magnitude: 0 (000) thru 7 (111) nnumber range for n bits = +/-(2 -1)n-1

n2 representations for 0

= + 4

= - 4

+

-

ncumbersome addition/subtraction

sign and magnitude: addition and subtraction

straightforward Addition of magnitude result sign equals operands' sign general remark

subtraction can be implemented via addition and negation:

4 - 3 = 4 + (-3) addition of two numbers with equal signs:

addition of two numbers with different signs:

1 3 4+

-1 -3 -4+ 0001

0011 0100

1001 1011 1100

4 -3

1+

0100 1011 0001 how do we

implement this?

subtract

-4 3 -1+

1100 0011 1001

need subtractor and comparator

ones complement

0000

0111 0011 1011

1111 1110 1101 1100

1010 1001

1000

0110 0101

0100 0010 0001

+0 +1

+2 +3 +4 +5 +6 -7 +7

-6 -5 -4 -3 -2

-1 -0

0 100 1 100

nhigh order bit is sign: 0 = positive (or zero), 1 = negative nnumber range for n bits = +/-(2 -1)n-1

n2 representations for 0

= + 4

= - 7 + 4

+

-

= - 3 4: offset from -2 +1^n-1

npositive numbers: low order bits are the magnitude nnegative numbers: low order bits are the offset from -2 +1n-1

ncomplications with addition

ones complement

what is the 1's complement representation of -m ?

shortcut method:

bit-wise complement

0111 -> 1000 (7) (-7) example: 1's complement of -7 let m be a positive number

let m be this representation m = (2 - 1) - (m)n

2 1c

4

10 2

(2 ) = 10000 (1)₁₀= 00001₂

11112 - (7)₁₀= 0111_1c

- 10001c= (-7)₁₀

4

10 2

(2 ) = 10000 (1)₁₀= 00001₂

11112 - (-7)₁₀= 1000_1c

- 01111c= (7)₁₀ works also for negative

numbers!

1000 -> 0111 (-7) (7)

and so does shortcut method

ones complement: addition and subtraction

straightforward addition as before,

subtraction is implemented via addition and negation addition of two numbers with equal signs:

addition of two numbers with different signs:

1 3 4+

-1 -3 -4+

4 -3

1 + the same!

adder and bit-wise complement suffice to implement addition and subtraction 0100

1100 1 0000+

0001 0011 0100 +

1110 1100 1 1010 +

1011+ end-around carry 1

1+ 0001

-4 3 -1+

1011 0011 1110 +

(= -5)

end-around carry

why does the end-around carry work?

k, m positive with m > k

k, m positive with m + k < 2n-1

after end-around carry:

it is equivalent to subtracting 2 and adding 1n (m + (-k)) = ?₁₀

= m + (2 - 1) - k _1c n 2 1c

m + k1c = m + (2 - 1) - k ₂ n _{2 2} n

= (m - k + (2 - 1) ) ₁₀ {k, m positive}

so, simply adding 1s complement representations of m and - k means that we have to subtract 2 and add 1 in order to be correct: end-around carryn

1

2 ((-m) + (-k)) = ?₁₀

m + k n n

2

= ((2 - 1) - m ) + ((2 - 1) - k )2 _{2 2}

= (m + k)

= (2 - 1) + [(2 - 1) - (m + k) ] n n

2 2 2

but this is the correct form for representing -(m + k) = ((-m) + (-k)) in 1's comp!_{10 10}

= (2 - 1) - (m + k)n

2 2

twos complement

0000

0111 0011 1011

1111 1110 1101 1100

1010 1001

1000

0110 0101

0100 0010 0001

+0 +1

+2 +3 +4 +5 +6 -8 +7

-7 -6 -5 -4 -3

-2 -1

0 100 1 011

nhigh order bit is sign: 0 = positive (or zero), 1 = negative

= + 4

= - 8 + 3

+

-

= - 5 3: offset from -2^n-1

npositive numbers: low order bits are the magnitude nnegative numbers: low order bits are the offset from -2 n-1

n1 representation for 0 and no complications with addition nnumber range for n bits: from 2 -1 to -2n-1n-1

1s complement, shifted 1 position clockwise

twos complement

what is the 2's complement representation of -m ?

shortcut method:

bit-wise complement + 1

0111 -> 1000 + 1 -> 1001 (7) (-7) example: 2's complement of -7

let m be a positive number

let m* be this representation m* = (2 ) - (m)n

2 2c

4

10 2

(2 ) = 10000 (7)₁₀= 0111_2c

10012c-= (-7)₁₀ 4

10 2

(2 ) = 10000 (-7)₁₀= 1001_2c

01112c-= (7)₁₀ works also for negative

numbers!

1001 -> 0110 + 1 -> 0111 (-7) (7) and so does shortcut method

twos complement: addition and subtraction

straightforward addition as before,

subtraction is implemented via addition and negation

1 3 4+

-1 -3 -4+

4 -3

1 +

adder and bit-wise complement suffice to implement addition and subtraction 0100

1101 1 0001+

0001 0011 0100 +

1111 1101 1 1100 + ignore carry-out

-4 3 -1+

1100 0011 1111 +

simpler addition scheme makes twos complement the most common choice for integer number systems within digital systems

carry-out?

why can the carry-out be ignored?

k, m positive with m > k

k, m positive with m + k ≤≤≤≤2n-1

ignoring carry-out:

it is equivalent to subtracting 2n (m + (-k)) = ?₁₀

= m + (2 ) - k _2c n 2 2c

m + k*2c = m + (2 ) - k ₂ n_{2 2} n

= (m - k + 2 ) ₁₀ {k, m positive}

so, simply adding 2s complement representations of m and - k means that we have to subtract 2 in order to be correct: ignore carry-outn

1

2 ((-m) + (-k)) = ?₁₀

m* + k* n n

2

= ((2 ) - m ) + ((2 ) - k )2 _{2 2}

= (m + k)*

= (2 ) + [(2 ) - (m + k) ] n n

2 2 2

but this is the correct form for representing -(m + k) = ((-m) + (-k)) in 2's comp!_{10 10} (2 ) - (m + k)n

2 2

overflow

adding two positive numbers yields a negative number

5 + 3 = -8

0000 0001

0010 0011

1000

0101 0110

0100

1001 1010 1011

1100 1101

0111 1110

1111

+0 +1

+2 +3 +4 +5 +6 -8 +7

-7 -6 -5

-4 -3

-2 -1

-7 - 2 = +7

0000 0001

0010 0011

1000

0101 0110

0100

1001 1010 1011

1100 1101

0111 1110

1111

+0 +1

+2 +3 +4 +5 +6 -8 +7

-7 -6 -5

-4 -3

-2 -1

adding two negative numbers yields a positive numberor

overflows can only occur with numbers of equal signs!

detecting overflow

+5 +3 -8

0 1 0 1 0 0 1 1 1 0 0 0 overflow

no overflow

overflow if and only if carry-in to sign does not equal carry-out 0 1 1 1 (carries)

+5 +2 +7

0 0 0 0 0 1 0 1 0 0 1 0 0 1 1 1

-7 -2 +7

1 0 0 1 1 1 1 0 1 0 1 1 1

-3 -5 -8

1 1 1 1 1 1 0 1 1 0 1 1 1 1 0 0 0 carry-in ≠≠≠≠carry-out

1 0 0 0

carry-in = carry-out sum of sign bits

carry-out always 0 ! sum of sign bits 0

carry-out always 1 ! carry-in of 1

implies overflow carry-in of 0 implies overflow

underflow

overview

part five:

positional number notations

negative-number representations

addition, subtraction

overflow conditions

part six:

arithmetic circuits

arithmetic logic units

serial binary addition

half adder a_i 0 0 1 1

b_i 0 1 0 1

sum 0 1 1 0

carry 0 0 0 1

sum = a_i' • b_i+ a_i• b_i'

= a_i⊕⊕⊕⊕b_i

carry = a_i• b_i

carry a _i sum

b _i

multi-bit adder : (ripple-carry)

+ a₃ b₃

s₃

+ a₂ b₂

s₂

+ a₁ b₁

s₁

+ a₀ b₀

s₀ c₁ c₂

c₃

a_i b_i 0 1

0 1

0 0

1 0 a_i

b_i 0 1 0

1

0 1

1 0

serial binary addition

a_ib_i c_i

0 1

00 01 11 10 0

1 1 0

1 0 0 s_i 1

a_ib_i c_i

0 1

00 01 11 10 0

0 0 1

0 1 1 c_i+1 1

s_i= c_i⊕⊕⊕⊕a_i⊕⊕⊕⊕b_i

c_i+1= b_i• c_i+ a_i• c_i+ a_i• b_i= c_i• (a_i+ b_i) + a_i• b_i a_i

0 0 0 0 1 1 1 1

b_i 0 0 1 1 0 0 1 1

c_i 0 1 0 1 0 1 0 1

s_i 0 1 1 0 1 0 0 1

c_i+1 0 0 0 1 0 1 1 1 full adder

+ a₃ b₃

s₃

+ a₂ b₂

s₂

+ a₁ b₁

s₁

+ a₀ b₀

s₀ c₁ c₂

c₃ multi-bit adder :

(ripple-carry)

ci a b

+

a b co

+

a b co

+

a b co

+

s 3 s 2 s 1 s 0

adder/subtractor

0 1 a 3 b 3 b 3

0 1 a 2 b 2 b 2

0 1 a 1 b 1 b 1

0 1 a 0 b 0 b 0

sel sel sel sel

ci add/subtract co

overflow

(a - b) = (a + ( - b)) = (a) + b + 1

(a + b) = (a + b)

multiplexers

critical delay: the propagation of carry from low to high order stages

@0@0

@0@0

@n

@1

@1

@n+1 (if n > 0)

@n+2 arrivinglate

signal

@2

@2

@3

@4

@5

@6

@7

@8 s 0

c 1 s 1 c 2

s 2 c 3

s 3 c 4 c 0

a 1 b 1 a 2 b 2

a 3 b 3 0

1

2

3 a0 b 0

final sum and carry

worst-case carry delay

two gate delays to compute c_i+1

a_i a_i

b_i b_i

c_i c_i+1

a_i b_i c_i

s_i

one gate delay to compute s_i assumption: all gates have delay 1

@0

@0

@n

@1

@n+1 (if n>0) 1

0 0 1 1

0 1

0 1 0

1 1 0

1 0

1 1111 + 0001 0

worst case addition

t0 t2 t4 t6 t8

c₀ s₀ c₁ s₁ c₂ s₂ c₃ s₃ c₄

s0, c1 valid s1, c2 valid s2, c3 valid s3, c4 valid

worst-case carry delay

1111 + 0001 worst case

addition

critical delay:

the propagation of carry from low to high order stages

32 bits? 64 bits?

observed delay depends on bit patterns!

solution: carry lookahead logic (not treated)

trade-off between space and time

arithmetic logic units

0 0 f_i= a_i input a_itransferred to output

0 1 f_i= not a_i complement of a_itransferred to output 1 1 f_i= a_ixnor b_i

1 0 f_i= a_ixor b_i compute xor of a_i, b_i compute xnor of a_i, b_i m = 0, logical bitwise operations

m = 1, c₀= 0, arithmetic operations 0 0

1 1 0 1 0 1

f = a f = not a f = a plus b f = (not a) plus b

input a passed to output

complement of a passed to output sum of a and b

sum of b and complement of a m = 1, c₀= 1, arithmetic operations

0 0 1 1

0 1 0 1

f = a plus 1 f = (not a) plus 1 f = a plus b plus 1 f = (not a) plus b plus 1

increment a

twos complement of a increment sum of a and b b minus a

not all operations appear useful, but "fall out" of internal logic

s₁ s₀ function comment

unit implementing logical and arithmetic operations

inputs: a₀, … , a_n-1, b₀, … , b_n-1, c₀ ouputs: f₀, … , f_n-1, f_n(=c_n) control inputs: m (mode), s₀, s₁(selectors)

slice i: 6 inputs m, s₀, s₁, a_i, b_i, c_iand 2 outputs f_i, c_i+1

arithmetic logic unit design

traditional design approach truth table

23 product terms!

equivalent to 25 gates

.i 6 .o 2

.ilb m s1 s0 ci ai bi .ob fi co

.p 23 111101 10 110111 10 1-0100 10 1-1110 10 10010- 10 10111- 10 -10001 10 010-01 10 -11011 10 011-11 10 --1000 10 0-1-00 10 --0010 10 0-0-10 10 -0100- 10 001-0- 10 -0001- 10 000-1- 10 -1-1-1 01 --1-01 01 --0-11 01 --110- 01 --011- 01 .e

m 0

1

1 s1

0 0 1

1

0 0 1

1

0 0 1

1 s0

0 1 0

1

0 1 0

1

0 1 0

1 ci x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

ai 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 0 1 1 0 0 1 1

bi x x x x 0 1 0 1 0 1 0 1 x x x x 0 1 0 1 0 1 0 1 x x x x 0 1 0 1 0 1 0 1

fi 0 1 1 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 1 0

ci+1 x x x x x x x x x x x x x x x x 0 0 0 1 0 1 0 0 0 1 1 0 0 1 1 1 1 1 0 1

& espresso output

arithmetic logic unit design

multilevel implementation using MisII

.model alu.espresso .inputs m s1 s0 ci ai bi .outputs fi co

.names m ci co [30] [33] [35] fi 110--- 1

-1-11- 1 --01-1 1 --00-0 1

.names m ci [30] [33] co -1-1 1

--11 1 111- 1

.names s0 ai [30]

01 1 10 1

.names m s1 bi [33]

111 1

.names s1 bi [35]

0- 1 -0 1

.end 12 gates

\s1

\bi

[35]

[35] m

m m

s1

bi [33] [33]

[33]

[33]

s0 ai

[30]

[30]

[30]

[30]

[30]

ci ci

ci ci

co

\co

\co

\co

\[30]

\[35]

fi

arithmetic logic unit design

clever hand-made multi-level logic implementation

8 gates (but 3 are xor)

logic mode (m=0):

cascaded xors form output f_ifroma_iand b_i output c_i+1don’t care

s₁= 0 blocksb_i (operations involvea_ionly) m = 0 blocks c_i

bi

s1 s0 ai m ci

ci+1 fi

x1

x3

a1 a2

a3 a4

o1

x2

arithmetic mode (m=1):

c_ito xor gate x2

ifs₁= 1, b_ito xor gate x3 ifs₀= 0, x1 passes a_i ifs₀= 1, x1 passes a_i

inputs of o1 are a_i/a_i• c_iand b_i/0 •(a_i/a_i⊕⊕⊕⊕c_i)