SWITCHING THEORY
course 5A050
september-november 2004 Twan Basten
Ralph H.J.M. Otten
Eindhoven University of Technology
previous parts
introduction to logic design
chapter 1 till 1.1.1 and 1.2-1.4
(introduction excluding number systems)
chapter 2 excl 2.6 and 2.9
(boolean algebra / combinational circuits)
first part:
information and digital abstraction
combinational devices and networks
implementation
second part:
boolean algebra
proof techniques
switching algebra
overview
you have read in “introduction to logic design":
chapters 2 and 3: K-maps
chapter 5: delays
part three:
expressions and switching functions
equivalence of devices
canonical representations
part four:
two-level realizations
multilevel minimization
boolean expressions
boolean expressions over the symbols
are defined recursively as follows:
1 2 nx , . . . . . , x , x
are boolean expressions
if and are boolean expressions, then so are
n 2
1
, x , . . . . . , x x
, 1 , 0
X
1X
2(((( )))) X
1(((( )))) X
1'
(((( X
1++++ X
2)))) (((( X
1•••• X
2))))
the symbols of an expression, complemented or not, are called literals
we often omit parentheses,
assuming •••• is evaluated before + , and ' is evaluated before •••• and +
we mostly drop the symbol ••••
we often replace with (((( )))) X
1' X
1conventions
switching functions
a switching function is a function from { 0,1 } into { 0,1 } , and can be represented by a boolean expression over n symbols
n
find the combinational device
corresponding with the switching function x (y+z) +y
y y
y y
z y+z
z y+z
x
x (y+z) x
x (y+z)
x (y+z)+y
switching functions and combinational devices
remark: every switching function can be represented by many different boolean expressions
equivalent combinational devices
two combinational devices ,
each having the inputs , are said to be equivalent, if and only if, whenever they receive the same inputs, they produce the same output
n 2
1
, x , . . . . . , x x
two combinational devices are equivalent if and only if their switching functions are the same
(not necessarily the expressions representing them)
important questions :
functional completeness :
which set of gates allows making any combinational device?
technology mapping :
what is the "best" realization of a given switching function?
functionally complete sets of gates
obviously, { AND, OR, NOT } is functionally complete
x
y y
x
x y x y= x + y = x + y however,
an OR-device has an equivalent device consisting of AND and NOTS !
{ AND, NOT } is functionally complete similarly, { OR, NOT } is functionally complete a set of gates { g
1, g
2, . . . . , g
k} is functionally complete,
if it is possible to construct a combinational device for any given switching function f : { 0,1 } → n { 0,1 }
functionally complete sets of gates
x x
x x
y y
x + y
{ NAND } is functionally complete similarly, { NOR } is functionally complete a NAND-gate is defined as a combinational device
that produces 0 at the output if and only if all inputs are 1 x
y
xy
x 0 0 1 1
y 0 1 0 1
y 1 0 1 0 x 1 1 0 0
f 0 1 1
both NOT and OR can be made
1by exclusively NANDS
canonical representations
a representation of boolean functions is canonical if and only if it satisfies the following condition:
if two functions are the same, then their canonical representations are the same.
can be used to decide equivalence two-level canonical forms
sum of minterms
f 0 0 0 1 1 1 1 1
f ' 1 1 1 0 0 0 0 0 c
0 1 0 1 0 1 0 1 b
0 0 1 1 0 0 1 1 a
0 0 0 0 1 1 1 1
truth tables and sums of minterms, under fixed order schemes,
are canonical representations
f' = a' b' c' + a' b' c + a' b c' f = a' b c + a b' c' + a b' c + a b c' + a b c
f' = a' b' c' + a' b' c + a' b c'
sum of minterms
f 0 0 0 1 1 1 1 1
f ' 1 1 1 0 0 0 0 0 c
0 1 0 1 0 1 0 1 b
0 0 1 1 0 0 1 1 a
0 0 0 0 1 1 1 1
truth tables and sums of minterms, under fixed order schemes,
are canonical representations
a b c = m 1 a b c = m 2 a b c = m 3 a b c = m 4 a b c = m 5 a b c = m 6 a b c = m 7minterms a b c = m 0
f in shorthand notation : f(a,b,c) = ΣΣΣΣm(3,4,5,6,7)
= m3 + m4 + m5 + m6 + m7
= a' b c + a b' c' + a b' c + a b c' + a b c f = a b' (c + c') + a' b c + a b (c' + c)
= a b' + a' b c + a b
f ' = ( a + b c )' = a' ( b' + c' )
= a' b' + a' c' f = a' b c + a b' c' + a b' c
+ a b c' + a b c
unfortunately not very concise
= a (b' + b) + a' b c
= a + a' b c
= a + b c f' = a' b' c' + a' b' c + a' b c'
maxterm shorthand notation
maxterm:
sum of literals
in which each variable
appears exactly once in either true or complemented form, but not both!
maxterm form of a function f:
find truth table rows where f is 0 0 in input column implies true literal 1 in input column implies
complemented literal
f(a,b,c) = ΠΠΠΠM(0,1,2)
= (a + b + c) (a + b + c') (a + b' + c) f'(a,b,c) = ΠΠΠΠM(3,4,5,6,7)
= (a + b' + c') (a' + b + c) (a' + b + c') (a' + b' + c) (a' + b' + c') a
0 0 0 0 1 1 1 1
b 0 0 1 1 0 0 1 1
c 0 1 0 1 0 1 0 1
maxterms a + b + c = M 0 a + b + c = M 1 a + b + c = M 2 a + b + c = M 3 a + b + c = M 4 a + b + c = M 5 a + b + c = M 6 a + b + c = M 7
product of maxterms
f 0 0 0 1 1 1 1 1
f ' 1 1 1 0 0 0 0 0
f' = a' b' c' + a' b' c + a' b c' apply de morgan's law to obtain f:
(f')' = (a' b' c' + a' b' c + a' b c')' f = (a + b + c) (a + b + c') (a + b' + c)
f' = (a + b' + c') (a' + b + c) (a' + b + c') (a' + b' + c) (a' + b' + c')
(f')' = ((a + b' + c') (a' + b + c) (a' + b + c') (a' + b' + c) (a' + b' + c'))' f = a' b c + a b' c' + a b' c + a b c' + a b c
apply de morgan's law to obtain f:
two-level canonical forms and de morgan
from sum of minterms of f' to product of maxterms of f
from product of maxterms of f' to sum of minterms of f m0
M0
conversion between sums and products
minterm to maxterm conversion:
obtain maxterm shorthand using minterm shorthand
replace minterm indices with the indices not already used e.g., f(a,b,c) = ΣΣΣΣ m (3,4,5,6,7) = ΠΠΠΠ M (0,1,2)
maxterm to minterm conversion:
obtain minterm shorthand using maxterm shorthand
replace maxterm indices with the indices not already used e.g., f(a,b,c) = ΠΠ M (0,1,2) = ΣΣΣΣ m (3,4,5,6,7)ΠΠ
minterm expansion of f to minterm expansion of f':
in minterm shorthand form, list the indices not already used in f e.g., f(a,b,c) = ΣΣΣΣ m (3,4,5,6,7) →→→→ f'(a,b,c) = ΣΣΣΣ m (0,1,2)
= ΠΠΠΠ M(0,1,2) →→→→ = ΠΠΠΠ M (3,4,5,6,7)
minterm expansion of f to maxterm expansion of f':
rewrite in maxterm form, using the same indices as f
e.g., f(a,b,c) = ΣΣΣΣ m (3,4,5,6,7) →→→→ f'(a,b,c) = ΠΠΠΠ M(3,4,5,6,7)
= ΠΠΠΠ M (0,1,2) →→→→ = ΣΣΣΣ m(0,1,2
a
b
c d
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
a
b
c d
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
minterm = a'b'c'd' maxterm = a+b+c+d
two-level canonical forms: karnaugh maps
minterms and maxterms in karnaugh maps
f = (a'+b)(b'+c)(b+d')
two-level canonical forms: karnaugh maps
f = a'b'd' + bc a
b
c d
1 0 0 1 0 0 1 1 0 0 1 1 0 0 0 0
a
b
c d
1 0 0 1 0 0 1 1 0 0 1 1 0 0 0 0
example
minimal sum of products
a'+b
b+d' b'+c
minimal product of sums Which implementation is the smallest?
Are minimal SoP/PoS forms canonical?
check: f = (a'b'+a'c+bc)(b+d')
= a'b'd'+a'bc+a'cd'+bc+bcd' a'bcd' + a'b'cd'
overview
you have read in “introduction to logic design":
chapters 2 and 3: K-maps
chapter 5: delays
part three:
expressions and switching functions
equivalence of devices
canonical representations
part four:
two-level realizations
multilevel minimization
the simplification problem
x y
z
x y z
f = xyz + xyz + xyz
= x (y + z)
= xy + xyz
= xy + xyz + xyz
= xy + xz
technology mapping :
what is the "best" realization of a given switching function?
two-level vs multilevel
canonical sum of minterms
two-level minimization
a
b
c
f 3
f 2
f 4
four two-level implementations of f = a' b c + a b' c' + a b' c + a b c' + a b c
canonical product of maxterms f = (a + b + c ) (a + b + c' ) (a + b' + c )
minimal sum of products
f = a + b c
minimal product of sumsf = (a+b) (b+c) any boolean function can be reduced to a two-level form
with a minimal number of literals
f 1
minimal sum of products
Karnaugh maps (veitch 1952, karnaugh 1953)
iterated consensus (quine-mccluskey, 1952-59 )
signature cube generation (mcgeer-sanghavi, 1992)
characteristic binary decision diagrams (coudert-madre, 1992)
however, exact two-level minimization is not tractable !
so why are we then interested in two-level forms ?
and more compact multilevel realizations might exist !
fusible links
1 2 3 4 5 6 7 8 9
a a b b c c
1 2 3 4 5 6
fusible links
1 2 3 4 5 6 7 8 9
a a b b c c
a'c'
bc
ab'
1 2 3 4 5 6
a'c' + bc + ab' sum of products
NB: high signal on unconnected line !!!!
programmable logic arrays
AND-array
sum of products (((( ΣΣΣΣ Π Π Π Π ))))
OR-array product terms
input signals output signals
all possible connections are available before programming
programmable logic array
f0 f1 f2 f3
a b c
programmed logic array
f0 f1 f2 f3
a b c
f0 = a + b'c' f1 = ac'+ ab
f2 = b'c'+ ab f3 = b'c+ a
a
abc a b c a'
b'
c'
a'b'c'
a'b'c a'bc'
ab'c'
abc'
a'bc ab'c
f1 f2 f3 f4 f5 f6
design example:
f1 = a b c f2 = a + b + c f3 = a b c f4 = a + b + c f5 = a XOR b XOR c f6 = a XNOR b XNOR c multiple functions of a, b, c
compact design diagrams
a b c
minimization
programmed logic arrays are multi-output switching functions
that can share product terms
area is proportional to the number of product terms
reliability somewhat related to the number of transistors (switches)
find the sum of products with the smallest number of terms, and among those the one with the fewest literals
two-level minimization
example: f0 = a + b' c' f1 = a c' + a' b f2 = b' c' + a' b f3 = b' c + a f4 = a + b
equations
key to success: shared product terms
1 = asserted in term 0 = negated in term - = does not participate input side:
1 = term connected to output 0 = no connection to output output side:
two-level reductions for programmable logic arrays
inputs a 0 - 1 1 -
b 1 0 - 0 -
c - 1 0 0 - - 1 -
reuse termsof 1
outputs f 0 0 0 0 1 1
f 1
0 1 0 0
f 2 1 0 0 1 0
f 3 0 1 0 0 0 0 0 0 1
f 4 0 0 0 0 1 1 personality matrix
product t erm
a b b c a c b c a b
example: f0 = a + b' c' f1 = a c' + a' b f2 = b' c' + a' b f3 = b' c + a f4 = a + b
equations
key to success: shared product terms
1 = asserted in term 0 = negated in term - = does not participate input side:
1 = term connected to output 0 = no connection to output output side:
two-level reductions for programmable logic arrays
inputs a 0 - 1 1 -
b 1 0 - 0 -
c - 1 0 0 - - 1 -
reuse termsof 1
outputs f 0 0 0 0 1 1
f 1
0 1 0 0
f 2 1 0 0 1 0
f 3 0 1 0 0 0 0 0 0 1
f 4
0 0 0 1 1
BUT
= a + a' b
1 personality matrix
product t erm
a b b c a c b c a b
by involution
programmable logic arrays
(((( ))))
ΣΠ ΣΠ ΣΠ
ΣΠ ==== ΣΠ ΣΠ ΣΠ ΣΠ
(((( ΣΣΣΣΣΣΣΣ ))))
====
(((( Π Π Π Π ΣΣΣΣ ))))
====
(((( ))))
==== Π Π Π Π Π Π Π Π
by the de morgan
laws
(((( Π Π Π Π ΣΣΣΣ ))))
====
by involution
by the de morgan
laws
by the de morgan
laws
sum-of products ΣΣΣΣ Π Π Π Π
and-array or-array
input register
φφφφ1
input output
φφφφ2 output register
programmable logic arrays
(((( ΣΣΣΣΣΣΣΣ ))))
====
sum-of products ΣΣΣΣ Π Π Π Π
conversion between and-or, or-and, nor-nor, nand-nand, etc
and-array or-arrayinput register
φφφφ1
input output
φφφφ2 output register
left nor-array
right nor-array
inverting
input register inverting output register
φφφφ1
φφφφ2
input output
multilevel minimization
3. map factored form onto library of gates factored form:
sum of products of sum of products . . .
x = (a b + b' c) (c + d (e + a c')) + (d + e)(f g)
+ + +
+ +
•
•
•
•
•
•
•
x f1
f2
f3
f4 a
b b'
c c
d e a c'
f g d e
1. factor out common sublogic (reduce fan-in, increase gate levels), subject to timing constraints
2. minimize number of literals (correlates with number of wires)
operations on factored forms:
• decompostion
• extraction
• factoring
• substitution
• collapsing
manipulate network by interactively issuing the appropriate instructions
multilevel minimization
there exists no algorithm that guarantees an "optimum" multi-level network to be obtained
take a single boolean expression and replace it with a collection of new expressions:
multilevel minimization: decomposition
after decomposition f ab
dc
before decomposition f ab
c ab d ac d bc d
f = a b c + a b d + a' c' d' + b' c' d’ (12 literals, 11gates) f rewritten as:
f = x y + x' y'
x = a b (8 literals, 7 gates)
y = c + d
f = (a + b) c d + e g = (a + b) e' h = c d e
(11 literals, 8 gates)
"kernels": primary divisors
multilevel minimization: extraction
before extraction e e
g a h
a
b b
c c
d d
f
factor out common intermediate subfunctions from a collection of functions:
(11 literals, 7 gates) f = x y + e
g = x e' h = y e x = a + b y = c d after extraction:
after extraction x
e g
y
h ab
cd
f
can be rewritten as:
f = (a + b) (c + d) + e (5 literals, 4 gates)
multilevel minimization: factoring
before factoring a
a
b b c c
d d
e
f
after factoring ba
cd e
f an expression in two level form is re-expressed in multi-level form:
f = a c + a d + b c + b d + e (9 literals, 5 gates)
substitution: function g into function f, express f in terms of g f = a c' + b c
g = a + c (6 literals, 5 gates)
collapsing: reverse of substitution; used to eliminate levels to meet timing constraints
f = g (c' + b)
= (a + c) (c' + b)
= a c' + a b + b c
= a c' + b c
f rewritten in terms of g:
f = g (c' + b) (5 literals, 4 gates) g = a + c
multilevel minimization: substitution and collapsing
b f c
ac g
ac
f b
ca g
key to implementing optimization operations: "division" over boolean functions
f = p q + r
divisor quotient remainder
example:
x = a c + a d + b c + b d + e y = a + b
x "divided" by y : x = y (c + d) + e
multilevel minimization: division
complexity: finding suitable divisors
g does not divide f under algebraic division rules but it does under boolean rules
f = [g (a + c) d] + e
= (a + b) (a + c) d + e
= (a a + a c + a b + b c) d + e
= (a + b c) d + e
= a d + b c d + e
multilevel minimization: “algebraic” and “boolean” divisors
f = a d + b c d + e
algebraic divisors (divide f under algebraic division rules):
d, a + b c
g = a + b
boolean divisors (divide f under boolean-algebra rules):
in general, a function has a very large number of boolean divisors!
