Abstract— Integrated Polarization Converters (PCs) with high (>99%) conversion efficiency open up many new possibilities in an InP-based Photonic Integrated Circuit (PIC). In this paper we describe how such a PC can be added to a circuit containing Semiconductor Optical Amplifiers (SOAs), in order to obtain polarization independent amplification. Polarization independence is obtained by placing the PC halfway between two identical SOA sections. This approach has the advantage that no compromises in design and fabrication are needed. The polarization conversion is found to be very high, above 99.5%, when using a tolerant two section PC. The extra insertion loss due to the converter is below 0.5 dB. The Polarization Dependent Gain (PDG) of the SOA reduces from 17 dB to only 0.3 dB by inclusion of the PC. This is comparable to the best PDG values found in the literature with other techniques. The reduction is achieved over the whole C-band and for varying pump currents.
Index Terms— Indium Phosphide, semiconductor optical amplifier, photonic integration, polarization converter.
I. INTRODUCTION
A polarization converter is a valuable component for photonic integration, since the behaviour of optical waves on a Photonic Integrated Circuit (PIC) depends very much on polarization. In recent years a generic PIC technology has emerged [1], resulting in foundry services that provide optical chips to customers. These foundries allow one to combine passive waveguide structures and active devices (lasers, amplifiers, photodetectors), resulting in complex circuits. However, so far a reliable integrated polarization converter has been lacking. A number of proposals have been made for TE/TM converters [2-10]. The most promising of these to be integrated in photonic circuits seem to be the sloped sidewall single section PCs, which are the shortest and have a relatively easy
fabrication. These converters operate as an integrated optical analogue of a half-wave plate.
Manuscript received MM DD 2015. This work was supported by European FP7 project EuroPIC under grant agreement NMP 228839.
The authors were with COBRA Inter-University Research Institute on Communication Technology, Eindhoven University of Technology, Opto-Electronic Devices Group, P.O.Box 513, 5600 MB Eindhoven, The Netherlands, (e-mail: J.J.G.M.v.d.Tol@tue.nl). M. Felicetti is currently with Infinera (US) and M.J. Wale is part-time with Oclaro (UK).
Copyright (c) 2011 IEEE. Personal use of this material is permitted. However, permission to use this material for any other purposes must be obtained from the IEEE by sending a request to pubs-permissions@ieee.org.
The tolerances to obtain an acceptable level of conversion are however relatively narrow; e.g. in [8] it is found that width deviations should be kept below 50 nm for a conversion efficiency above 95%. In [10] a new two section Polarization Converter (PC) was proposed, with a much improved tolerance and consequently with a high conversion. This device has been experimentally demonstrated [11]. In the current paper we describe how such a polarization converter can be integrated within an optical circuit fabricated on a standard generic PIC process platform. This is done using a post-processing
technique. The integrated circuit aims at providing polarization independence in a Semiconductor Optical Amplifier (SOA). In addition to providing amplification, such a device can also be used for switching/gating and for non-linear functions. An example of the latter is a wavelength converter [12]. For SOAs to operate in a fibre optic network, polarization independence is a prerequisite. Since SOAs are planar devices, often making use of quantum wells or quantum dots as an active medium, TE and TM polarized light usually experience different gains. Furthermore, the use of SOAs in switches and wavelength converters is compromised, since the phase shift and the non-linear response are also polarization dependent. In order to obtain a low Polarization Dependent Gain (PDG), a number of different approaches have been followed. The most common way to reduce PDG is to apply a specific amount of strain to the materials [13]. In this way a PDG in the range of 0.3 dB to 1 dB has been obtained. This technique can however be difficult, and in some cases even impossible, to apply [14]. It also frequently results in compromises with respect to optimal performance parameters of the SOA, since one degree of freedom in the design has to be sacrificed. Furthermore the effective index, and consequently the phase transfer and the non-linear response, are not independent of polarization (see e.g. [15]). An alternative method is the use of on-chip
polarization handling. In [16] a device is presented which uses an averaging solution. The polarization is converted halfway between two SOA sections and hence the polarization properties are averaged out over the two polarization states. This approach avoids the disadvantages of the strain compensation technique mentioned above. Using a polarization converter not only eliminates the PDG, it also compensates polarization effects in phase shift and non-linear effects (like SPM or XPM). This compensation is obtained
Integrated high performance TE/TM Converters
for Polarization Independence in Semiconductor
Optical Amplifiers
Manuela Felicetti, Jos J. G. M. van der Tol, Erik Jan Geluk, Dzmitry Pustakhod, Michael J. Wale,
Member IEEE, Meint K. Smit, Member IEEE
without limiting the design options for the SOA. The performance reported in [16] fell short of typical system requirements, however, with a PDG of several dBs across the whole C-band. The reason for this was the low polarization conversion in the device.
The present paper shows that a high performance polarization converter can be integrated in a PIC to obtain an SOA with very low PDG.
II. POLARIZATION CONVERTER
Polarization conversion can be obtained with a narrow waveguide having an asymmetric cross-section (fig.1). In the converter which will be used here, the tilted modes are obtained with a triangular top cladding. Due to the electromagnetic boundary conditions the angled interface rotates the polarization of the modes. With a careful design the rotation will be 45°. In that case a TE mode from a rectangular shaped input waveguide equally excites the two rotated orthogonal modes. These modes propagate with different propagation constants, β1 and β2. After half of the beat length (Lλ/2=π/[β1- β2]) the rotated modes recombine to a TM mode in a rectangular output waveguide.
Fig. 1. Structure of the polarization converter.
In this way full conversion between TE and TM is possible. Since the device is reciprocal, a full conversion from TM to TE can be obtained in the same way.
As it has been reported in [10], a double section converter can overcome the limited tolerances in fabrication of a single section converter. The tolerant device consists of two PC waveguide sections, whose cross sections are mirrored with respect to each other. In this configuration, the two orthogonal modes M1 and M2 have rotation angles with opposite signs in each section. If the first section has a length of Lλ/4=π/2[β1- β2] the phase angle shift between the two modes is equal to π/2; a second mirrored section with a length of L3λ/4=3π/2[β1- β2], has a −3π/2 phase shift between the modes. This can also be considered as π/2 phase shift, so equal in magnitude to the phase shift in the first section. Therefore the two sections have an equal weight in the polarization conversion. If any error
occurs on the tilt angle of the first section, this will be opposite in the second section, so on average the tilt angle of 45° will be maintained in the full PC device. The total length of the double section PC is twice the length of the single section device. A short waveguide with a rectangular cross section (Bridge) is placed between the two sections to avoid etching issues.
Figure 2: Double section PC with bridge connection.
Fig. 2 shows a scheme of the double section PC with the bridge connection. The bridge connection is a waveguide section with the same width as the PC and a length of 5 μm. This is small enough to avoid any appreciable effect on the conversion efficiency.
Figure 3: PC cross-section. α1 (11º) and α2 (3º) are the etched sidewall angles
of the core and substrate layer respectively. These angles are taken into account in the design of the converter.
The PC cross-section, as obtained with the fabrication process described in section IV, is shown in fig. 3. The structure is 1.05 μm wide (at the topside of the core layer) and gives a single section PC which is 96 μm in length and a double section PC with a total length of 192 μm. The simulated conversion efficiency is 99.99% with an insertion loss below 0.5 dB (@ λ=1550 nm). Fig. 4 shows the comparison between the single section (PC) and the double section (2PC) converter performance in terms of width variation tolerance and
wavelength dependence. The 2PC shows a doubled width tolerance range for more than 95% conversion efficiency and conversion efficiency above 99% over the full C-band.
(a)
(b)
Figure 4: (a) Simulated conversion factor C (%) as a function of the PC width WPC (μm) for the single section PC and the double section PC (2PC). (b) Conversion factor C (%) as a function of wavelength (μm) for the single section PC and the double section PC (2PC).
III. PRINCIPLE OF POLARIZATION INDEPENDENT SOA A polarization independent SOA can be obtained by placing a passive PC between two identical SOA sections. Suppose that a TE polarized mode with power Pin is injected in the circuit; if the PC gives a full conversion (C = 1) from TE to TM and vice versa, the output power Pout is:
Pout = G(TM)G(TE)Pin (1) with G(TE) and G(TM) the gain of the SOA in the TE and TM case respectively. If a TM polarized mode is injected at the input of the circuit, the output power is:
Pout = G(TE)G(TM)Pin (2) Thus, by using a full conversion PC, the circuit gives a signal amplification independent of the input polarization (i.e., assuming that the SOAs are equal and not in saturation). If C < 1, the output power is:
Pout = CG(TM)G(TE)Pin + (1 − C)G(TE)2Pin (3) if the input mode is TE. For TM input the output power is: Pout = CG(TE)G(TM)Pin + (1 − C)G(TM)
2
Pin (4) Thus, in this case, the output power depends on the input polarization and an estimate of C can be obtained from measuring the PDG.
A chip containing several Polarization Independent SOA (PI-SOA) structures, but still without the PC, was designed and fabricated within an InP Multi-Project Wafer (MPW) run [17]. The structures consist of passive waveguides (straight, curved and tapered), formed by etching 4 μm deep trenches on both sides, along with SOAs (see Fig. 5(a)). An unprocessed space of 500 μm is left in order to fabricate the PC afterwards, together with connecting waveguides (Fig. 5 (b)). The SOA is based on a single mode weak waveguide. This weak
waveguide is obtained using a wet etch stop scheme, hence the process depends on the crystal orientation. The weak
waveguide and the SOA need to be defined in the [-110] direction, in order to obtain straight sidewalls [18]. The sloped sidewall of the PC is also obtained with a wet etch, and requires the PC to be defined in the [110] direction.
Figure 5 (a) PI-SOA structure. (b) PI-SOA with the insertion of a PC.
IV. PROCESSING
We have integrated the polarization converter with post-processing on a PIC from a MPW run in the generic
technology platform of Oclaro [1, 17], for testing the converter in a polarisation independent SOA. The PI-SOA chip is the central 4x4 mm2 part of a 12x12 mm2 cell, which facilitates handling during post-processing. The PIC from the MPW run contains structures to apply the PC, with input and output waveguides, in an unprocessed space of 500 μm (Fig.5(a)). The post processing technology [19] has three main challenges:
1. The PIC-PC connection.
2. The protection of the PIC during the post processing. 3. The processing of the PC itself.
a) PC-PIC connection
The connection between the PC and the rest of the circuit is realized with pairs of coupled tapers. The PC is fabricated with tapered input and output waveguides that face tapers on the PIC (Fig. 5(b)). A trade-off between device performance and µ
dimensions leads to the choice of a taper length of 100 μm, tapering from 1.5 to 5 μm, which according to simulations gives less than 0.1 dB coupling loss for two coupled tapers with a 5 µm wide free propagation region in between. b) PIC protection
The post-processing technology [19] starts with the protection of the pre-processed circuit. During the PC fabrication, the PIC should be protected against chemicals used for wet and dry etching of InP. Moreover, the plasma machines, used for deposition, etching and cleaning processes, must be used at temperatures no higher than the annealing temperature of the contact pads of the active components on the PIC. The difficulty in the protection is mostly due to the topology of the chip; since the passive waveguides are 4 μm deep-etched, it is not easy to deposit or spin a material uniformly on the PIC surface in order to protect the waveguide ridges.
A protection method based on photolithography has been developed. This method consists of spinning photo-resist on top of the PIC, which is coated with silicon nitride (Si3N4), and then opening the area for the post-processing using a
photolithography mask.
The chip is then ready for the PC post-processing. This requires first that ZEP electron-beam resist is spun on the chip. This ZEP layer is quite uniform (around 350 nm thick) from the middle of the opened areas to 5 µm away from the PIC tapers (where the ZEP thickness is 400 nm). Thanks to this uniformity the electron beam lithography (EBL) exposure for the PC-definition can be performed with the same dose over the whole opened area. The opening for the post-processing starts 2.5 μm away from the PIC tapers, so the boundaries between the two different technologies fall in the middle of the free propagation region. Since the protection mask has no critical features and the alignment accuracy of the optical lithography is in the order of 0.5 µm, we can easily achieve a good alignment between the optical mask and the PIC. The protection layer is renewed after every dry or wet InP etching step of the PC post-processing.
c) PC processing
The main goal of the technology for the post processing of the PC is robustness against geometrical deviations of the PC shape that can occur during fabrication. Also it is necessary to keep the symmetry between the two sections of the double section converter. This leads to the development of an optimized self-aligned process for the fabrication of the PC. To fabricate the PC together with input and output
waveguides, we used the process flow shown in Fig.6 and described in the following.
a) The fabrication process starts with an InP/InGaAsP/InP layer stack, on which a InGaAs contact layer (500 nm) is grown. A Si3N4/SiO2 passivation layer (260 nm) is present on top of the wafer, as well as a backside metallization of Cr/Pt/Au (205 nm).
b) The Si3N4/SiO2-layer is removed using a CHF3:O2 RIE process, after which the contact layer is selectively wet etched in a solution of 10 H2O: 1 H2SO4: 1 H2O2. The top cladding is lowered to the PC top height (760 ±10 nm above the InGaAsP-layer) with a CH4:H2 ICP plasma. A 400 μm Si3N4 mask layer is then deposited with PECVD, on to which a layer of electron beam resist (ZEP) is spun.
c) In the next step, one of the vertical sidewalls of the PC is defined using EBL, together with input and output waveguides and the waveguide bridge of the double section converter. After exposure and development of the ZEP layer, the Si3N4 mask is dry etched using a pure CHF3 RIE process. A CH4:H2 ICP plasma is used to etch 4 μm deep trenches.
d) A layer of silicon nitride (50 nm) is deposited with PECVD. This deposition is conformal, so that the sidewalls of the etched structures are fully covered.
(a) (b) (c) (d) (e) (f) (g) (h) InP InGaAs SiNO SiN ZEP InGaAsP Cr/Pt/Au
Figure 6: Process flow for the fabrication of the PC. The structures on the left and on the right are mirror images of the PC waveguide cross section, as is used in the double section converter.
e) In the RIE process for etching Si3N4 the direction of the etch is perpendicular to the sample surface and it is therefore possible, by controlling the etching time, to the remove the nitride on top of the mesa, but to keep it on the vertical sidewalls. This allows for etching of the slope in the top cladding with a solution of 4 H3PO4: 1 HCl, using the sidewall nitride as an etching mask.
f) The sample is then covered with a thick layer of Si3N4 (1000 nm) using PECVD.
g) At this point we etch the nitride in a CHF3:O2 RIE process. In the vertical direction the nitride on the slope appears thicker to the plasma than on a horizontal surface. This depends on the slope angle. With 1000 nm of nitride deposited on the
horizontal surfaces the effective vertical thickness on the slope (36º w.r.t. the chip surface) is 1250 nm. Controlling the etching time, the nitride can therefore be completely removed from the horizontal top surface while a thin layer of nitride (around 70 nm) is remaining on top of the slope.
(a)
(b)
Figure 7: SEM pictures of the fabricated chip. (a): double section PC, (b) overview of the PI-SOA circuits.
h) The remaining layer of nitride is used as a mask to etch the second vertical sidewall with a CH4:H2 InP RIE process. The RIE process is highly selective between Si3N4 and the semiconductor, thus it is possible to deeply etch InP (up to about 2 μm).
The remaining nitride is finally removed using a 10% HF solution. Fig.7 shows SEM pictures of the fabricated double section PC device, post-processed on a MPW PIC.
V. EXPERIMENTAL RESULTS
The characterization of the integrated polarization converters is done by measuring the polarization dependence of the transmission through the PI-SOA circuits as a function of wavelength and SOA current.
(a)
(b)
(c)
Figure 8: Difference in transmission for TE and TM inputs (dB), as a function of the wavelength (μm) for 300 μm long SOA sections. (a) Without PC. (b)With the insertion of a double section PC, for different current settings. (c): Comparison with (2PC) and without (no PC) double section polarization converter (30 mA injection current).
Fig.8 (a) shows the polarization dependence of the output power as a function of the wavelength for two 300 μm-long SOA sections without polarization converters. The PDG is between 13 and 18 dB over the C band. The PDG increases as a function of the current, injected in both the SOA sections. PTE -PTM has also been measured in the case of a PI-SOA, consisting of 300 μm long SOA sections combined with a double section PC (Fig.8 (b)). The graph shows the PTE -PTM behaviour for different current settings; in this case, the PDG decreases to 0.05-0.9 dB over the C band. Fig.8 (c) shows that the PDG is reduced dramatically when the PC is placed halfway between two SOA sections; PTE -PTM for λ = 1.55 μm decreases from 17 dB to only 0.35 dB.
Fig.9 (a) shows PTE -PTM as a function of the wavelength for two PI-SOA devices (300 μm long SOAs, 30 mA injected current): one with a double section PC (indicated with “2PC”) and the other with a single section PC (indicated with “PC”). Even though both devices show a low PDG, the double section converter has a much improved performance with a PDG below 0.4 dB over the C band.
(a)
(b)
Figure 9: (a): Comparison between the PDG of a single section PC (“PC”) and a double section PC (“2PC”) PI-SOA (300 μm long SOAs, 30 mA of injected current), as a function of the wavelength (μm). (b): Estimated minimum polarization conversion efficiency C (averaged over the C band) as a function of the SOA injected current (ISOA(mA)), for single section PC (“PC”) and
double section PC (“2PC”).
In Fig. 9(b) the PC conversion efficiency C, averaged over the C band, is shown. This is derived from the measurement results using eqs. 3 and 4, assuming that both SOA section are perfectly identical. Of course the value of C cannot depend on the SOA current, so the fact that the derived value nevertheless varies with different current settings indicates that the SOA sections are not exactly equal. Since unequal SOA sections deteriorate the PDG this implies that the estimate for C is a lower boundary. Thus the polarization conversion must be above 99.5% in the case of the double section PC, whilst it is above 97.5% for the single section PC. This result confirms the superior performance of the double section converter. Comparing test structures with and without a double section PC (with 300 μm long SOA sections), an insertion loss below 0.5 dB for the double section polarization converter has been estimated.
VI. CONCLUSIONS
In this paper it is demonstrated that a high-performance polarization converter can be integrated into a foundry supplied photonic integrated circuit, by using a post-processing technique. This integration is used to obtain polarization independence in a Semiconductor Optical Amplifier (SOA), by placing the converter between two SOA sections. This results in averaging of the relevant properties over the TE and TM polarizations. A very high polarization conversion is obtained (> 99.5%), with less than 0.5 dB extra loss. This was achieved by using a tolerant two-section TE-TM converter. The high polarization conversion resulted in a reduction of the polarization dependent gain from 17 dB to only 0.3 dB over the full C-band.
ACKNOWLEDGEMENTS
The research leading to these results has received funding from the European Community’s Seventh Framework Programme FP7/2007-2013 under grant agreement n° 228839 EuroPIC. The realization of the PC was done in the facilities of NanoLab@TU/e.
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Manuela Felicetti received the M.Sc. degree in electrical engineering in
2009 from Roma Tre University, Rome, Italy. In the same year, she joined the Photonic Integration (PhI) group at the Eindhoven University of Technology (TU\e), The Netherlands, where she received the Ph.D degree (2014). In 2015 she joined Infinera (Sunnyvale, California), where she is currently working as Senior PIC Development Engineer.
Jos J.G.M. van der Tol received the M.Sc and Ph.D degrees in physics from
the State University of Leiden, The Netherlands in 1979 and 1985, respectively. In 1985 he joined KPN Research, where he became involved in research on integrated optical components for use in telecommunication networks. Currently dr. Van der Tol is working as an associate professor at the Eindhoven University of Technology in The Netherlands, where his research interests include opto-electronic integration, polarization issues, photonic membranes and photonic crystals. He is (co-)author of more than 160 Publications in the fields of integrated optics and optical networks, and has 26 patent applications to his name.
Erik Jan Geluk is a member of the technical staff of Nanolab@tue. He is
mostly responsible for the SEM and EBL machines.
Dzmitry Pustakhod received the M.Sc. degree in physics in 2006 from the
Belarusian State University, Minsk, Belarus, and he is currently working toward the Ph.D. degree in the Photonic Integration (PhI) group at the department of Electrical Engineering, Eindhoven University of Technology (TU\e), Eindhoven, The Netherlands. His current research is focused on the development of process control modules for photonic integration technology, which are used for assessment of the fabrication process and measurement of the performance parameters of the building blocks.
Michael Wale is Director Active Products Research at Oclaro, Caswell, with
responsibility for strategic technology development and collaborative programmes. He received his MA and D.Phil. degrees in physics from the University of Oxford, UK, and joined Plessey Research, which evolved into Oclaro, in 1982. He has been responsible for a wide range of activities relating to research and development of photonic devices and their applications and is (co)-author of more than 130 published scientific papers, including numerous invited contributions to international conferences. Mike is Professor at TU Eindhoven and Honorary Professor of Photonic Communications at the University of Nottingham. He is a member of the Executive Board of the European Technology Platform, Photonics21, and chair of its working group on design and manufacturing of optical components and systems. Mike Wale is a member of IEEE and of Optical Society of America.
Meint K. Smit graduated in Electrical Engineering in 1974 and received his
Ph.D. in 1991, both with honours. He started research in Integrated Optics in 1981. He invented the Arrayed Waveguide Grating, for which he received a LEOS Technical Achievement award in 1997 and he was closely involved in the development of the MMI-coupler. Since 2000 he is the leader of the Photonic Integration group at the COBRA Research Institute of TU Eindhoven. His current research interests are in InP-based Photonic Integration, including integration of InP circuitry on Silicon. Meint Smit is a LEOS Fellow.
