Studying DAC capacitor-array degradation in charge-redistribution SAR ADCs

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Studying DAC Capacitor-Array Degradation in

Charge-Redistribution SAR ADCs

Muhammad Aamir Khan, Hans G. Kerkhoff

Testable Design and Test of Integrated Systems (TDT) Group,

University of Twente, Centre of Telematics and Information Technology (CTIT), Enschede, the Netherlands

m.a.khan / h.g.kerkhoff@utwente.nl

Abstract— In this paper, system-level behavioural models are used to simulate the aging-related degradation effects in the DAC capacitor array of a charge-redistribution successive approximation register (SAR) ADC because of the large calculation time of transistor-level aging simulators. A performance-analysis system based on the degraded models has been implemented in the LabVIEW environment in order to study the aging effects in static and dynamic performance parameters. A comparison of results from the degradation in the buffer and comparator with reference to the degradation in the capacitor array has also been conducted. Most of the static and dynamic performance parameters are severely affected by the DAC capacitor-array degradations. Whereas, in case of the buffer and comparator degradations, only offset from the static performance parameters and all of the dynamic performance parameters are severely affected. The simulation results can be used in advance by electronic designers to come to a more reliable design, especially in aging-critical technology nodes.

Keywords- degradation modelling analysis; charge-redistribution SAR ADC; sensitivity analysis; DAC capacitor-array degradation; dependable design

I. INTRODUCTION

The possibility of small-feature sized transistors has made it possible to integrate large and complex systems on a single chip. Being billion-transistor systems, it has become an essential necessity of the electronic industry to use system-level behavioural models [1] for these complex systems design. Electronic designs developed in aging-critical technology nodes even require aging simulations in advance for obtaining a highly dependable design. Simulating aging effects in these large and complex systems at transistor level are very time consuming and even impossible in some cases. This necessitates the use of behavioural models for aging simulations as well.

Aging simulations using device-level (transistor) models are already in practical use [2, 3] and are less time consuming for small circuits like inverters, ring oscillators, and amplifiers. Therefore, one possible way to simulate aging effects in complex systems is to sub-divide the large system into smaller building blocks. First simulate the aging effects for each or at least for more aging critical sub-building blocks and then incorporate the degradation information in the ideal system-level behavioural models to study their effect on the whole system. Another possibility, which is being used in the current paper, is to analyse the performance of the whole complex

system by using a potentially possible set of degraded values in the behavioural models of each sub-building block.

The focus of the current paper is to analyse the degradation effects in the performance parameters of a relatively simple mixed-signal circuit, a charge-redistribution SAR ADC, based on the degraded models of its sub-building blocks. The emphasis will be to analyse the performance degradation as a result of DAC capacitor-array degradation which will be further compared with the results of degradation in the buffer and comparator blocks [4]. For simplicity, the rest of the sub-building blocks will be treated as ideal components. The static and dynamic performance parameters include offset, gain, dynamic nonlinearity error (DNLE), integral nonlinearity error (INLE), signal-to-noise and distortion (SINAD), total harmonic distortion (THD), and effective number of bits (ENOB). They will be analysed as part of the performance analysis for our charge-redistribution SAR ADC.

The rest of this paper is organized as follows. Section II will briefly describe the building blocks of a charge-redistribution SAR ADC, its operational principles, and the degradation modelling in the DAC capacitor array blocks. The important mathematical formulations, used to analyse the static and dynamic performance parameters, the architectural composition of the performance-analysis system, realized in the LabVIEW environment, and the corresponding simulation results will be discussed in section III. The conclusions and some important references are presented in sections IV and V respectively.

II. MODELLING DEGRADATION EFFECTS IN CHARGE

-REDISTRIBUTION SARADC

Successive approximation register (SAR) analog-to-digital converters (ADCs) are among the most widely used ADCs in electronic industry due to their medium digital output resolution, relatively simple architecture and control scheme as shown in Figure 1 [5]. Furthermore, the charge-redistribution (CR) based architecture is among the popular architectures for SAR ADCs due to built-in sample and hold capabilities. Figure 2 shows the simplified circuit diagram of the binary-weighted capacitor array for an N-bit digital-to-analog converter (DAC) architecture, which consists of N capacitors and one dummy capacitor of capacitance C, for an N-bit CR SAR ADC. The latter will be simply referred to as “ADC” in the remainder of this paper

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Fig. 1: Simplified circuit diagram of the charge-redistribution SAR ADC Fig. 2: DAC capacitor array for an N-bit CR SAR ADC

phases; the sampling phase, the hold phase and the redistribution phase in which the actual conversion takes place. During the sampling and hold phase, the analog input voltage is sampled and a voltage equal to the input voltage ��

is provided to the comparator input. Furthermore, if ��,��

and ��,�� represent the offset voltages of the buffer and the

comparator respectively then after the redistribution phase, which takes N-conversion steps for an N-bit ADC, the ideal output voltage of the DAC capacitor array will be the sum of the voltages in the hold phase and in the redistribution phase [4]:

�� ,�� ,�� _��

�� ,��1�

where �� is the sum of the capacitances connected to the ��

terminal and �� is the sum of the capacitances connected to the

ground terminal. The details of the buffer and the comparator offset voltage degradations and their consequence on the ADC performance parameters can be found in [4].

The next step is to model the DAC capacitor-array degradation effects. Metal-Insulator-Metal (MIM) capacitors, being widely used in A/D and D/A converters, degrade as a function of input stress voltage, working stress temperature, and stress time. This degradation could change its behaviour (increasing or decreasing) after a certain amount of time based on the stress conditions [6-9]. For example, in case of SiO2

MIM-capacitors the capacitance increases at a constant stress for a certain period of stress time and starts decreasing after that period of stress time with the same stress conditions. This reversal in MIM-capacitance degradation-behaviour begins earlier at elevated stress temperatures [8]. This means, the change in capacitance of MIM capacitors is a complex function of input stress voltage (��), working stress temperature

(��) and the corresponding stress time (�). This can be

written as:

�� , ��, ��

If we assume that the input stress voltage �� and the

working stress temperature �� are randomly changing

over a specific period of time (e.g. 20 years), then the degradation in each capacitor �� of the DAC capacitor array

will depend on the switching activity of its associated switches S��and S�� (Figure 2), the stress time, the input stress

voltages �� and �� and the stress temperature ��. This

means:

�� S��, S��, ��, ��, ��, ��

Furthermore, the switching activity in the associated switches S�� and S�� for each capacitor �� will further

depend on the input voltage�� that can have any random

value in between zero voltage and the full-scale (FS) voltage values of the ADC (Figure 1). This means, for each capacitor �� the input stress voltage will fluctuate randomly

between��, �� and ground terminal; with �� being another

random value as described above. During the random ON state (S�� is closed) the capacitor �� is connected to the ��

terminal and hence��. Similarly, during

the random OFF state (S�� is closed) the capacitor �� is

connected to the ground terminal and hence�� 0�0�.

This makes the input stress voltage �� for capacitor �� a

random process over the stress time ‘�’. Similarly, if the stress temperature �� is also randomly changing over the stress

time ‘�’ (e.g. 20 years) then at some random points in time the capacitance will increase whereas at other random points in time the capacitance of capacitor�� will decrease [8].

Therefore, a randomly increasing or decreasing degradation in each capacitor ��, as a result of aging, will result in a

randomly degraded ADC, having a different DAC capacitor array, at random points of time during the stress time ‘�’. The randomly changing input voltage �� will decide the random

ON or OFF activity and hence the random input stress voltage

�� for each capacitor �� during the stress time ‘�’.

Similarly, the random working stress-temperature ��

along with the above stress conditions will decide the random increase or decrease in the capacitance of each capacitor ��

during the stress time ‘�’. This can be modelled for each capacitor as a random degradation of its ideal value. Therefore, the value of each capacitor �� in Figure 2 can be rewritten as:

�� /100� � ��

where � � 1�� 0��

�� 1�� 0��

here � is the maximum possible percentage degradation that can occur during the stress time ‘�’ (e.g. 20 years) and can be obtained from the experimental data. The parameters �� and

�� are two independent random number generators that

generate random values between ‘0.0’ and ‘1.0’. The parameter �� can be related to the random amount of degradation in the

capacitance of each capacitor �� at random points of time

during the stress time ‘�’. Similarly, the parameter �� can be

related to the randomly increasing and decreasing degradation-behaviour in the capacitance of each capacitor ��

at random points of time during the stress time ‘�’. Therefore, �� and �� in equation (1) become:

�� ∑ ��

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Table 1: The set of equations that have been used for calculating the static and dynamic performance parameters of the ADC. (Details in [10-12]).

Fig. 3: Block diagram of the ADC performance-analysis system as realized in the LabVIEW environment.

Table 2: Values used for the static and dynamic performance parameters in the ADC performance-analysis system shown in Figure 3.

��

Therefore, equation (1) can be rewritten as:

�� _�_{��}��_��_{��}�� (8)

It is clear from the above equation that the capacitor degradation in the DAC capacitor array and the degradation in the buffer and comparator offset voltages, as a result of aging, will change the voltage value at the comparator input and hence the digital output of the ADC. These degradations in the DAC capacitor array as well as the buffer and the comparator offset voltages have been incorporated in the ideal models. The next two sections will discuss how the degradation as a result of aging will affect the static and dynamic performance parameters of the ADC.

III. THE PERFORMANCE ANALYSIS SYSTEM AND SIMULATION

RESULTS

A performance-analysis simulation setup has been constructed in the LabVIEW environment in order to investigate the degradation effects in the static and dynamic performance parameters of an N-bit ADC as a result of the degradation in some of its building blocks as shown in Figure 3. A well-known and one of the widely used methods for ADC testing, the sine-wave histogram method [10], is used to analyse the static performance parameters. Similarly, a full-scale sine-wave input having a peak value of 2��_{has been}

used to estimate the ADC dynamic performance parameters. Table 1 summarizes the set of equations that have been used in this simulation setup in order to calculate the static and dynamic performance parameters of the ADC [10-12]. Here ��

denotes the total number of samples used in the histogram method whereas ��0� and ��2�_{� �� represent the number of}

hits at the lower and upper codes respectively. Similarly, ��/2

represents the confidence level [12], � the ADC number of bits, and ‘�’ denotes the measured DNLE resolution respectively.

The implemented performance-analysis system has a flexible architecture where parameters like input sine-wave amplitude, frequency, dc level, number of samples, input reference voltage, buffer and comparator offset voltages, ADC number of bits, maximum DAC capacitors percentage error, and different confidence levels for DNLE resolution can be selected by the user. Table 2 summarizes the values that have been used during this performance analysis.

Furthermore, based on (4) and (5), twenty randomly degraded DAC capacitor arrays have been generated, by assuming a maximum of ±0.5% degradation (i.e. parameters ‘�’ in (1)) of their ideal values (2N-1_{C) over the stress time ‘�’}

(e.g. 20 years) as shown in Table 3. This could be an exaggerated value but the idea is to test the system under worst case scenario. The upper ten values have been used for analysing the static performance parameters whereas the lower ten values have been used for analysing the dynamic performance parameters respectively. The reason to use separate values for static and dynamic parameters lies in the fact that it is hard to generate the same random values in the simulation setup because they are randomly generated during the simulations. Simulations have been conducted for each of these ADCs according to the values given in Tables 2 and 3. The output of each randomly degraded ADC is then stored in a memory which is further used to calculate the static and dynamic performance parameters using the equations summarized in Table 1. Furthermore, simulations conducted here are related to aging (temporal) degradations and cannot be extracted based on simple corner analysis techniques.

Figures 4(a), and 4(b) show the offset voltage variation and standard deviation of ten randomly degraded ADCs having degraded DAC capacitor array values (Table 3) as a function of the buffer and comparator offset voltage degradations. It means the change in the offset voltage of each degraded ADC, as a result of the random degradations in the capacitors of its DAC capacitor array, is highly dependent on the buffer and the comparator offset degraded values whereas it has almost a

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Table 3: Degraded values of each capacitor of twenty randomly generated DAC capacitor arrays for analyzing the static (upper 10 values) and dynamic (lower 10 values) performance parameters of ADC.

(b) (c) (d)

Fig. 4: Ten 12-bit CR SAR ADCs, (a) offset variation surface [mV], (b) offset standard deviation, (c) gain variation surface, and (d) gain standard deviation due to

the random degradation of each capacitor in DAC capacitor array as a function of the degradation in the buffer offset voltage (െͳͲ ൑ ୓ୗǡ୆୙୊୊൑ ͳͲ) and the

comparator offset voltage (െͳͲ ൑ ୓ୗǡେ୓୑୔൑ ͳͲ) respectively.

negligible affect from the capacitor degradations (Figure 4(b)). In other words the ADC output offset is highly affected by the buffer and comparator offset degradations and is negligibly affected by the random capacitor degradations in the DAC capacitor array as a result of aging effects.

Similarly, Figures 4(c), and 4(d) show the gain variation and standard deviation of ten randomly degraded ADCs (Table 3) as a function of the buffer and comparator offset voltage degradations. These figures provide the information that contrary to the output offset (above paragraph), the change in the gain parameter of the randomly degraded ADCs is affected less by the buffer and comparator offset voltage degradations whereas it is changed, though very small, as a result of capacitor degradations in the DAC capacitor array. This change in gain parameter of the ADC is proportional to the percentage degradation in the capacitor values due to the aging effects. Therefore, the degradation in the gain parameter will increase as a result of large degradations in the capacitors of the DAC capacitor array.

Furthermore, Figures 5(a), 5(b), 5(c) and 5(d) show the DNL error (DNLE) and INL error (INLE) standard deviation and the corresponding DNLE and INLE mean, minimum and

maximum values of each digital output code for ten randomly degraded ADCs (Table 3). Similarly, Figures 5(e) and 5(f) show the standard deviation of DNLE and INLE values of each ADC as a function of the buffer and comparator offset voltage degradations. The nearly flat DNLE and INLE surface of each randomly degraded ADC in Figures 5(e) and 5(f) show that the degradation in the buffer and comparator offset voltages have almost no effect on the DNLE and INLE values whereas a random capacitor degradation in the DAC capacitor array will lead to severe effects in the DNLE and INEL values. Additionally, the DNLE minimum values (DNLE value = -1) in Figure 5(b) indicates that as a result of random capacitor degradations (Table 3) there will be many missing codes in the digital output of the ADC. Of course the number of missing codes is dependent on the maximum degradation in every capacitor, the reference voltage, and the number of ADC digital output bits. Having smaller values of the reference voltage and higher values of the ADC number of digital output bits will result in even more severe effects in DNLE and INLE values for the same random degradation in the capacitor values. Figures 6(a), 6(b) and 6(c) show the change in SINAD, THD, and ENOBs of ten randomly degraded ADCs (Table 3) -10 -5 0 5 10 -10 -5 0 5 100 0.01 0.02 0.03 Comparator Offset [mV] Buffer Offset [mV] O ffset S ta nd ar d D evi at io n [m V] 0 0.005 0.01 0.015 0.02 0.025

Std. Dev. due to DAC Capacitor Array Degradation

-10 -5 0 5 10 -10 -5 0 5 10 0.999 0.9995 1 1.0005 1.001 Comparator Offset [mV] Buffer Offset [mV] G ai n 0.9994 0.9996 0.9998 1 1.0002 1.0004

DAC Capacitor Array Degradation

-10 -5 0 5 10 -10 -5 0 5 10 4.1 4.2 4.3 4.4 x 10-4 Comparator Offset [mV] Buffer Offset [mV] Ga in S ta nd ar d D ev ia tio n 4.15 4.2 4.25 4.3 4.35 x 10-4

Std. Dev. due to DAC Capacitor Array Degradation (a)

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(a) (b) (c)

(d) (e) (f)

Fig. 5: Ten 12-bit CR SAR ADCs, having different DAC arrays, (a) DNLE standard deviation, (b) DNLE mean, min and max, (c) INLE standard deviation, (d) INLE mean, min and max of each individual digital output code due to the random degradation of each capacitor in the DAC capacitor array, and standard

deviation surface of (e) DNLE and (f) INEL of each ADC as a function of the degradation in the buffer offset voltage (െͳͲܸ݉ ൑ ܸைௌǡ஻௎ிி൑ ͳͲܸ݉) and

comparator offset voltage (െͳͲܸ݉ ൑ ܸைௌǡ஼ைெ௉൑ ͳͲܸ݉) respectively.

as a function of the degradations in the buffer and comparator offset voltage. Similarly, Figures 6(d), 6(e), and 6(f) respectively show the standard deviation of SINAD, THD and ENOB of ten randomly degraded ADCs as a result of the random degradations in each capacitor of the DAC capacitor array. The standard deviation itself shows that the random degradation in the capacitors of the DAC capacitor array has a huge impact on the SINAD, THD and ENOB of the ADC. Similarly, the variation in the standard deviation of SINAD, THD and ENOB of ten randomly degraded ADCs as a result of the buffer and comparator offset degradations show that the buffer and comparator offset voltage degradations also have a severe effect on the dynamic performance parameters of the ADC. This is because of the fact that according to (1) and (8) the comparator offset voltage will try to cancel the buffer offset voltage. However, the DAC capacitor array will introduce some part of the buffer offset voltage at node C (Figure 1). This will saturate the comparator in one direction and will introduce distortion in the actual value. This distortion will further lead to reduction of SINAD, THD and ENOB.

In short, among the static parameters, the offset, and among the dynamic parameters, the SINAD, THD and ENOB, are severely affected by the buffer and comparator offset degradations whereas the static parameters like gain, DNLE, and INLE are minimally affected (almost no effect) by the buffer and comparator offset degradations. On the other hand all of the static, except offset voltage, and all of the dynamic

performance parameters of the ADC are severely affected due to the capacitor degradations in the DAC capacitor array. These results are further summarized in Table 4. Furthermore, Cadence transistor-level simulations are being carried out on a SAR ADC to validate the behavioral models and corresponding static and dynamic performance parameters.

IV. CONCLUSIONS

In this paper, system-level behavioural models have been used in order to analyse the static and dynamic performance parameter degradations of the charge-redistribution SAR ADC as a result of the aging degradations in the DAC capacitor array. Degradation effects of the DAC capacitor array have been modelled and incorporated in the system-level model of the SAR ADC along with the buffer and comparator degradations. These models have been further used in a flexible performance-analysis simulation setup designed in the LabVIEW environment where different input parameters including degradation values of different building blocks can be selected by the user. Simulation results of this setup show that the degradation in the DAC capacitor array has severe effects on almost all of the static and dynamic performance parameters of ADC except the offset voltage. However, the degradations in the buffer and comparator offset voltages have severe effect on the offset, SINAD, THD, and ENOB values. The linearity of the ADC, INLE and DNLE values, is almost not affected by the buffer and comparator offset voltage 500 1000 1500 2000 2500 3000 3500 4000 0 0.5 1 1.5 2 2.5 3 3.5 Digital Code D N LE St an da rd D ev ia tio n [L SB ]

500 1000 1500 2000 2500 3000 3500 4000 -1 0 1 2 3 4 5 6 7 8 9 Digital Code D N LE M ea n, M in a nd M ax [L S B ] DNLE Mean DNLE Min DNLE Max 500 1000 1500 2000 2500 3000 3500 4000 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 Digital Code IN LE S ta nd ar d D ev ia tio n [L S B ]

500 1000 1500 2000 2500 3000 3500 4000 -6 -4 -2 0 2 4 6 8 Digital Code IN LE M ea n, M in and M ax [L S B ] INLE Mean INLE Min INLE Max -10 -5 0 5 10 -10 -5 0 5 10 0.16 0.18 0.2 0.22 0.24 Comparator Offset [mV] Buffer Offset [mV] D N LE S ta nd ar d D ev ia tio n [L S B ] 0.16 0.17 0.18 0.19 0.2 0.21 0.22

-10 -5 0 5 10 -10 -5 0 5 101 1.5 2 2.5 3 3.5 Comparator Offset [mV] Buffer Offset [mV] IN LE S ta nd ar d D ev ia tion [L S B ] 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2

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(a) (b) (c)

(d) (e) (f)

Fig. 6: Ten 12-bit CR SAR ADCs, (a) SINAD variation surface, (b) THD variation surface, (c) ENOB variation surface, of each ADC and (d) SINAD standard deviation, (e) TDH standard deviation, (f) ENOB standard deviation due to the random degradation of each capacitor in the DAC capacitor array as a function of the

degradation in the buffer offset voltage (െͳͲ ൑ ୓ୗǡ୆୙୊୊൑ ͳͲ) and comparator offset voltage (െͳͲ ൑ ୓ୗǡେ୓୑୔൑ ͳͲ) respectively.

Table 4: The effect of DAC capacitor array and the buffer and comparator offset voltage degradations on the static and dynamic performance parameters of the CR SAR ADC.

degradations. The presented technique can be used in advance by system designers for achieving higher system reliability. Furthermore, complicated degradation effects, including non-linear and process variations, can also be incorporated in these system-level degradation models in order to increase the efficiency and accuracy of the simulated results.

REFERENCES

[1] R.A. Rutenbar, G.G.E. Gielen, and J. Roychowdhury, “Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs,” in IEEE Proceedings, Vol. 95, No. 3, pp. 640-669, 2007.

[2] Y. Baoguang, F. Qingguo, J.B. Bernstein, Q. Jin, and D. Jun, “Reliability Simulation and Circuit-Failure Analysis in Analog and Mixed-Signal Applications,” in IEEE Tran. on Device and Materials Reliability, Vol. 9, No.3, pp.339-347, 2009.

[3] E. Maricau, et al., “A compact NBTI model for accurate analog integrated circuit reliability simulation,” in Proc. of the European Solid-State Device Research Conference (ESSDERC), pp. 147-150, 2011.

[4] M.A. Khan, and H.G. Kerkhoff, “Analysing Degradation Effects in Charge-Redistribution SAR ADCs,” in IEEE Int. Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 65-70, 2013.

[5] X. Pei, and P. Wang, “Design and modeling of a 12-bit SAR ADC IP with non-lumped capacitor array,” in IEEE Int. Conf. on Future Computer and Communication (ICFCC), Vol. 3, pp. 392-395, 2010.

[6] M. K. Hota, et al., “Reliability behavior of TaAlOx Metal-Insulator-Metal capacitors,” in IEEE Int. Symp. Physical and Failure Analysis of Integrated Circuits, pp. 803-806, 2009. [7] N. Sedghi, W. Davey, I.Z. Mitrovic, and S. Hall, “Reliability

studies on Ta2O5 high-κ dielectric metal-insulator-metal

capacitors prepared by wet anodization," in Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, Vol. 29, No. 1, pp. 01AB10-01AB10-8, 2011. [8] H. Chi-Chao, et al., “An Innovative Understanding of

Metal-Insulator-Metal (MIM)-Capacitor Degradation Under Constant-Current Stress,” in IEEE Tran. on Device and Materials Reliability, Vol. 7, No. 3, pp. 462-467, 2007.

[9] S.H. Wu, C.K. Deng, T.H. Hou, and B.S. Chiou, "Stability and Degradation Mechanism of La2O3 Metal-Insulator-Metal Capacitors under Constant Voltage Stress," in ECS Meeting Abstracts, Abstract No. 33, April 2010.

[10] T. Hsin-Wen, L. Bin-Da, and C. Soon-Jyh, “A Histogram-Based Testing Method for Estimating A/D Converter Performance,” in IEEE Tran. on Instrumentation and Measurement, Vol. 57, No. 2, pp. 420-427, 2008.

[11] N. Gray, “ABCs of ADCs,” by National Semiconductor Corporation, Rev 3, 2006. [12] http://www.atx7006.com/articles/adc_histogram_test -10 -5 0 5 10 -10 -5 0 5 10 50 55 60 65 70 Comparator Offset [mV] Buffer Offset [mV] S INAD [d B] 52 54 56 58 60 62 64

-10 -5 0 5 10 -10 -5 0 5 10 -75 -70 -65 -60 -55 -50 Comparator Offset [mV] Buffer Offset [mV] THD [d B] -72 -70 -68 -66 -64 -62 -60 -58 -56 -54

-10 -5 0 5 10 -10 -5 0 5 108 9 10 11 Comparator Offset [mV] Buffer Offset [mV] E NO B [BI T] 8.5 9 9.5 10 10.5

-10 -5 0 5 10 -10 -5 0 5 101 2 3 4 Comparator Offset [mV] Buffer Offset [mV] S IN A D S ta nd ar d D ev ia tion [dB ] 1.5 2 2.5 3 3.5

Std. Dev due to DAC Capacitor Array Degradation

-10 -5 0 5 10 -10 -5 0 5 102 3 4 5 6 Comparator Offset [mV] Buffer Offset [mV] TH D S ta nd ar d D ev ia tio n [d B ] 3 3.5 4 4.5 5

-10 -5 0 5 10 -10 -5 0 5 10 0.2 0.3 0.4 0.5 0.6 0.7 Comparator Offset [mV] Buffer Offset [mV] E N O B S ta nd ar d D ev ia tio n [B IT ] 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6