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5. WEIGHT MEASUREMENT
5.4 Analog Devices AD7730
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After comparison of all specifications ( [11], [12] ) the choice was made to use the Analog Devices AD7730 because the measurements will be almost static, an effective resolution of 14 bits suffices and no expensive amplifiers are needed. Further it has some useful features. See Figure 5.4.
The device accepts direct low-level signals directly from a transducer, and outputs serial words via SPI. The input signal is applied to a proprietary programmable gain front end based around an analog modulator.
The modulator output is processed by a low pass programmable digital filter; allowing adjustment of filter cut-off, output rate and settling time.
The part features two buffered differential programmable gain analog inputs as well as a differential reference input.Itaccepts four unipolar analog input ranges (0-10mv, 20mV,40mV and 80mV) and four bipolar input ranges (±lOmV, ±20mV, ±40mV and
±80mV). The peak to peak resolution achievable directly from the part is 220,000 counts. An on-chip 6 bit DAC allows the removal of TARE voltages. Clock signals for synchronising ac excitation of the bridge are also provided.
The serial interface on the part can be configured for three-wire operation and is compatible with micro-controllers and digital signal processors. The AD7730 operates at a clock-frequency between 1 and 5 MHz.
AVoo DVoo REF IN(-) REF IN(+)
VB lAS
AINI(+) AINI(-)
AIN2(+)/D1 AIN2(-)IDO
ACX ACX
IDOnA
MUX1---.----1
MCLKIN MCLKOUT
SCLK
~ DIN DOUT
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As can be seen in the previous figure, the device features:
.:. AC-Excitation
~ For AC-excited bridge applications (see next paragraph) .:. Output Drivers
~ The second analog input channel can become two digital output lines .:. OffsetfTare DAC
~ Allows programmed voltage to be added/subtracted from input .:. Register Bank
~ 13 registers control all functions and provide status-information .:. Serial Interface
~ SPI-compatible .:. Clock-Oscillator Circuit
~ External clock or crystal resonator can be applied .:. Standby Mode
~ This mode reduces power consumption .:. Programmable Digital Filter
~ 2-stage filter that sets the output-update-rate and settling-time .:. Sigma-Delta ADC
~ 24 bits no missing codes, supports chopmode for removing drift errors .:. Differential Reference
~ This facilitates ratiometric operation, the reference is either 2,5 or 5 Volts .:. Programmable Gain Amplifier
~ The amplifier allows 4 uni- and bipolar input ranges from 0 to 80mV .:. Buffer Amplifier
~ Presents a high impedance input stage .:. Burnout Currents
~ 2 burnout currents of lOOnA to detect transducer bum or open-circuit .:. Analog Multiplexer
~ Switches one of 2 input-channels to the buffer-amplifier
5.4.1 Interfacing the weight-bridge
The weight-bridge can be excited in DC or in AC mode.
A common source of unwanted drift effects are parasitic thermocouples, these effects are generated every time there is a junction of two dissimilar metals.
AC excitation addresses many of the concerns about drift and thermocouple effects.
In AC-excitation the polarity of the excitation voltage to the bridge is reversed on alternate cycles. The result is the elimination of DC errors in expense of a more complex system design. Figure 5.5 outlines the connections for an AC excited bridge application.
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The excitation voltage to the bridge must be switched on alternate cycles. Transistors Tl to T4 in Figure 5.5 perform this switching. A special bridge driver chip (Micrell 4427 or Maxim TSC 427) can be used to perform this task.
One of the problems encountered with AC excitation is the settling time associated with the analog input signals after the excitation voltage is switched. The AD7730 addresses this problem by allowing the user to program a delay of up to 48,75~s
between the switching of the ACX signals and the processing of the data at the analog inputs.
Figure 5.5: AC-excited bridge application
When connecting the bridge directly to the ADC the bridge signal will be degraded because of several influences. Examples of these influences are drift due temperature, noise, cross-talk of the line-frequency and clock frequencies on the controller-card. To avoid this a filter is inserted between the bridge and the ADe.
For the static measurement theoretically the cut-off frequency can be very low. A restriction is that the frequency must be higher than the chopping frequency (which is half the output rate).In our case the output rate is 80 Hz.
Inpractice the cut-off frequency has to be much higher in order to obtain an acceptable signal at the input of the ADC with very low attenuation below cut off, therefore a High Pass Filter (HPF) is not applicable here.
The AD7730 has a standard line-frequency rejection of 88 dB, so this is not an issue and the drift is eliminated due to chopping the device, so the only remaining
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5.4.2 Configuration of the AD7730
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Before the actual measurement is performed, the ADC has to be configured to adjust the right settings for the filter, gain, mode and offset. After configuration a calibration should be performed to assure accurate measurements.
The standard procedure is:
1. configuration
2. (self-) calibration (after power-onI reset) 3. measurement
An additional feature of the AD7730 is the check for burnout of the bridge-transducer, this is performed by switching internal current sources, see figure 5.4.1
Configuration of the adc
The first stage filter is a low pass sine3 filter whose primary function is to remove quantization noise introduced at the modulator. By setting SFII-SFO, the amount of averaging, outputrate and cut-off frequency can be programmed.
The outputrates in chop and non-chop mode are determined by the following relationships and a figure of the frequency-response is given below:
-100 -110
-120o 200 400 600 800 1000 1200 uoo 1600 1800 FREQUENCY - H.
Output Rate CHOP
=
fCLKIN 1 Figure 5.6, Frequency response 1slstage filter
(5.11)
Because of noise-reduction it is recommended to use the lowest output data rate as possible. Also multiples of the line-frequency should be avoided because harmonics will not fully be attenuated.
Because the scaling factor SF has range: 2048 - 75 (20 if in skipped mode) and the clock frequency is 4 MHz, the maximum output rate is 1111 Hz (4167 Hz if skipped) The minimum output rate is 41 Hz.
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Notice that the -3 dB frequency is 0.0395 times the output rate, for an output rate of 41 Hz this gives a -3 dB frequency of 1,6 Hz, this is not acceptable for faster
(dynamic) measurements.
The second stage filter is a 22 tap Finite Impulse Response (FIR) filter, this filter processes the output of the first stage filter. The filter has three modes of operation:
Normal, FastStep and Skip mode, which will be explained now.
FIR-mode
Inthis mode the filter acts like a normal 22-tap FIR filter.
The -3dB and stop frequencies are determined by the following relationships and a figure of the frequency-response is given below. Notice that the FIR filter's settling time depends on the output rate.
For non-chopping mode these frequencies have to be multiplied by 3.
(5.12)
Figure 5.7, FIR-filter response
Itis recommended to choose a cut off frequency with certain distance to the line frequency because of aliasing effects.