All-optical synchronous S-R flip-flop based on active
interferometric devices
Citation for published version (APA):
Reis, C., Maziotis, A., Kouloumentas, C., Stamatiadis, C., Bougioukos, M., Calabretta, N., Andrè, P., Dionisio,
R., Neto, B., Dorren, H. J. S., Avramopoulos, H., & Teixeira, A. (2010). All-optical synchronous S-R flip-flop
based on active interferometric devices. Electronics Letters, 46(10), 709-710.
https://doi.org/10.1049/el.2010.1017
DOI:
10.1049/el.2010.1017
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Published: 01/01/2010
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All-optical synchronous S-R flip-flop based
on active interferometric devices
C. Reis, A. Maziotis, Ch. Kouloumentas, C. Stamatiadis,
M. Bougioukos, N. Calabretta, P. Andre`, R. Dionisio,
B. Neto, H.J.S. Dorren, H. Avramopoulos and A. Teixeira
An all-optical clocked set-reset flip-flop is experimentally demon-strated. It is based on a hybrid-integrated S-R latch and two additional Mach-Zehnder interferometer structures with semiconductor optical amplifiers acting as AND logic gates. The switching behaviour of the synchronous S-R flip-flop was investigated and 18 dB extinction ratio performance was achieved.
Introduction: All-optical flip-flops are key elements to perform optical signal processing operations in next generation photonic transmission systems, in particular as buffering memories for temporary storage of decisions in optical packet routers [1]. In the last few years, several approaches have been proposed to realise optical bistable devices. In [2]the proposed scheme uses a single SOA based Mach-Zehnder inter-ferometer (MZI) with a feedback loop, which consists of an interferom-eter containing semiconductor optical amplifiers (SOAs) in both arms, and the energy of set/reset pulses, that change the state of the flip-flop, are highly dependent of the loop delay. In [3] and [4] two coupled laser diodes and SOA fibre ring lasers are used, respectively, in which one of the two lasers is lasing and suppressing the other laser. Most of the optical bistable devices known in the literature do not work with a synchronisation signal, and any change of information in the set/reset inputs is transmitted, immediately, to the output, according to its truth table. In some cases input S and R can suffer unwanted vari-ations and if we are using asynchronous devices, we can be storing unwanted information. Therefore, a clock input signal can be very important to control the enabling of the latch, making it sensitive or not to the values present in the inputs S and R. In[5]an optical synchro-nous S-R flip-flop based on coupled fibre ring lasers was implemented. However, this technology has a serious speed limitation. In this Letter, we experimentally demonstrate the operation of a synchronous S-R flip-flop, with fast switching speeds, high extinction ratio and photonic integration since all building blocks are based on hybrid MZI-SOAs. Experiment: An S-R flip-flop with a clock signal input is shown in
Fig. 1. It consists of a latch S-R and two AND gates to enable the flip-flop by the logical level of the clock signal. In this type of optical bistable device, it is necessary that the clock signal is in the high level so that the information present in the inputs produces effects on the output. S S R R Q latch clock AND1 AND2 50/50
Fig. 1 Scheme of optical clocked S-R flip-flop
Fig. 2shows the setup used for the experimental tests. To generate the set and reset optical pulses, an external cavity laser peaking at 1558.17 nm was used, followed by a polarisation controller and an exter-nal Mach-Zehnder modulator (MZM). The NRZ data sigexter-nal is amplified and split into two equal parts using a 3 dB coupler. Different set and reset patterns are obtained by delaying the signals.
The Boolean logic operations were implemented using integrated SOA-based Mach-Zehnder interferometers and the principle operation relies on nonlinear effects in the SOAs. MZI-SOA1 performs the AND logic function between the reset control signal and the clock signal; MZI-SOA2 performs the AND function between the set signal and the clock signal. Since both AND gates were implemented in a co-propagation configuration, the wavelength of the control signals (set/reset signal) and the incoming signal (clock signal) must be separ-ated wide enough to avoid undesired crosstalk and nonlinear effects such as four-wave mixing (FWM). The powers of the continuous-wave signals (CW) used in MZI-SOA1 and MZI-SOA2 were set to adjust the gain of the SOAs. As can be seen inFig. 2, the outputs of AND1
and AND2 are obtained at the switching ports of the MZI-SOA and they will be coupled into reset and set ports of the asynchronous latch, respectively. The latch S-R consists of two coupled MZI-SOAs, powered by two CW signals at different wavelength and switches between two states (0 or 1) by injecting set and reset optical pulses into the MZI-SOA that is currently dominant. Its principle of operation as well as some experimental results were published in[6].
SOAS 70/30 DFB5 13 dBm 1554.75 nm DFB4 1557.36 nm DFB3 1559.7 nm output AND2 output AND1 DFB6 10 dBm 1550.26 nm BPF3 BPF2 SOA6 70/30 #E #D #F #8 #L #H #1 #3 #2 #7 #7 #6 #1 #2 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/5050/50 50/50 PS1 PS2 SOA1 SOA2 MZI-SOA1 MZI-SOA2 50/50 50/50 50/50 EDFA EDFA EDFA BPF1 MZM PG MZM PG DFB2 13 dBm 1562 nm DFB1 10 dBm 1558.17 nm 50/50 50/50 50/50 latch S-R S0A4 S0A3 PS4 PS5 PS6 PS3 EDFA output Q EDFA
Fig. 2 Experimental setup
The truth table of the clocked S-R flip-flop is the same as the S-R latch but only when the clock signal remains at high level (CLK ¼ 1). If CLK ¼ 0, the flip-flop maintains its previous state (last Q).
The output signal from the clocked S-R flip-flop was filtered, ampli-fied by an EDFA and analysed by an oscilloscope (Agilent 86100C), connected through a pin photodiode.
Results: The experimental results of the clocked S-R flip-flop are pre-sented inFig. 3. The input set and reset signals have a repetition rate of 40 MHz with a pulse width of 2 ns and are delayed by 11.6 ns. The pulses energies are set to be 100 pJ. The clock signal has a repetition rate of 300 MHz with a pulse width of 1.67 ns.
a b
c
d
e
Fig. 3 Experimental results
Vertical scale is arbitrary and horizontal scale is 5ns/div. forFigs. 3aand b and 10 ns/div. forFigs. 3c– e
a Clock signal b Reset signal
c AND2 optical gate (set > clock) d AND1 optical gate (reset > clock) e Optical clocked S-R flip-flop output
Fig. 3cdemonstrates the logic AND function between the set and clock signals and an optical pulse will be obtained at the output only in the case that both data signals are equal to 1. Fig. 3d shows the AND operation between the reset signal and the clock signal. The clock signal and the control set/reset pulses were launched only in one of the two arms of the MZI-SOA and after balancing we achieved an extinction ratio (ER) of 36 and 25 dB in SOA1 and MZI-SOA2, respectively.
InFig. 3eit is possible to distinguish the two different stable states of the flip-flop and it is very noticeable that the inputs of the S-R flip-flop are transferred to the Q output only when the clock signal is enabled.
We achieved switching speeds of 430 ps and 420 ps for rise time and fall time, respectively. We also analysed the performance of the synchro-nous S-R flip-flop and 18 dB of extinction ratio was obtained.
Conclusion: A novel scheme for an all-optical synchronous S-R flip-flop, based on MZI-SOAs, has been presented. We have demonstrated that the clocked S-R flip-flop dynamically changes its state only when the clock signal is enabled, which allows the flip-flop to work as a finite state machine. We achieved 18 dB of extinction ratio and switch-ing times less than 450 ps.
Acknowledgments: This work was supported by the EURO-FOS project and by the Portuguese Scientific Project PANORAMA (ADI 2009/ 003144).
#The Institution of Engineering and Technology 2010 15 April 2010
doi: 10.1049/el.2010.1017
One or more of the Figures in this Letter are available in colour online. C. Reis, P. Andre`, R. Dionisio, B. Neto and A. Teixeira (Instituto de Telecomunicac¸o˜es, Campus de Santiago, Aveiro 3810-193, Portugal ) E-mail: creis@av.it.pt
A. Maziotis, Ch. Kouloumentas, C. Stamatiadis, M. Bougioukos and H. Avramopoulos (School of Electrical and Computer Engineering, National Technical University of Athens, 9 Iroon Polytechniou Street, Zografou, Athens 15773, Greece)
N. Calabretta and H.J.S. Dorren (Eindhoven University of Technology, Eindhoven, MB 5600, The Netherlands)
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