Design of EMI-Suppressing Power Supply Regulator for Automotive electronics

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MICAS Department of Electrical Engineering (ESAT)

Design of EMI-Suppressing Power Supply Regulator for Automotive electronics

October 11th, 2006

Junfeng Zhou

Promotor: Prof. Wim Dehaene

KULeuven ESAT-MICAS

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Part I: Introduction

Part II: Low Noise Power Supply–EMI-Suppressing Regulator

• Principles

• Design

• Simulation

• Calculation

• Chip Details

• Measured Results

Part III: Possible Improvements Part IV: Future work

Outline

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Part I: Introduction



Electro-Magnetic Interference (EMI ( EMI ) and radiated emission ) radiated emission have become a major problem for automotive electronics,



Radiated emission is mostly a consequence of di/dt di/dt ^{on the}

supply lines.



Although the detailed calculation of EMI noise is rather difficult , we can use the di/dt di/dt as the index, since the current loop

contributes the EMI.

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Part II: EMI-Suppressing Regulator

Previous research on Low Noise Logic Families shows that 2 major problems still remain:

• Static power consumption

• New logic family standard cell library must be

designed and characterised. (large NRE cost, risk)

? Any global approach ?

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Diagram of EMI-Suppressing Regulator

1. Current source 1. Current source

ensures the ensures the major di/dt major di/dt

reduction reduction 2. Slow varying 2. Slow varying

is key to EMC is key to EMC success

success

3. Minimize the Minimize the static current static current

Principles

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EMI-Suppressing Regulator – basic structure

Determine the switching speed, Determine the switching speed,

Hence determine the di/dt Hence determine the di/dt

Energy reservoir

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Why new structure ?

1. Simple 1. Simple

2. Driving capability 2. Driving capability 3. Miller effect on 3. Miller effect on

compensation compensation capacitor

capacitor

4. Cascode device 4. Cascode device

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Functionality Simulation &

Comparison with standard CMOS

di/dt and FFT comparison with standard CMOS

w/o EMI-SR and SR

I

_Vbat

I_Vbat: di/dt ^p-p = 1.0x10⁷ A/s

w/o EMI-SR and SR, di/dt ^p-p =1.51x10¹¹^A/s

44dB

PSD comparison

di/dt comparison

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Maple calculation

[ / ] di A s dt

[ ]s

An input current step of 1 mA and 100-ps rise time was used for the calculation and simulation

10 ( / )

7

di A s

dt 

[ ] I A

[ ]s

di/dt I

stimulus

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Stability analysis

Approximation Approximation : :

1 - * 1

2 - 1

tan

*(1 )

3 - 1

* 1

1 - *( 1- )

1 1

1

2 ( 1 )

* tan p Gota

Caux Av gm Gload

p C k

Gaux Caux p Cgs

Caux Gaux gm Z Caux gm Gaux

Av gm

Gds Gload

p gm Gload Caux

GBW Gm C k



 





 

  p1

p2 p3

z1

>3 for > 72° phase margin

Stability ~ C

_aux

/C

_tank

p4

i i

_in_in

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Stability analysis – Simulation vs.

Calculation

Spectre simulation Spectre simulation

Maple calculation Maple calculation

Raux=1.852K , Caux=20p,Ctank=100p

Stability vs. Iload

φ>72°

Iload =192.7u A

Stability vs. Iload (26.7u A ~ 72m A) Stability vs. Iload (26.7u A ~ 72m A)

φ ≥60°

Worst case

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Current TF analysis

1

2 1

tan

* ( 1 )

3 * 1

p Gm

Caux

p gm

C k

Gaux Cgs Caux

p Caux Cgs

 

  

* * 1

1 * * 1 * * 1 1* * * 1* 1 * 1*

* * 1 * * 1 1* * * 1* 1 * 1*

2 * 1*( 1)

Gaux Gm gm

Z Gaux Caux gm Gm Caux gm Cgs Gm Gaux Gaux Gds Cgs Gaux Gds Caux

Gaux Caux gm Gm Caux gm Cgs Gm Gaux Gaux Gds Cgs Gaux Gds Caux

Z Caux Cgs Gaux Gm Gds

     

    

   

H(s)=I

_VDD

(s)/I

_in

(s) (i.e. di/dt attenuation)

dominant pole

second pole

third pole

High frequency zero

left half-plane zero

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Current TF- simulation vs.

calculation

Spectre simulation Maple calculation

Iload =80u A, Raux=1.852K , Ctank=100p

( ) ( )

( )

VDD in

I s

H s  I s

( ) ( )

( )

VDD in

I s H s  I s

dB

- 44 dB - 44 dB - 43 dB

- 43 dB

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Maximum Attenuation

Maple calculation Maple calculation

Iload =800u A, Raux=1.852K , Ctank=100p

TF vs. Caux

1

1 tan

1 lim ( ) ( )

( )

VDD db

s in db k

p Gm

Caux

I s C

H s I s C C



 

  



Cut-off freq. ~ 1/Caux Large attenuation

requires Large Ctank and/or small Cdb1

Cascode structure !

dB

- 40 dB - 40 dB

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Caux/Ctank and ∆V _DDinput

∆VDDinput Caux = 4, 8, ..20 pF Caux = 4, 8, ..20 pF

∆ ∆ V V

DDinput_DDinput

~ C ~ C

_aux_aux

/C /C

_tank_tank

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Design Strategy

 EMI-Suppressing Regulator design principles EMI-Suppressing Regulator design principles



Stability ~ C Stability ~ C

_aux_aux

/C /C

_tank_tank



Time domain ∆V Time domain ∆V

_DDinputDDinput

~ C ~ C

_aux_aux

/C /C

_tank_tank



More stable also means a larger ∆V More stable also means a larger ∆V

_DDinput_DDinput



Current TF Current TF



Cut-off freq: Gm/C Cut-off freq: Gm/C

_aux_aux



Max. attenuation: C Max. attenuation: C

_db_db

/(C /(C

_db_db

+C +C

_tank_tank

) )



Design for small C Design for small C

_db_db

 Similar story possible for Similar story possible for Gm, g Gm, g

_m_m

 Caution should be exercised to maintain the stability of the Caution should be exercised to maintain the stability of the

EMI-suppressing regulator while designing for higher di/dt reduction EMI-suppressing regulator while designing for higher di/dt reduction

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EMC test chip with

EMI-Suppressing Regulator

SR1, MS-FF, No capa SR2, MS-FF, 1/2 PNMOS capa

SR3, MS-FF, PNMOS capa SR4, MS-FF, PNMOS capa, PWR SR5, MS-FF, PNMOS capa, MIMC capa

SR6, D-FF, No capa SR7, D-FF, 1/2 PNMOS capa

SR8, D-FF, PNMOS capa SR9, D-FF, PNMOS capa, PWR SR10, D-FF, PNMOS capa, MIMC capa

On-chip LDO

PD

On-chip Serial regulator

PD

SR1 RST Din CLK OUT

GND LDO

PD

EMI regulator

Ctank

VDD_input

Emergency block

Power down block

V3v3

Vbat

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Current source simulation results

[ ] I mA

[ ] V v

I

_Vbat

V3v3

VDD_input Vctrl

[ ] V v

Power down enable

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Frequency simulation results

current of Vbat

di/dt ^p-p =8.5x10⁴ [A/s]

9x10⁶

load current of digital core

FFT FFT

di/dt ^p-p =1.8x10⁹ [A/s]

7x10³

di/dt of Vbat di/dt

of V3v3

40dB (EMI regulator) + 20dB (Serial regulator 40dB (EMI regulator) + 20dB (Serial regulator) )

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Chip Details

EMI

Suppressing regulator

Area: 1mm x 1.1mm

C_tank =100p F C_aux= 20 p F

Power transistors: Wp=5000 μm Lp= 1 μm (fixed) Technology

: AMIS 0.35μm I3T80

Supply voltage

: 12 V

Output voltage

: typ. 8V, min.5.5V

Quiescent current

: 30 μA

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Measurement Setup

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Measured Results (1)

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Measured Results (2)

Load transient response

I

_load

(0 mA ~ 20 mA ) V

_out

10 ns

8 V

5.78 V

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Measured Results (3)

Peak : ~ 5x

T

rise

: ~ 7x

di/dt

_peak

: ~ 24x

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Measured Results (4)

Peak : ~ 9x

T

rise

: ~ 12x

di/dt

_peak

: ~ 18x

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Measured Results (5)

di/dt TF di/dt TF

I I

_AC_AC

injected injected

-3dB: 1.6 MHz

-33 dB

di/dt TF di/dt TF

I I

_AC_AC

injected injected

-3dB: 1.8 MHz

-35 dB

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Conclusions

A Low Noise Power Supply Techniques A Low Noise Power Supply Techniques is presented: is presented:



Control the way Control the way the current delivered to the internal digital core, the current delivered to the internal digital core, hence keep the EMI under control,

hence keep the EMI under control,



Comparable reduction on di/dt noise with low noise digital cells Comparable reduction on di/dt noise with low noise digital cells only,

only,



More power efficient More power efficient than the low noise digital cells, than the low noise digital cells,



Have similar power consumption Have similar power consumption to the conventional CMOS logic, to the conventional CMOS logic,



A global approach- A global approach- Can be adjusted to a wide range of chip size Can be adjusted to a wide range of chip size and power consumption level,

and power consumption level,



Measurement results match the simulation well. Measurement results match the simulation well.

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Part III: Possible Improvements

Frequency

H(s)-dB

peaking

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• 

_z1

– G

m

/C

aux

• 

_z2

– parasitic zero, high frequency

• 

_p1

– Pole at V

_ctrl

: G

_m

/C

_aux

• 

_p2

– Pole at V

VDD_input

: g

m

/C

tank

• 

_p3

– pole caused by compensation path, high frequency

Current TF: small signal model

   

  

^z1

 

^z2



VDD

noise p1 p2 p3

1 + sω1 + sω I (s)

I (s)  1 + sω1 + sω1 + sω

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• _z1 cancel off the _p1

• Make the _p2 cut-off frequency

• This zero is intrinsic for this feedback topology

sacrifices dynamic noise performance

• Make Make _p2_p2 dominant dominant

• Advanced compensation techniques Advanced compensation techniques needed

needed

Current TF: pole-zero tracking

Frequency H(s)-dB



_z1



_p1



_p2

peaking

Options

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• Key Idea :

Achieving Stability Without Sacrificing Dynamic Supply Current Rejection

• R-C compensation

• Reduced Gm of OTA

• R

_eq

added for moving the output pole high frequency, also for improvement of the dynamic di/dt rejection

Possible solution

V_ref -

+

R_Load

C_tank Vctrl

VDD_input C_aux

Mp

R_aux OTA

“ Req”

+ -

Vbias

VDD_input

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Current TF analysis

• 

_p1

–

• 

_p2

–

• 

_z1

–

• 

_z2

–

high frequency

   

 ^z1 ^z2

VDD

noise p1 p2

1 + sω1 + sω I (s)

I (s) 1 + sω1 + sω

( )

m m

aux m m aux eq

g G

C g G R G



   

tan

m m aux eq

k

g G R G C

  

( )

m m

aux m m aux

g G

C g G R



  

1

m m aux

O db

g G R

r C

  

R

_eq

makes 

_p1

and 

_z1

well separated

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Current TF--Simulation results

C_tank: 100p I_load:

20uA~2m A G_m : 4uA/V R_C: 1K

C_aux: 20p F R_aux: 100 K 632.5 uA

20 uA

63.25 uA 200 uA

TF vs. I

_Load

2 mA

-3dB

Peak

Freq

_-3dB

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Part IV: Future Work

 Extend the TF measurements into higher frequency,

 Find a way to linearly inject the AC current,

 Characterization & quantification of EME from digital circuits,

 Prediction of EME of digital circuits,

 Spread spectrum clock generation.

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Design of EMI-Suppressing Power Supply Regulator for Automotive electronics