Switching Theory / Schakeltechniek 5A050
Lab session Optimization
Highlights previous session
B0 01 1 A0 01 1
S0 11 0
C0 00 1
S = AB + AB C = AB
truth table
Boolean expression
implementationgate
A B
S
design trajectory C
testing
representations
Highlights previous session
• Expressions and gate implementations not unique
– optimization possible– Boolean-algebra domain
• Manipulation of Boolean expressions
– not systematic: intuition required – unclear when optimality is achieved – gives insight in digital circuitsFrom truth tables to gates
… An… 0
… 1 A00
0. ..
X0 1. ..
X = A0…An + … A0An
X truth table expression gate implementation
... ...
product: minterm expression: sum-of-products (SOP)
gate implementation: 2-level
• disadvantage: size
(gates with many inputs + large number of gates)
• advantage: timing
(all signals travel through exactly 2 gates)
2-level optimization: goal
B0 01 1 A0 01 1
X0 01
1 AB + AB = A(B+B) = A • 1 = A A
B
X
X
A optimal
2-level implementation Goal: find the smallest possible 2-level implementation
2-level optimization: basic idea
B0 01 1 A0 01 1
X0 01 1 A
B
X
AB + AB = (A+A)B = B
X B
• look in the truth table for 2 lines where 1 variable changes and both with 1 outputs
• eliminate this changing variable
• implement the 2 lines with 1 (sometimes 0) AND-gate
2-level optimization: cubes
• every k-dimensional plane represents one AND
• method useful up to three variables A0
00 01 11 1
B0 01 01 01 1
C0 01 01 01 1
X0 00 11 11 1
A BC
X X = A + BC
000 100
110 011 111
010 001 101
A B
C 1 in truth table
BC
A
AB AB A
AB AB B
2-level optimization: Karnaugh maps
• 2-dimensional method
• useful up to four to six variables
neighboring elements:
• differ in one variable
• neighboring 1s can be combined, eliminating the variable that changes value
X = A + B A
B X:
1 1 1
B0 01 1 A0 01 1
X0 11 1 alternative representation
of truth table
2-level optimization: Karnaugh maps
• combined neighbors can be neighbors again
• rule of thumb:
elliptic groups of 2n ones can be combined (implicants)
• biggest such groups are prime implicants
• look for a minimal set of prime implicants
• gives the smallest possible 2-level SOP expression / gate implementation
A
B X:
1 1 1 1
1
C
X = A + BC ABC
ABC AB
ABC ABC
AB A
Karnaugh maps: 4 variables
A
B X:
1 1 1 1
1
C 1 1 D 1
AB C
B X
A C B D A D
Karnaugh maps: borders
A
B 1
C 1
D ACD
upper and lower border connected
A
1 B
C
1 D
CD
1
left and right 1
border connected
Karnaugh maps: corners
A
B 1
C
1
D
1 1
connection via upper and lower border
and via
left and right border
C D
Example: 3 variables
A0 00 01 11 1
B0 01 01 01 1
C0 01 01 01 1
Z0 01 01 11 1
C AB
Z Z = AB + C
A
B Z:
1
1 1 1
1
C
smallest possible 2-level SOP implementation
Example: 4 variables
1 B 1 1 1 1
C 1 1 D 1
1
1
A
1 B 1 1 1 1
C 1 1 D 1
1
1
A A
1 B 1 1 1 1
C 1 1 D 1
1
1 Find the smallest
possible SOP expression for the following K-map
essential prime implicants 1 B
1 1 1 1
C 1 1 D 1
1
1
A
CD + CD + BC CD + CD + BD
2-level optimization: recipe
• (Give a truth table)
• Fill out K-map
• Cover all 1s with prime implicants
– find all essential prime implicants – find a minimal set of prime implicantscovering remaining 1s
• Create a SOP expression
– Deduce a product term from each of the selected prime implicants
– Take the sum of these product terms
Example
Reduce the following expression as much as possible:
AB + BC + AD + CD + AB + BC
1 1
1 1 1
1 1
1
1
1 B
C D
A
1 1
B 1 1 1
1 1 1
C 1 1 D 1
1
1 A
1 1 1
AB + AC + BD + BC no essential prime
implicants !
Don’t cares
• Some A,B,C,D input combinations cannot occur
• Those combinations are don’t cares
• Designer may choose output for those combinations
• Gives freedom for further reduction of circuit
circuit to be designed A
B C D some given X
circuit
Don’t cares: example
• Don’t cares are denoted with x’s
• Generation of prime implicants: consider x as 1
• Select minimal set of implicants covering all real 1s
• Consider uncovered x-s as 0
A
B X:
x
1 x x
x
C 1 1 D 1
1 1 1
1 1
A
B X:
1
1 1 1
0
C 1 1 D 1
1 1 1
1 1 X = A + B
Multi-level optimization
ADF + AEF + BDF + BEF + CDF + CEF + G
(A + B + C)(D + E)F + G
• often smaller circuits (less and smaller gates)
• often slower (some signals must go through > 2 ports)
• unstable timing / glitches
• unfortunately NOT exact
