Efficient estimation of die-level process parameter variations via the EM-algorithm

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Efficient estimation of die-level process parameter variations

via the EM-algorithm

Citation for published version (APA):

Zjajo, A., Krishnan, S., & Pineda de Gyvez, J. (2008). Efficient estimation of die-level process parameter variations via the EM-algorithm. In Design and Diagnostics of Electronic Circuits and Systems 2008, DDECS 2008, 11th IEEE Workshop 16-18-04-2008 (pp. 1-16) https://doi.org/10.1109/DDECS.2008.4538804

DOI:

10.1109/DDECS.2008.4538804

Document status and date: Published: 01/01/2008 Document Version:

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Efficient Estimation

of Die-Level Process

Parameter Variations

via

the EM-Algorithm

Amir

Zjajo',

Shaji

Krishnan',

Jose Pineda de Gyvez'2

'NXP

SemiconductorsResearch, HighTechCampus 37, 5656 AEEindhoven, The Netherlands

2EindhovenUniversity ofTechnology,DenDolech2, 5612 AZEindhoven,The Netherlands e-mail: amir.zjajo@nxp.com

Abstract- A new approach for efficient estimation of die- deletion and structural equation modelling [8] would level process parameter variations based on the expectation- provide us with estimates of the selected performance

maximization algorithm iS

parimizamete andorenhanc diagnostiean.

proposed. To estimate_ls

_dedicated

the

t

figures (from

the

incomplete

data),

imputation

method and

embedded sensors have been designed. Additionally, to guide its special case, multiple imputationsbased on

expectation-the test with expectation-the information obtained through monitoring maximization (EM) algorithm [9-10] offers maximum

process variations, maximum-likelihood method and adjusted likelihood estimates ofparameters in probabilistic models, support vectormachine classifier isemployed.The information where the model depends on latent variables. The proposed

acquired is re-used and supplement the circuit calibration. The estimation method is evaluated on an

analog

to digital

proposed estimation method is evaluated on aprototype ADC

converterwith dedicated sensors fabricated in standard single converter (ADC) as the appropriate representative. Since

poly, fivemetal0.09-tmCMOS. functional fault in each of the analog component in the

multi-stepADCaffects the transfer functiondifferently [ 1],

I. INTRODUCTION analyzingthis property form the basis of our approach.

CMOS technologies move steadily toward finer

geometries, which provide higher digital capacity, lower II. MULTI-STEP ADC

dynamicpowerconsumption and smaller area, which results

inintegrationof whole systems, orlargepartsof systems, on A Multi-Step ADCArchitecture

the same chip. However, dueto technology scaling ICs are The input signal is sampled by a three-times interleaved

becoming

more

susceptible

to variations in process sample-and-hold (S/H), eliminating the need for re-sampling parameters and noise effects like power supply noise and of the signal after each quantization stage. As shown in cross-talk reduced supply voltage and threshold voltage Figure 1,the S/H splits and buffers the analogue delay line

operation. Likewise, imperfection at the manufacturing sampled signal that is then fed to three A/D converters stage, with a rawfactory yieldbetween 50-95%, depending (ADCs), namely, the Coarse (4 bits), the Mid (4 bits) and

onthematurity of the process technology, silicon area, and the Fine (6 bits). The quantization result of the Coarse A/D

extending the use of 193nm lithography for sub-65 nm converter is used to select the references for the mid CMOS technology, where Resolution Enhancement quantization in the next clock phase. The selected references

Techniques are no longer sufficient for accurate device are combined with the held input signal in dual-residue

definition, significantly impact circuit performance. With amplifier, which is offsetcalibrated [12-14]. increased system complexityand reduced access to internal

nodes,the task ofproperly testingthese devices isbecoming referenceladder a major bottleneck. The large number of parameters

_..

required to fully specify the performance ofmixed-signal

circuits and the presence of both analog and

digital signals

Iidthermo[16:0]m

in these circuits make the

testing expensive

and a time

consuming task.

Particularly

for nanometer CMOS

ICs,

the g

L|ta

largenumber of metallayerswithincreasing metaldensities,

preventsphysicalprobing of the signals for debugpurposes. | d

Since

parameter

variations

depend on unforeseen

operational conditions, chips may fail despite they pass

standardtest

procedures.

_

To enhance observation of

important

design

and

technology parameters, such as temperature, threshold dig.-t

voltage,

etc.,

dedicated sensors are_{' '.} embedded within the_. _. _. _{~~~~~~~~~~~~Figure}_{1: Block diagram of the}_{Multi-step ADC and part of the test control}

functional

cores [1-3]. To

guide

the test

with

the

information

circuitry. Obtained through monitoring process variations, we

employed maximum-likelihood method and adjusted The MidA/D converter quantizes the output signals of these support vector machine (SVM) classifier [4-5], since it mid-residue amplifiers. The outputs from both coarse and simultaneously minimize the classification error and mid A/D converters are combined in order to select proper maximize the geometric margin. Although, in statistics references for the fine quantization. These references are several methods, such as listwise [6] and pairwise [7] combined with the sampled input signal in, also offset

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calibrated, dual-residue amplifier. The amplified residue C DedicatedSensors

signals are applied to a Fine A/D converter. In multi-step

ADC, high linearity is obtained by extensive usage of To illustrate the concept of Die-level process monitors correction and calibration procedures. Providing structural (DLPMs) [3], consider only the Coarse ADC, which is a DfT and BIST capabilities to this kind of ADCs is difficult simple four bit flash stage as shown n Figure 2,

consisting

since theeffects ofcorrection mechanism must be taken into of reference ladder and sixteen comparators. From the

ainccunt.

Oerlapo borrectweeteion

rechanitanges ontwo

one can conclude that the

gain,

decision

sagesunthverlto

betonsidered,ooterwise theres

may e and referenceladderarecrucialtothe proper Coarse ADC's

stages have to be

considered, otherwise,

there may exist promne ommcteDTbhvo,tegi-ae

conflicting operational situations that can either mask faults performance To mimic the DUT behavior, the

gain-based

orgive an incorrect faultinterpretation. DLPM and decision stage-based DLPM are extracted

or

gieninoretautinerrtaio(replicated)

from that

particular

part

of the DUT

[3].

The

DLPM measurements are directly related to asymmetries

B. Multi-StepADCerrorsources between the branches composing the circuit, giving an

The staticparameters are determined by the analog errors estimation of the offset when both DLPM inputs are

in various ADC components and therefore, a major grounded or set at predefinedcommon-mode voltage.

challenge in ADC test is to estimate the contribution of VDD

those individual errors to the overall ADC linearity

parameters. The overall

A/D converter consists primarily of (D T3 T5

T6

T4

E

non-critical low-power components, such as low-resolution 5 a) l

quantizers, switches and open-loop amplifiers. If timing O errorsarenot considered, the primary error sources present in a multi-step ADC are decision stage offset errors (i),

stage

gain

errors

(a),

and errors in the internal reference l

voltages (y). Each of the these errors is the combined result ...6...I.

of two physical effects: noise, which includes charge injection noise in analog switches, thermal, shot and flicker

noise, and noise coupled from digital circuitry (via crosstalk G l

or substrate), and on-chip process parameter variation, e.g.

device mismatch. The offset errors include offset caused by Figure3:Stage gain-basedDLPM schematicview.

either component mismatch, self heating effects, comparator

hysteresis or noise. The gain error group includes all the Asshownin Figure3, thegain-basedmonitorconsists

ofthe

errors in the amplifying circuit, including technology circuitry replicated from the observed ADC gain stage, variations and finite gain and offset of the operational which consists of a differential inputpair(transistors T1 and

amplifier. The reference voltage errors are caused by T2) with activeloading(T3 andT4)andsomeadditional

gain

resistor ladder variations and noise, as well as to errors in (transistors T5 andT6)to increase theDLPM resolution and the switch matrix, which are mainly due to charge injection transistors T7 and T8 to connect to read lines

(lines

leading

inthe CMOS transmission gate. to a programmable data decision

circuit).

Similarly,

in the

proposed decision stage monitor circuit (Figure 4) the latch

DIE (transistors T12 to T17) has been broken to allow a DC

_ ...current flow through the device needed for the intendedset

i +Sensor I' ~~~~~~Sensoro _of_{measurements.}

u s l

| |

t

~~~~~~~ro

2 VDDcess1S3

F

,r

_;

_

/

~~~~~~~~~~~~~~~~~~~gradientl

ll

I

~

~~

g

OS

DUT ~~~~~~~~~~T1T1_

.A

11 1l Figure 4: Decision stage -based DLPM_{T10n1 T1111l-W_lZi} _, schematictview.

lg ;=111_li 1A11 '

11monitoring

circuit as shown in Figure 5 sense the

.S. W *

.s~

mismatching between two of the unit resistors used in the

actual resistor ladder design. The current that flow through Figure 2: Coarse ADC withbuilt-in sensors. the resistors (whose values are extracted from the ladder

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itself) is fixed using a current mirror. Since the current is When a measured parameter distribution on-chip (Figure 6) fixed, the voltage dropbetween the nodes labeled V1 and V2 is derived, next step is to update high and low limitvalues is a measurement of themismatching between the resistors. by adjusting the support vector machine (SVM) classifier The chosen current mirror topology is reliable enough to [4-5] (Figure 7) in thecorresponding functional test specs of neglect the possibledeviations due to transistor mismatch. the device undertest.

ol ~~VDD 0

lMAILSAL

I i.H O osL \ \o@I£I

e = X 1 2 1 j 10RiER(I0.

0~~~~~~~~~~~~~~~~~~~~~~0

0.3 0

0.1 0.2 0.3 04 05 06 07 08 09 LSB

Figure 5: Internal reference voltages-based DLPM schematic view. Figure 6: Contour plot of thedistribution function of multiple runs of DLPM and DUT measurements derived through the Maximum-Likelihood

By extracting the DLPM circuit from the DUT itself, the method. DLPM circuit accomplishes some desirable properties: i) it

is designed to maximize the sensitivity of the circuit to the Let fxQ Rn - R be a discriminant function trained from target parameter to be measured, ii) it matches the physical the data Txy4. The parameters 0 of a posteriori distribution py layout of the extracted device under test, iii) it is small and 0F(yJ(X), 0) of the hidden state y given the value of the stand alone, consumes no power while in off state, and iv) discriminant functionfx) are estimated by the maximum-the design of maximum-the DLPM is flexible enough to be applied in likelihood method

several ways depending on the system-on-chip to which it is

added .

~~~~~0

= r a lgy,,y f

(xj)

0') (2)

0 i=

III.ESTIMAION

METHODObtaining optimum estimates

through ML method thus

Typical circuit design is based on worst-case process involves two steps: 1) computing the likelihood function; 2) variability conditions to ensure circuit functionality in maximization over the set of all admissible sequences. To various process corners. This has as drawback that the evaluate the contribution of random parameters 0=Qu, ~, y), circuit is bigger, is power hungry and it is much more analysis of the likelihood function require computing an difficult to reach the desired specs. Thus, it would be better expectation over the joint statistics of the random parameter to choose simply a more "relaxed" design condition. Even vector, a task that is analytically intractable. Even if the though extensive research [15-18] has been done to estimate likelihood function can be obtained analytically off line, the various errors in different ADC architectures, use of a however, it is invariably a nonlinear function of 0, which dedicated sensors for analysis of multi-step ADC to estimate makes the maximization step (which must be performed in parameter variations have been negligible. Statistical data real time) computationally infeasible.

extracted through the DLPM measurements allows us to

characterize current process variability conditions (process 1 0(

corners) of certain parameters of interest, enabling the >X (i

optimized designenvironment. ~(° °°S @)8 % (

Consider the classical problem of estimating data from the 0.8 C O 0@°°4<

vector of observations x,s X, where the hidden state y,Yis= @0 CO0> (1,.,c} ar assumdto be reaizations of rano vau)-riablesk

which are independent andidentically distributed according r0.6 0 00

to the Pxy o(x,y 0). The parameters OEO involves parameters E 0.5 Ei/O 0 0

(uy,Xy),yEYof

GaussianL components anLd the values of the 4 )((fi)

discrete distlribution pyI,H(y

0), yei<

The input set Txy

iS54

(

given by TXt{(x1, yl)...,(x1,y')}-. Tol:.-estimae daa-idely 0

employed method in statistics is the method of maximum

002

0.3 0.4 0.5 0.6 0.7 0.8 0.9

likelihood (ML) defined as LSB

Figure 7: Fitting a posterioriprobability to the SVM output [4-5].

0 = arg max Zlog

Px)

,o

(x,,

y, 0)

(1)

In such cases, the expectation-maximization (EM) algorithm [9-10,19-22] may provide a solution, albeit iterative (and possibly numerical), to the ML estimation problem. It has been found in most instances that the EM algorithm has the

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advantage of reliable global convergence, low cost per repetitive single-DLPM measurements are performed to iteration, economy of storage, and ease of programming [19]. minimize noise errors; the number of measurements The EM algorithm builds a sequence of parameter estimates depends upon the test time budget. Each measurement is

o(O)

0(l),

....,

0(n)

such that the

log-likelihood

L(0()1

Txy)

weighted depending

upon theDLPM

spatial position

and its

monotonically increases, i.e.,

L(0(°)I

Txy)

< corresponding matchingstructureinthe circuit under test.In

L(0()

ITxy)<...

<L(O(')ITxy)

untila

stationary point

L(O(n

)I

TxY)

general,

it holds that measurements of DLPMs

spatially

=

L(-(n)l

Txy)

is achieved. In each iteration, two steps, called closer to their matching structures have a greater weight

E-step and M-step, are involved. In the E-step, the EM than measurements of other non matching DLPMs. In other algorithm determines the expectation of log-likelihood of words, the farther the structure from itsmatchingDLPMis,

the complete data based on the incomplete data and the the lower the assigned weight is. The estimation of the

currentparameter0 parameters based on the EM-algorithm is illustrated in

Figures 13-16. The ground truth model (Figure 13) is a

Q(O O(n()

=E(log p(X, Y 03) X,0(n)) (3) Gaussian model with two univariate Gaussian components

based on DLPMand Coarse ADC DNL measurements. The In the M-step, the algorithm determines a new parameter plot of thelog-likelihood function

L(O(t)l

Txy)withrespect to

maximizing Q the number of iterations is visualized in Figure 14. Finally, in Figures 15 and 16, mean ,u and variance u of decision

+-)=arg max Q(O

(nt)

(4) stage offseterrors(i), stage gain errors

(q),

anderrorsin the

0 internal reference

voltages (y)

areestimated.

The EM algorithm makes use of the log-likelihood function

for the complete data in a two-step iterative procedure V. CONCLUSIONS

which under some conditions converges to theML estimate

given in (1) [9,22]. At each step of the EM iteration, the With the use of dedicated sensors, which exploit

likeliho

function2].

cA

be show

toe

non-decreasion

knowledge

of the circuit structure and the

specific

defect [9,22]; if it is also bounded (which is mostly the case in mechanisms, we facilitate early and fast identification of

practice),then thealgorithm converges, excessive process parameter variation effects at the cost of

at maximum 10% area overhead. The sensors allow the readout of local (withinthecore) performanceparameters as

EMAlgorithm well as the global distribution of these parameters. The

Initialization flexibility of the concept allows the system to be easily

-Initialize the dataset

Txy.{(xi

y).(xi,

y.)}

extended

with

a

variety

of other performance sensors. The

-Initialize theparameter0(0)

Datacollection

implemented

maximum-likelihood method and adjusted

-Collect Nsamplesfrom the DLPMs support vector machine classifier allow us to guide the test

Update parameter estimate with the information obtained

through monitoring

process

1. CalculateQ(O

0(l)=E(logp(X,f

O)X,0(n))-Estep vrti em ploy edexpectati on iton (eM)

2. Re-estimate 0by maximizing the 0-function variations.

Employed expectation-maximization (EM)

O(n+]'=argmaxo

Q(Ol0(n)),estimate mean and variance-Mstep algorithm for estimation of the selected performance figures

3. Increase the iterationindex,n offers maximum likelihood estimates of parameters in

4.Stop whenastationary pointL(O(n-)' Txy)=L(O(n) Txy)is found. probabilistic

models,

where the model

depends

on latent

variables.

IV. TEST RESULTS

A prototype ADC converter with dedicated sensors is ACKNOWLEDGMENT

fabricated in standard single poly, five metal 0.09-pm The authors acknowledge the contributions of M.J. Barragan CMOS with the core area of 1.4 mm2. Influence of the Asian G. Gronthoud P. Pavithran and V. Zieren.

coarse ADC offset on the coarse and mid quantization and A G the transfer characteristics is illustrated in Figure 8. The

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7~ ~ ~~.-184-~ 6 -186 -188-5 E -190

1

04-l 0 02 04 0. . 0 0 B -192 _j

~~~~~~~~~~~~~~~~~~~~~~~~~~~-194-z0 3.r 2 -196 -198- -200-0 0.2 0.4 0.6 0.8 1 -202 LSB 0 5 10 15 20 25 30 35 40 45 50 iterations

Figure

F1:

CoarseADCDNLhistogramestimated from hundredsamples. Figure14:Log-likelihoodwithrespecttothe number of iterations of the EM. 4-5 4 .5-gain-mean decision-mean E_,5 3 0) 12 0.45 2.5- 0.35-0 0.0044.6 0. LSB 0 50 100 150 200 250 300 350 400

Figure 12: DLPMhistogramestimated from hundred andforty samples. iterations

Figure15:Estimating I,q,y-gtvalues withrespecttothe number of

iterations of the EM.

True model 3 ~~~~~~~~~~~~~~~~MLestimation 0.16 ref-sigma gain-sigma 2.5- 0.15 -decision-sigma 2- _0.14 1.5-C/) 0.13 0.12 0.5-0 0.11 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0.1I

Figure13:UsingtheEM-algorithmfor ML estimation. 0 50 100 150 200 250 300 350 400 iterations

Figure16:Estimating~I,q, y-uvalues withrespecttothe number of