RESURF power semiconductor devices - Performance and operating limits

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(2) RESURF power semiconductor devices Performance and operating limits. Alessandro Ferrara.

(3) Members of the dissertation committee: prof. dr. prof. dr. prof. dr. prof. dr. prof. dr. prof. dr. dr. ir. prof. dr.. P. M. G. Apers J. Schmitz L. K. Nanver E. van Tuijl P. G. Steeneken G. Groeseneken R. J. E. Hueting F. Udrea. University of Twente (chairman and secretary) University of Twente (promotor) University of Twente University of Twente TU Delft/NXP Semiconductors KU Leuven/IMEC University of Twente (assistant promotor) University of Cambridge, UK. This work is part of the Dutch Point-One program and is supported financially by Agentschap NL, an agency of the Dutch Ministry of Economic Affairs.. MESA+ Institute for Nanotechnology, University of Twente P.O.Box 217, 7500 AE Enschede, the Netherlands. c 2015 by Alessandro Ferrara, Enschede, The Netherlands. Copyright This work is licensed under the Creative Commons Attribution-NonCommercial 3.0 Netherlands License. To view a copy of this license, visit http://creativecommons.org/licenses/by-nc/3.0/nl/ or send a letter to Creative Commons, 171 Second Street, Suite 300, San Francisco, California 94105, USA. Typeset with LATEX. Printed by Gildeprint, Enschede, The Netherlands (www.gildeprint.nl). Cover designed by Nunzio Postiglione, Four Colors Process S.A.S., Casoria (NA), Italy (www.graficapostiglione.it).. ISBN DOI. 978-90-365-4032-2 10.3990/1.9789036540322 http://dx.doi.org/10.3990/1.9789036540322.

(4) RESURF POWER SEMICONDUCTOR DEVICES. P ERFORMANCE AND OPERATING LIMITS. P ROEFSCHRIFT. ter verkrijging van de graad van doctor aan de Universiteit Twente, op gezag van de rector magnificus, prof. dr. H. Brinksma, volgens besluit van het College voor Promoties in het openbaar te verdedigen op woensdag 13 januari 2016 om 12.45 uur. door Alessandro Ferrara. geboren op 2 september 1988 te Napels, Italie.

(5) Dit proefschrift is goedgekeurd door:. prof. dr. dr. ir.. J. Schmitz (promotor) R.J.E. Hueting (assistant promotor).

(6) To my Parents. If you want to find the secrets of the universe, think in terms of energy, frequency and vibration. (N. Tesla).

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(8) A BSTRACT Power transmission is the transfer of energy from a generating source to a load which uses the energy to perform useful work. Since the end of the 19th century, electrical power transmission has replaced mechanical power transmission in all long distance applications. The alternating current (AC) generator invented by Nikola Tesla allows to efficiently convert mechanical energy into electrical energy and is still used nowadays to power cities all over the word. The transmitted electrical energy often needs to be manipulated before it can be used by the load. For example, the electrical signal has to be amplified (or attenuated) and/or converted into a different waveform. These operations are performed by power electronic circuits acting as an interface between the source and the load. The rapid growth of the semiconductor industry started in the second half of the 20th century has allowed the large scale manufacturing of the semiconductor devices used in modern electronics. As this industry has become more and more mature, it has allowed the system integration of operations of different nature, such as analog/digital processing and electrical power manipulation. This integration is usually referred to as smart power technology. Since the 1990’s, smart power electronic systems have extensively been used in the automotive and lighting industry. In the next future, with the advent of the internet of things (IoT), smart power systems will become more complex and allow the wireless transmission of information between smart objects. This thesis aims at investigating theoretical and experimental methods for the analysis and the performance optimization of the power semiconductor devices used in smart electronic systems. The results are complimentary to those documented in the doctorate thesis of B. K. Boksteen1 . In the following, a chapter-by-chapter content overview is provided.. Overview Chapter 1 provides a brief introduction to power semiconductor devices, constituting the principal component in a power electronic circuit: the switch. A classification of the existing power devices is provided together 1 B. K. Boksteen, Field-plate assisted RESURF power devices: Gradient based optimization, degradation and analysis. PhD thesis, University of Twente, 2015.. vii.

(9) viii ABSTRACT. with an overview of their operation physics. The discussion allows to introduce the trade-offs emerging in the design of an optimized power device. The main focus of this thesis is highlighted with respect to existing work in the field and a brief outline of the following chapters is provided. Chapter 2 provides the theoretical background for designing the drift extension of power semiconductor devices in order to maximize the breakdown voltage without sacrificing the on-resistance. This is achieved using the REduced SURface Field (RESURF) effect, which aims at achieving an electric field distribution in the drift region along the current flow direction ( Ex -field) with low (ideally zero) slope. Chapter 3 focuses on the trade-off between the specific on-resistance and the off-state breakdown voltage in RESURF power devices. Analytical equations are derived based on the RESURF theory presented in Chapter 2 to estimate the specific on-resistance as a function of the off-state breakdown voltage in an optimized RESURF drift extension. It is shown that a switchable field plate electrode acting on the drift extension can be used to further reduce the on-resistance without affecting the Ex -field distribution in the off-state. The device based on this principle, named the boost transistor, is discussed. In Chapter 4, three electrical techniques (pulsed-gate, AC-conductance and sense-diode) for evaluating the junction temperature of power transistors are discussed and experimentally compared. The device under test is provided with embedded sense-diodes in the center and at the edge of the device for providing local temperature information. In Chapter 5 a general procedure for experimentally determining the safe operating limits of power transistors is presented. It is proposed to extend the safe operating area to a volume by adding a junction temperature axis, and normalizing the drain current to the gate width. The resulting three-dimensional space comprising the safe operating points is defined as safe operating volume (SOV). In Chapter 6, a physics-based model is derived based on a linearization procedure for investigating the electrical, thermal and electro-thermal instability of power metal-oxide-semiconductor (MOS) transistors. The model leads to a theoretical definition of the SOV, proposed in Chapter 5. In Chapter 7 the main results of this thesis are summarized and recommendations for future work are provided..

(10) S AMENVATTING Vermogensomvorming is het proces waarbij energie van een bron naar een ontvanger wordt getransfereerd, zodat deze nuttige arbeid kan verrichten met de energie. Sinds het eind van de 19de eeuw heeft elektrische omvorming de plaats ingenomen van mechanische omvorming in alle langeafstandstoepassingen. De wisselstroom generator, uitgevonden door Nikola Tesla, maakt het mogelijk om efficiënt mechanische energie in elektrische energie om te zetten en wordt nu nog steeds gebruikt om steden over de hele wereld van energie te voorzien. De verzonden elektrische energie moet vaak worden bewerkt voordat het gebruikt kan worden door de ontvanger. Het elektrische signaal moet bijvoorbeeld worden versterkt (of verzwakt) en/of geconverteerd in een andere golfvorm. Deze bewerkingen worden uitgevoerd door vermogenselektronica circuits die fungeren als een interface tussen bron en ontvanger. De snelle groei van de halfgeleiderindustrie, die begonnen is in de tweede helft van de 20de eeuw, heeft het mogelijk gemaakt om grote aantallen halfgeleiderapparaten te produceren die nu gebruikt worden in moderne elektronica. Naarmate deze industrie volwassener werd, heeft dit geleid tot systeemintegratie van functies van verschillende aard, zoals analoog/digitaal verwerking en elektrische vermogensomvorming. Sinds de jaren 0 90 worden slimme vermogenselektronica circuits op grote schaal gebruikt in de auto- en verlichtingsindustrie. In de nabije toekomst, met de komst van het internet of things (IoT), zullen slimme vermogenselektronica systemen complexer worden en de draadloze verzending van informatie van informatie tussen slimme objecten faciliteren. Dit proefschrift heeft tot doel om theoretische en experimentele methoden voor de analyse en optimalisatie van vermogenshalfgeleiderapparaten in slimme elektronische systemen te bestuderen. De resultaten zijn complementair aan de resultaten in het doctoraal proefschrift van B. K. Boksteen2 . Hieronder zal per hoofdstuk een kort overzicht van de inhoud van het proefschrift gegeven worden.. 2 B. K. Boksteen, Field-plate assisted RESURF power devices: Gradient based optimization, degradation and analysis. PhD thesis, University of Twente, 2015.. ix.

(11) Overzicht x SAMENVATTING. Hoofdstuk 1 geeft een korte introductie van de vermogenselektronica apparaten die de belangrijkste component in een vermogenselektronica circuit vormen: de schakelaar. Een classificatie van bestaande vermogensapparaten wordt gegeven samen met een overzicht van hun werkingsprincipes. De discussie introduceert de afwegingen die gemaakt moeten worden in de optimalisatie van vermogens apparaten en transistoren. Het hoofddoel van dit proefschrift wordt uitgelicht ten opzichte van bestaand werk in dit vakgebied en een korte samenvatting van de volgende hoofdstukken wordt gegeven. Hoofdstuk 2 geeft de theoretische achtergrond voor het ontwerp van de hoogspanningsextensie van vermogenshalfgeleiderapparaten dat de doorslagspanning maximaliseert zonder de aan-weerstand op te offeren. Dit wordt bereikt met behulp van het gereduceerd oppervlakteveld (RESURF) effect, dat erop gericht is om een elektrisch veld distributie in de richting waarin de stroom loopt ( Ex -veld) met een lage (idealiter nul) helling te bereiken. Hoofdstuk 3 richt zich op de afweging tussen de specifieke aan-weerstand en de doorslagspanning in de uit-toestand in RESURF vermogens apparaten. Analytische vergelijkingen worden afgeleid, gebaseerd op de RESURF theorie die gepresenteerd is in hoofdstuk 2, om de specifieke aan-weerstand als functie van de uit-toestand doorslagspanning in te schatten in een geoptimaliseerde RESURF hoogspanningsextensie. Het wordt aangetoond dat een schakelbare veldplaat elektrode, die op de hoogspanningsextensie inwerkt, gebruikt kan worden om de aan-weerstand verder te reduceren zonder de Ex -veld distributie in de uit-toestand te beÃ´rnvloeden. Het apparaat dat op dit principe werkt, genaamd de boost transistor, wordt besproken. In Hoofdstuk 4, worden drie elektrische technieken (gepulste gate, ACgeleidbaarheid en sensor-diode) om de junctie temperatuur van vermogenstransistoren te bepalen besproken en experimenteel vergeleken. Het apparaat-onder-test is uitgerust met sensor-diodes in het midden en aan de rand van het apparaat om lokale temperatuurinformatie te leveren. In Hoofdstuk 5 wordt een algemene procedure gepresenteerd om de veilige bedrijfslimieten van vermogenstransistoren te bepalen. Het wordt voorgesteld om het concept van veilig bedrijfsoppervlak uit te breiden naar een volume door een junctietemperatuur-as toe te voegen en de drain stroom te normaliseren naar de gate breedte. De resulterende driedimensionale ruimte die de veilige bedrijfspunten omvat wordt gedefinieerd als het veilige bedrijfsvolume (SOV)..

(12) In Hoofdstuk 7 worden de belangrijkste resultaten van dit proefschrift samengevat en worden aanbevelingen voor toekomstig werk gegeven.. xi SAMENVATTING. In Hoofdstuk 6, wordt een fysica-gebaseerd model afgeleid, op basis van een linearisatie procedure, om de elektrische, thermische en elektrothermische instabiliteit van vermogens metaal-oxide-halfgeleider (MOS) transistoren te onderzoeken. Het model leidt tot een theoretische definitie van het SOV, voorgesteld in hoofdstuk 5..

(13) C ONTENTS A BSTRACT · vii S AMENVATTING · ix 1. 1.4. P OWER S EMICONDUCTOR D EVICES 1.1 Introduction 1.2 The switch 1.3 Power semiconductor device classification An insight into power semiconductor device physics 1.5 Design trade-offs 1.6 Thesis outline I DEAL RESURF GEOMETRIES 2.1 The principle of RESURF 2.2 Derivation of the ideal RESURF solution Examples of ideal and DIELER RESURF structures 2.4 Combined RESURF structures 2.5 Discussion 2.6 Conclusions. · · · · · · ·. 13 14 15 20 24 25 27. B REAKDOWN VOLTAGE AND SPECIFIC ON - RESISTANCE 3.1 Ron V-BV trade-off in RESURF drift extensions 3.2 Improving the Ron V-BV trade-off: the boost transistor 3.3 Conclusions. · · · ·. 29 30 34 41. 4 J UNCTION TEMPERATURE 4.1 Self-heating in power devices Three electrical techniques for temperature evaluation 4.3 Experimental results 4.4 Benchmarking analysis 4.5 Conclusions. · · · · · ·. 43 44 45 52 52 56. 5 S AFE OPERATING LIMITS 5.1 Determining the safe operating limits 5.2 From Safe Operating Area to Safe Operating Volume 5.3 The general nature of the Safe Operating Volume 5.4 Prediction of SOA curves from the SOV. · · · · ·. 57 58 62 62 65. 2. 2.3. 3. 4.2. xii. · 1 · 2 · 3 · 4 · 6 · 9 · 11.

(14) 5.5. Conclusions · 66. 6. 7. S UMMARY AND RECOMMENDATIONS 7.1 Summary 7.2 Innovative contributions 7.3 Recommendations for future work. · · · · · · · ·. 69 70 71 72 77 80 81 83. · · · ·. 85 85 87 88. B IBLIOGRAPHY · 95 L IST OF PUBLICATIONS · 99 Peer-reviewed · 99 Other · 99 A CKNOWLEDGMENTS ·101. xiii CONTENTS. 6.7. P HYSICS -B ASED S TABILITY A NALYSIS 6.1 Introduction 6.2 Origin of electro-thermal runaway 6.3 Analytical stability analysis 6.4 The Safe Operating Volume (SOV) 6.5 Discussion 6.6 Conclusions Avalanche, MOS and bipolar model equations.

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(16) CHAPTER. P OWER S EMICONDUCTOR D EVICES Abstract This chapter provides a brief introduction to power semiconductor devices, constituting the principal component in a power electronic circuit: the switch. A classification of the existing power devices is provided together with an overview of their operation physics. The discussion allows to introduce the trade-offs emerging in the design of an optimized power device. The main focus of this thesis is highlighted with respect to existing work in the field and a brief outline of the following chapters is provided.. 1. 1.

(17) Source. Iout. Ii. Load. 2 1.1. INTRODUCTION. Vi. Power processing. Vout. Figure 1.1: Schematic illustration of a power processing circuit.. 1.1. Introduction. Power electronics is the branch of electronics dealing with the processing of electrical energy. An electrical source generates energy which is amplified, stored and/or converted to a different waveform by a power electronic system and eventually transferred to a user (load). A schematic of an example power conversion system is shown in Fig. 1.1 [1]. Its function is to match the current and voltage requirements of the source to those of the load. Depending on requirements of the application, a power circuit can contain different components, such as switches, amplifiers, transformers, transducers, actuators, storage and dissipative elements. The most important figure of merit of a power circuit is the power conversion efficiency, defined as the ratio between the average output and input powers. Highly-efficient power conversion can be achieved by combining a switch with energy storage elements. The switch is periodically opened and closed in order to modulate the input current from the source. The energy storage elements act as a filter selecting the desired frequency components to transfer to the load from the modulated input. For maximum efficiency, the power losses on both the switch and energy storage elements should be minimized. Since the advent of solid-state electronics, the switching function is performed by a power semiconductor device, whose behavior should be as close as possible to that of an ideal switch (defined in Section 1.2) in order to maximize the system efficiency. Energy storage is performed by inductors and capacitors, which should be ideally lossless. In practice, the filter losses are determined by the parasitics in its components. Since the 1990’s, the rapid developments in microelectronics have allowed to design and manufacture power semiconductor devices using similar technology available for digital electronics. Such integration has laid the grounds for the so-called smart power technology, allowing digital drivers, control systems, and interfaces to microprocessors to be available on the same chip as the power device [2]. This is especially useful in automotive applications [3], where different analog, digital and power conversion func-.

(18) On-state. Off-state max. Von = 0. Voff = ∞. -. +. -. Ioff = 0. Ion = ∞ Ion = Von /Ron Ron. Real switch. Cswitch. + Von ≠ 0. Ron -. Cswitch. max. Voff = BV +. Diode. -. Diode Ioff ≠ 0. Figure 1.2: Ideal vs. real switch. tionalities are needed within the same system. The power devices experimentally investigated in this thesis have been fabricated in NXP’s 140nm Advanced Bipolar CMOS DMOS (A-BCD9 [3]) smart power technology.. 1.2. The switch. As mentioned in Section 1.1, the switch is one of the main constituents of a power circuit, and its performance is critical for maximizing the power conversion efficiency. An ideal switch has the following characteristics: 1. When it is closed (on-state), it can carry an infinite amount of current without any voltage drop across it and hence without any static power dissipation; 2. When it is open (off-state), it can sustain an infinite voltage across its terminals without any leakage current; 3. It can transit (switch) from the on-state to the off-state (and vice versa) instantaneously and without any dynamic power dissipation; 4. It can operate at any (arbitrarily high) temperature; 5. It can sustain an infinite number of switching cycles without degrading (i. e., altering its performance) or being damaged. Compared to an ideal switch, a power device exhibits the following nonidealities: (Fig. 1.2):. 3 CHAPTER 1. POWER SEMICONDUCTOR DEVICES. Ideal switch. +.

(19) 4. 1. It has a finite resistance in the on-state, which is defined as onresistance (Ron ), an important figure of merit for the static power consumption.. 1.3. POWER SEMICONDUCTOR DEVICE CLASSIFICATION. 2. It carries a non-zero leakage current in the off-state, which increases with the voltage across its terminals. When the off-state leakage exceeds a critical value, the transistor is in breakdown condition. The voltage for which breakdown occurs is defined as the breakdown voltage (BV). 3. Because of parasitic capacitances (Cswitch ), switching a power device from the on-state to the off-state (and vice versa) requires a finite amount of time and causes a dynamic energy dissipation. 4. There is a maximum (junction) temperature Tj a power device can withstand, which is referred to as Tjmax . Because of its thermal impedance Zth , the device heats up in the on-state and the junction temperature Tj is higher than the ambient temperature Tamb . 5. Each switching cycle degrades the device performance by affecting the values of the on-resistance, breakdown voltage, leakage current and parasitic capacitances. In order to keep the degradation within acceptable limits, only a finite number of switching cycles can be perfomed. This number is strongly dependent on operating and environmental conditions and defines the transistor lifetime.. 1.3. Power semiconductor device classification. Several types of semiconductor switches have been invented in order to cover applications of different nature [4]. They can be classified based on the following criteria (Fig. 1.3): 1. Number of junctions; 2. Number of electric terminals; 3. Mechanism of current conduction. Based on the number of junctions, the most common power devices are formed by1 : 1. One junction, such as: a) The pn diode, containing a junction between a p-type and an n-type semiconductor layer; b) The Zener diode; 1 There. is no theoretical upper limit to the number of junctions a power device can have..

(20) c) The Schottky diode, containing a junction between a (p-type or n-type) semiconductor layer and a metal;. 2. Two junctions, such as: a) The metal-oxide-semiconductor field effect transistor (MOSFET) and the high electron mobility transistor (HEMT); b) The bipolar junction transistor (BJT) and the heterojunction bipolar transistor (HBT). 3. Three junctions, such as: a) The silicon(semiconductor)-controlled rectifier (SCR) (also known as thyristor); b) The gate turn-off (GTO) thyristor; c) The insulated gate bipolar transistor (IGBT). Based on the number of electric terminals, the devices can be classified as: 1. Two-terminal devices (diodes). In a diode, the current flow is regulated by the polarity of the voltage between the anode and the cathode (positive in the on-state and negative in the off-state). 2. Three-terminal devices2 (transistors and thyristors). In a transistor, the current flow is regulated by applying a voltage to a control terminal (gate) or injecting a current into it (base). A thyristor is switched on by applying a set of repetitive current pulses on the control terminal (gate) to induce positive feedback in the current flowing between the anode and the cathode (latch-up). A conventional thyristor (SCR) cannot be switched off by acting on the gate once latch-up has occurred. This limitation has been overcome by the invention of the GTO thyristor, which allows the current flow to be switched off by draining current from the gate. Based on the mechanism of current conduction, power semiconductor devices are classified as: 1. Minority carrier (bipolar) devices (pn diode, Zener diode, BJT, HBT, IGBT, SCR and GTO). The main contribution to the current is given by the diffusion of electrons in a p-type layer and holes in a n-type layer. Since both electrons and holes contribute to the current flow these devices are also referred to as bipolar devices. 2 Devices with more than three terminals are not standard, but are often used as test structures. For example, a separate body contact is useful for a more in-depth device characterization. A fourth terminal can be also used to measure the junction temperature (the embedded sense-diode, see Chapter 4).. 5 CHAPTER 1. POWER SEMICONDUCTOR DEVICES. d) The junction field effect transistor (JFET) and the metal-semiconductor field effect transistor (MESFET)..

(21) Two-terminal. Three-terminal. p1d. p2d. One-junction p1ad. 6. p1bd. A. A. p1cd. p1dd. 1.4. AN INSIGHT INTO POWER SEMICONDUCTOR DEVICE PHYSICS. K. K. Three-junction p2bd. p2ad. D. A. D G. G K. p3d. Two-junction p3ad. C G. S. MOSFET pn ZenerF SchottkyF JFET HEMT DiodeF Diode Diode MESFET MinorityF MajorityFcarrier carrier. p3cd. A. B G. G S. p3bd. A. C. E. K. K. E. BJT HBT. SCR. GTO. IGBT. MinorityFcarrier. Figure 1.3: Nomenclature and classification of power semiconductor devices. 2. Majority carrier (unipolar) devices (Schottky diode, JFET, MESFET, MOSFET and HEMT). The main contribution to the current is governed by drift of majority charge carriers (electrons in n-type layers or holes in p-type layers). Since only one carrier type contributes to the current flow, these devices are also referred to as unipolar devices. A majority carrier device provides a lower current density compared to a minority carrier device but a better (faster and with less dynamic losses) switching performance.. 1.4 1.4.1. An insight into power semiconductor device physics Intrinsic device and drift extension. All power semiconductor devices classified in Fig. 1.3 contain two main components: (1) an intrinsic device (diode, transistor or thyristor), which regulates and controls the current flow and (2) a drift extension, which sustains the breakdown voltage in the off-state (Fig. 1.4). The drift extension, as shown schematically in Fig. 1.5, is a slab of semiconductor material (n-type in an NMOS and p-type in a PMOS) which is depleted in the off-state operation. When an off-state voltage V0 is applied across the device terminals, a depletion layer is formed (green area in Fig. 1.5) which extends across the drift region by a distance x0 . As V0 increases by an amount dV, the depletion layer increases by a distance dx until breakdown occurs (i. e., V0 = BV). The relationship x = f(V) between the extension of the depletion layer and the applied voltage depends on the nature of the junction and its dimensions (1D, 2D or 3D junctions are possible). In the on-state, the drift extension simply acts as a resistor and contributes to the on-resistance. The higher the BV of the device, the longer the drift extension needed to sustain it, resulting in a larger Ron . The physics of the drift extension is responsible for the trade-off between the on-resistance times unit area A (specific on-resistance Ron A) and BV, known as the Ron A − BV trade-off..

(22) Intrinsic device (diode, transistor or thyristor). Anode. 7. Controls the current flow. Ron. Drift extension. Diode. Cathode. Sustains the breakdown voltage Contributes to the on-resistance. Figure 1.4: Schematic of a power semiconductor device including the intrinsic device and the drift extension.. In the discussion above, it has been assumed that the only contribution to Ron comes from the drift extension. This is a simplification, since in reality the intrinsic device also has a finite resistance (see [4] for an analysis of the different resistance contributions in a power device). However, the relatively-long drift extension needed to sustain high BV values often. 0. x. Junction. Metal or Semiconductor semiconductor drift region. dx. x = f (V). V0 dV. x0 Figure 1.5: Schematic of a 1D junction adjacent to a semiconductor drift extension. When an off-state voltage V0 is applied, a depletion layer (green area) is formed which extends across the drift region by a distance x0 . As V0 increases by an amount dV, the depletion layer increases by a distance dx until breakdown occurs (i. e., V0 = BV). The relationship x = f(V) depends on the physical nature of the junction.. CHAPTER 1. POWER SEMICONDUCTOR DEVICES. (Control).

(23) 8 1.4. AN INSIGHT INTO POWER SEMICONDUCTOR DEVICE PHYSICS. results in the drift resistance being much larger than that of the intrinsic device. For practical purposes, it is possible to treat the intrinsic device as an ideal switch (see Section 1.2) and to attribute the on-resistance and off-state diode behavior to the physics occurring in the drift extension.. 1.4.2. Operating limits. From a user’s point of view, the operating condition of a power device is determined by the applied voltage between the anode and cathode and the current flowing between them. In a three-terminal device, the magnitude of this current can be modified via the control terminal, e. g. by applying a gate-to-source voltage in a MOSFET. In the following, I and V refer to the current flowing through the drift region and the voltage drop across it, respectively. It is implicitly assumed that I can be voltage or current controlled. The device operation can be represented in the current-voltage (I-V) plane or in the current density-voltage (J-V) plane, by normalizing the current I to the cross-sectional area through which current flows (Aflow ). The current I density is defined as J = Aflow (Fig. 1.6) and the specific on-resistance as V Ron A = J for operation in the linear regime3 . dJ As shown in Fig. 1.6a, the J-V relationship is linear with slope dV = Ron1 A for voltage values below the saturation voltage Vsat . When V = Vsat , the current density saturates to the value Jsat because of the saturation of the carrier velocity with the electric field in the drift extension [5]. The maximum allowed value for the voltage V is defined by the breakdown voltage BV. The parameters Ron A, Vsat , Jsat and BV define a bounded area in the J-V plane, which is defined as the operating area. The operating area contains all possible operating points in the J-V plane, and can be formally defined as the area described by the following functions:  V  (a) J = Fon (V) = Ron A for V 6 Vsat  J = Fsat (V) = Jsat for V > Vsat   V = F (I) = BV BV. (b) ,. (1.1). (c). where Vsat = Ron AJsat . The extension of the operating area is primarily determined by the Ron A − BV trade-off. However, as shown in Fig. 1.6b, not all operating points yield a safe electrical operation, because of non-idealities in the device behavior caused by parasitic elements. In particular, the breakdown voltage is given by BV only when a negligible (ideally zero) leakage current flows into the device. In the on-state, the breakdown voltage depends on the current 3 The specific on-resistance is defined in literature as the product between R on and the device active area A rather than Aflow , since the device cost depends on the area it occupies on the wafer. This definition is correct for vertical devices where A = Aflow but has no physical meaning for lateral devices where A 6= Aflow (see Fig. 3.1). In order to deal with this issue, the on-resistance times unit volume has been introduced in Chapter 3..

(24) density J, and might be approximated by the following linear relationship (see Chapter 6.3.1 for a physics-based expression): BV − V for BVsat 6 V 6 BV BV − BVsat. 9 (1.2). where BVsat represents the breakdown voltage when J = Jsat . The area described by the intersection of the functions Fon , Fsat , FBV and Fel is defined as the electrical safe operating area. Further limitations to the safe operating limits originate from the phenomenon called self-heating (SHE), which will be experimentally analyzed in Chapter 4. When a current flows into the device, the dissipated power Pd = I · V causes an increase in the device temperature Tj = Tamb + Zth · Pd . The Tj -increase is particularly relevant in the saturation region, where both I and V are high. Since Jsat is temperature dependent, it decreases with the applied voltage according to (see Chapter 6.3.2): J = FSHE (V) =. Jsat ≈ Jsat (1 + Zth φV) for Zth φV 1, 1 − Zth φV. (1.3). sat where φ = ∂J ∂Tj is the (negative) temperature coefficient of Jsat [5]. As shown in Fig. 1.6c, Jsat decreases with V in the saturation region and reduces the extension of the operating area. In addition, the maximum junction temperature Tjmax the device can withstand imposes a limitation to the T −T maximum dissipated power Pdmax = j maxZth amb , where Tamb is the ambient temperature and Zth the device thermal impedance. As a result, the current density J is limited by the following hyperbolic function in the J-V plane:. J = Fth (V) =. Tjmax − Tamb . Zth · Aflow · V. (1.4). The area described by the functions Fon , Fsat , FBV , FSHE and Fth is defined as the thermal safe operating area. Finally, the intersection of the thermal and electrical safe operating areas determines the overall safe operating area of the power device (Fig. 1.6d).. 1.5. Design trade-offs. The various electrical and thermal mechanisms that characterize the operation physics make the design of an optimized power device a challenging task. Numerous trade-offs have to be considered. While optimizing the Ron A−BV trade-off, other important device parameters such as the the safe operating limits, the switching speed, the leakage current and the device lifetime have to be taken into account. A schematic overview of the design trade-offs based on the physical limits of a real switch (see Section 1.2) is given in Fig. 1.7. The main focus of this thesis is to provide the theoretical background and the experimental tools for analyzing and improving the trade-off between Ron A, BV and the. CHAPTER 1. POWER SEMICONDUCTOR DEVICES. J = Fel (V) = Jsat ·.

(25) Jsat. Operating Area Vsat. Voltage (V) BV. 0. Jsat. Fel FSHE Fth BVsat. Electrical Safe Operating Area Vsat. Voltage (V) BV. (d) Current density (A/cm2) 1/R on A. (c). on A. Jsat. 1/R. 1.5. DESIGN TRADE-OFFS. 0. Current density (A/cm2) 1/R on A. (b). Current density (A/cm2) 1/R on A. (a). Current density (A/cm2). 10. Fon Fsat FBV. 0. Thermal Safe Operating Area Vsat. Voltage (V). BV. 0. Jsat. BVsat. Safe Operating Area Vsat. Voltage (V) BV. Figure 1.6: Definition of the a) Operating Area, b) Electrical Safe Operating Area, c) Thermal Safe Operating Area and d) Safe Operating Area in the J-V plane.. electro-thermal safe operating limits, which P. L. Hower defines as the design triangle in [6]. When improving the Ron A − BV trade-off, larger current densities flow into the device. In particular, an increase in Jsat negatively affects the electro-thermal stability of the device (see Chapter 6.3) and results in a reduction of the corresponding safe operating areas. Reducing the resistance of the drift extension (e. g, by increasing the doping concentration or the cross-sectional area of the current flow) also results in an increase of the associated capacitance which in turn worsens the switching speed. In addition to the drift capacitance, there are other capacitance contributions depending on the physical and geometrical nature of the device. However, a detailed analysis of switching behavior of a power device is out of the scope of this work. For an overview of the figures of merit typically used for analyzing the capacitances and switching performance of power devices, the reader is referred to Refs. [7, 8]. Additional levels of complexity emerge when leakage current, reliability and lifetime considerations are made. This topic has been analyzed in detail for power MOSFETs in the doctorate thesis of B. K. Boksteen [9]. His work indicates that there is a strong correlation between the off-state leakage.

(26) Boksteen´s work [9] 11. This work. Temperature limit. Current limit. Refs. [7-8] Switching time limit. Lifetime limit. Figure 1.7: Overview of the trade-offs in the design optimization of a power semiconductor device and focus of this work. The red and green lines between the pentagon vertices indicate opposing and supporting limits, respectively. Grey lines are shown where the relationships are not clearly defined. current and the device lifetime. Optimizing the Ron A − BV trade-off yields devices with smooth electric field distributions in the drift extension (see also Chapters 2-3 of this thesis). This is beneficial for device reliability, since it reduces the impact of charge trapping mechanisms [10] which increase the leakage current and result in a shorter device lifetime.. 1.6. Thesis outline. The thesis is organized as follows. Chapter 2 provides the theoretical background for designing the drift extension of power semiconductor devices in order to maximize the breakdown voltage without sacrificing the on-resistance. This is achieved using the REduced SURface Field (RESURF) effect, which aims at achieving an electric field distribution in the drift region along the current flow direction ( Ex -field) with low (ideally zero) slope. Chapter 3 focuses on the trade-off between the specific on-resistance and the off-state breakdown voltage in RESURF power devices. Analytical equations are derived based on the RESURF theory presented in Chapter 2 to estimate the specific on-resistance as a function of the off-state breakdown voltage in an optimized RESURF drift extension. It is shown that a switchable field plate electrode acting on the drift extension can be used to further. CHAPTER 1. POWER SEMICONDUCTOR DEVICES. Voltage limit.

(27) 12 1.6. THESIS OUTLINE. reduce the on-resistance without affecting the Ex -field distribution in the off-state. The device based on this principle, named the boost transistor, is discussed. In Chapter 4 three electrical techniques (pulsed-gate, AC-conductance and sense-diode) for evaluating the junction temperature of power transistors are discussed and experimentally compared. The device under test is provided with embedded sense-diodes in the center and at the edge of the device for providing local temperature information. In Chapter 5 a general procedure for experimentally determining the safe operating limits of power transistors is presented. It is proposed to extend the safe operating area to a volume by adding a junction temperature axis, and normalizing the drain current to the gate width. The resulting threedimensional space comprising the safe operating points is defined as safe operating volume (SOV). In Chapter 6 a physics-based model is derived based on a linearization procedure for investigating the electrical, thermal and electro-thermal instability of power metal-oxide-semiconductor (MOS) transistors. The model leads to a theoretical definition of the SOV, proposed in Chapter 5. In Chapter 7 the main results of this thesis are summarized and recommendations for future work are provided..

(28) CHAPTER. I DEAL RESURF GEOMETRIES Abstract This chapter provides the theoretical background for designing the drift extension of power semiconductor devices in order to maximize the breakdown voltage without sacrificing the on-resistance. This is achieved using the REduced SURface Field (RESURF) effect, which aims at achieving an electric field distribution in the drift region along the current flow direction ( Ex -field) with minimal, ideally zero, slope. A method is demonstrated to construct devices that obey Poisson’s equation and satisfy the ideal RESURF condition giving zero slope in Ex throughout the two-dimensional (2D) device region. The designs are obtained by shaping the device geometry and the boundary and by applying the proper potentials at the boundaries. Using this method ideal designs have been derived for devices based on graded doping, graded thickness and graded field-plate potential. In addition, 2D solutions have been derived for periodic superjunction and DIELEctric Resurf (DIELER) device geometries. Solutions for devices that combine several types of field shaping are demonstrated. Finally, the effect of non-ideal geometries on the breakdown voltage in actual devices is discussed.. This chapter was published in IEEE Trans. Electron Devices [11]. For clarity it has been expanded with additional figures and explanations.. 13. 2.

(29) 2.1. 14. The principle of RESURF. 2.1. THE PRINCIPLE OF RESURF. Breakdown of semiconductor devices occurs due to an avalanche of charge carriers initiated by high electric fields in reverse biased junctions [4, 12]. In order to increase the breakdown voltage of high voltage semiconductor devices, a relatively long drift extension is therefore used to reduce the electric fields [4]. It is commonly known [13] that the off-state breakdown voltage is maximized by ensuring that the electric field in the drift region along the current flow direction (x-direction) satisfies: ∂ Ex (x, y) = 0. ∂x. (2.1). This is defined as the ideal RESURF condition for the Ex field. For most 2D device designs the solution of Poisson’s equation does not obey (2.1). As will be shown, an ideal RESURF geometry requires the device boundaries to be shaped in a special manner, an aspect that has not been dealt with in earlier work [14–20]. Since the ideal field condition is not satisfied everywhere, the breakdown voltage of these devices is lower than for those satisfying (2.1) at a given drift extension length L. For these reasons, the investigation of device designs that provide solutions of Poisson’s equation obeying (2.1) is worthwhile. Exact solutions of (2.1) are also useful for performance optimization of other semiconductor devices like FinFETs, nanowire, gate-all-around (GAA) FETs, deep submicron transistors [21] and avalanche photodiodes [22]. The RESURF (REduced SURface Field [23– 25]) principle is based on reducing the field in the current flow direction (xdirection) by introducing a perpendicular field gradient (in the y-direction) as is illustrated in Fig. 2.1. In the absence of RESURF (Fig. 2.1a), with Ex = ρε , where ρ zero Ey -field gradient, the Ex -field has a gradient ∂∂x is the charge density and ε the dielectric permittivity. In Fig. 2.1b), the ∂E RESURF effect is implemented using a ∂yy field gradient in the drift region. Since, according to Poisson’s equation, ∂Ey ∂y. ∂ Ex ∂x. +. ∂Ey ∂y. = ρε , it follows that for. Ex = ρε the gradient ∂∂x becomes zero and the ideal RESURF condition (2.1) is satisfied. The graphs on the right side of Fig. 2.1 illustrate that at identical maximum field and off-state breakdown voltage, an optimized 2D drift extension needs only half of the length compared to a 1D one. The breakdown voltage is equal to the grey area under the graphs. An additional advantage of the application of RESURF is that a higher doping in the drift region can be used. While increasing the doping would lead to a reduction of the breakdown voltage in a 1D device (Fig. 2.1a), the RESURF effect can be used to balance the increase in charge density by a higher ∂E vertical field gradient ∂yy . This further improves the specific on-resistance RON A-BV trade-off of power devices [26]. This chapter focuses on constructing 2D device designs that satisfy ideal RESURF (Fig. 2.1b). For the sake of generality, the x and y directions in this work respectively refer to the direction of the current flow and any of the.

(30) =. (no-RESURF). ) 15. Figure 2.1: Schematics explaining the RESURF principle by considering an infinitesimal part of the drift region containing a constant charge density ρ and dielectric constant . a) A 1D device in the absence of RESURF effect. ∂E Since ∂yy = 0, according to Poisson’s equation (2.3) the electric field Ex Ex has a slope ∂∂x = ρε . The infinitesimal variation of the Ex -field amplitude from x to x + dx is indicated by E0 (blue arrow). b) The ideal field condition can be satisfied by applying an electric field in the y-direction with gradient ∂Ey ρ ∂ Ex ∂y = ε , such that ∂x = 0 and Ex is constant.. two directions perpendicular to it, independently of the device orientation with respect to the wafer plane. Therefore, the proposed designs can be implemented in both lateral and vertical devices with RESURF fields acting either in or out of the wafer plane. The chapter is organized as follows. Section 2.2 describes ideal 2D RESURF geometries that are derived from the exact analytical solution of Poisson’s equation. Two types of geometries are discussed: 1) geometries that use field-plates to generate the field gradient ∂Ey ∂y and 2) periodic geometries that use superjunction and DIELER geometries to satisfy the ideal field condition. Section 2.3 shows implementation examples of the different types of ideal and near ideal RESURF solutions. Section 2.5 discusses the effect of deviations from the ideal case on the breakdown voltage and shows an example of a combined RESURF device. The conclusions are presented in Section 2.6.. 2.2. Derivation of the ideal RESURF solution. In this section analytical solutions of Poisson’s equation are derived that Ex satisfy the ideal RESURF condition ∂∂x = 0. The assumed geometry and boundary conditions are sketched in Fig. 2.2. The structure consists of two domains, with charge densities ρ1,2 and dielectric constants ε1,2 .. CHAPTER 2. IDEAL RESURF GEOMETRIES. (ideal RESURF).

(31) 16. Domain 1. 2.2. DERIVATION OF THE IDEAL RESURF SOLUTION. Domain 2. (FP-assisted RESURF). (Periodic RESURF). Figure 2.2: Schematic potential distribution ψ(x, y) in the drift extension of ideal RESURF devices. Only half of the symmetric structure is shown. The device is mirror symmetric in the boundary at y = 0 and a field plate (at potential VFP ) or periodic boundary condition is placed at y = t1 + t2 .. The interface between the domains is assumed to be ideal, i.e. free of interface charges. At this interface the perpendicular displacement field D⊥ , the parallel field Ek and the potential ψ need to be continuous. Domain 1 is made of a semiconductor material, that has the purpose to block current at high-voltages in the off-state and to conduct current in the on-state. The main purpose of domain 2 is to generate the field gradient ∂Ey ∂y needed for the RESURF effect in the current blocking state. In this work domain 2 is either made of a dielectric without fixed charge (ρ2 = 0) or of a semiconductor material with opposite charge density compared to that in domain 1 (ρ2 6= 0). Since the structure is intended for blocking voltages up to an off-state breakdown voltage BV, the right boundary is at a potential ψ = BV whereas the left boundary is at ground (ψ = 0). The geometry (and potential ψ(x, y)) is mirror symmetric with respect to the x-axis ( ∂ψ(x,y) |y=0 = 0). The non-periodic geometries are terminated ∂y by a field plate at the boundary y = t1 + t2 , which is held at a fieldplate potential ψ(x) = VFP (x). The periodic geometries have a periodic boundary condition along the line y = t1 + t2 and therefore require ∂ψ ∂y = 0 at this interface. The dielectric constants in both domains ε1,2 are assumed to be position independent. In both domains Gauss’ law needs to be obeyed: ∇ · D(x, y) = ρ(x, y),. (2.2). where D = εE is the electric displacement field and ρ is the charge density..

(32) Using E = −∇ψ, Poisson’s equation is obtained: ∇2 ψ(x, y) =. ∂2 ψ(x, y) ∂2 ψ(x, y) ρ(x, y) + =− . ∂x2 ∂y2 ε. (2.3). ρ(x, y) = ρ(x) = αx + β,. (2.4). with α and β being constants. A function ψ(x, y) satisfying (2.3), (2.1), the conditions ψ1 (0, 0) = 0 and ψ1 (L, 0) = BV, and (2.4) for any (x,y) is found to be: BV ρ(x)y2 ψ(x, y) = x− + c1 y + c2 , (2.5) L 2ε where c1 and c2 are integration constants. In other words, equation (2.5) describes exact ideal RESURF solutions of Poisson’s equation for charge distributions ρ(x) that are either constant or have a linearly graded doping concentration in the x-direction. This solution needs to be extended to both domains and suitable boundary conditions need to be found. Using 1 the symmetric boundary conditions from Fig. 2.2, ∂ψ ∂y = 0 at y = 0, the solution ψ1 (x, y) inside domain 1 is found to be: ψ1 (x, y) =. ρ1 (x) 2 BV x− y . L 2ε1. (2.6). This solution can be extended to domain 2 by using the continuity conditions at the interface between domains 1 and 2. These conditions ensure continuity of the displacement field perpendicular to the boundary and the electric field parallel to the boundary (see Fig. 2.2). When the interface is parallel to the x-axis (i.e., t1 does not vary with x), the potential ψ2 in domain 2 is given by: BV ρ1 (x) ε1 ρ2 (x) (y − t1 )2 . (2.7) ψ2 (x, y) = x− t1 t1 + 2 (y − t1 ) − L 2ε1 ε2 2ε2 It thus has been shown that equations (2.6)-(2.7) satisfy both Poisson’s equation and the ideal field condition throughout both domains. Moreover they satisfy the boundary conditions along the line y = 0 and the continuity equations at the interface y = t1 . By enforcing (2.6)-(2.7) to represent solutions of Poisson’s equation two challenges remain. Firstly, the outer boundary conditions at y = t1 + t2 need to be satisfied. This will be discussed in subsection 2.2.1 for non-periodic, field-plate assisted structures and in subsection 2.2.2 for periodic structures. Secondly, the boundary conditions ψ = 0 and ψ = BV on the left and right boundaries need to be satisfied for all y. This can be achieved by geometry shaping of the boundaries as described in subsection 2.2.3.. 17 CHAPTER 2. IDEAL RESURF GEOMETRIES. Potential distributions of the form ψ(x, y) = −(αx + β)f(y)/ε are consid2 f(y) = ρ(x, y). ered, which satisfy both equations (2.1) and (2.3) if (αx + β) ∂ ∂y 2 Since charge distributions with a zero or constant charge gradient are the most relevant for RESURF devices [14, 27–31] this chapter focuses on solu2 f(y) tions of the potential distribution ψ(x, y) with ∂ ∂y = 1 such that ρ(x, y) 2 is a linear function of x and is not a function of y:.

(33) 2.2.1. 18. Field-plate assisted RESURF. 2.2. DERIVATION OF THE IDEAL RESURF SOLUTION. In non-periodic structures the RESURF gradient in the y-direction is formed by a field plate. The field plate symmetrically terminates the structure at the top and bottom of the drift extension. In order to satisfy the boundary condition, the potential on the field plate needs to match that of the solution in equation (2.7), such that ψ(x, y)|y=±(t1 +t2 ) = VFP (x). Thus, for a field plate located at y = ±(t1 + t2 ), the field plate potential VFP (x) is obtained by substituting y = ±(t1 + t2 ) in (2.7) resulting in: VFP (x) =. ρ1 (x) ρ2 (x) BV x− teq (x)2 − t2 (x)2 , L 2ε1 2ε2. (2.8). where the equivalent thickness teq [27, 30] can be expressed in terms of t1 and t2 using: s 2ε1 teq (x) = t1 t1 + t2 (x) . (2.9) ε2. 2.2.2. Periodic RESURF. As an alternative to field plates, semiconductor domains with opposite ∂E charge density can be used to generate the gradient ∂yy . These periodic structures can be formed by alternating domains 1 and 2 in an infinite stack of domains with constant thicknesses 2t1 and 2t2 . Due to the repetitive, periodic nature of the superjunction stack, it is sufficient to show that the solution satisfies the boundary and continuity conditions at y = 0, y = t1 and y = t1 + t2 . If the structure is periodic in the y-direction, the boundary conditions at y = ±(t1 + t2 ) do not only require the continuity of the potential ψ(x, y)|y=±(t1 +t2 ) , but also of its y-derivative. From symmetry considerations, this is only possible if ∂ψ ∂y |y=±(t1 +t2 ) = 0. Applying this condition to (2.7) yields the well known charge balance condition [16]: ρ1 (x)t1 + ρ2 (x)t2 = 0.. (2.10). The equations (2.6)-(2.7) provide the RESURF solution in the field-plate assisted case together with (2.8), and describe the ideal potential distribution in the periodic domains for superjunction devices together with (2.10). In order to satisfy the ideal field condition the charge distributions in the periodic domains need to satisfy (2.10), which requires the sign of the doping charge to alternate between n-type and p-type. Therefore only superjunction devices can result in ideal periodic RESURF. In addition to superjunction devices, DIELER [32] devices will be discussed, since they represent another important type of periodic RESURF devices. In DIELER devices dielectric and semiconducting domains alternate in order to have a reduction in the slope Ex and increase BV. Since the fixed charge in the dielectric is assumed to be zero while that in the semiconductor is non-zero, DIELER devices cannot satisfy the charge balance equation (2.10) and ideal RESURF condition (2.1)..

(34) Exact solutions of Poisson’s equation for DIELER devices are shown below. For ρ2 = 0, since the RESURF is non-ideal, quadratic terms need to be added to equations (2.6)-(2.7). The following solution is found that satisfies (2.3) the boundary condition at all interfaces: =. ψ2 (x, y). =. (2.11). (2.12). After having satisfied the interface boundary conditions, the geometry shaping procedure in the next section will be applied in order to satisfy the boundary conditions at the left and right terminals for both periodic and non-periodic devices.. 2.2.3. Geometry shaping of the left and right boundaries. The left and right boundaries of the structure are curves in the x − y plane. They can be described by the parametric equation (x, y) = (xb (s), yb (s)), where xb (s) and yb (s) are the coordinates of the boundaries as a function of the position parameter s. The boundary potential ψb as a function of s is given by the equations (2.6)-(2.7): ψb (s) = ψ(xb (s), yb (s)).. (2.13). The potential ψb along the left (xb0 , yb0 ) and right (xbBV , ybBV ) boundaries of domain 1 is imposed to be a constant. In order to obtain boundary designs that satisfy this condition, a geometry shaping procedure is applied, which ensures that the boundaries run along an equipotential line of equation (2.6), as shown schematically in Fig. 2.3. Thus the shape of the left and right boundaries is found according to equation (2.13) by finding the equipotential lines (xb , yb ) that satisfy the following equations: ψ(xb0 (s), yb0 (s)) = 0 (a) . (2.14) ψ(xbBV (s), ybBV (s)) = BV (b) Some degrees of freedom are present in the choice of the shape on the left and right boundaries of domain 2. Suitable shapes can be chosen depending on the type of RESURF. In some cases equipotential lines as in equation (2.14) can be taken, in other cases a non-zero potential gradient will be present. In any case, ideal solutions are obtained as long as the boundary is shaped such that the potential along the boundary obeys equation (2.13). It should be emphasized that the shaping procedure described in this subsection is important for inducing 2D ideal RESURF solutions. Devices with straight boundaries at constant potential will not exactly obey equation (2.1) for non-zero doping ρ1 (see Sec. 2.5.1). After having derived ideal. 19 CHAPTER 2. IDEAL RESURF GEOMETRIES. ψ1 (x, y). BV ρ1 t 1 ρ1 2 x− [x2 − y2 ] − y L 2ε1 t1 + ε2 t2 2ε1 BV ρ1 t 1 x− [x2 − (y − t1 − t2 )2 ] L 2ε1 t1 + ε2 t2 ρ1 t1 t2 ε1 t2 + ε2 t1 . − 2ε1 ε1 t1 + ε2 t2.

(35) L. , �b. ,�b � b0. Domain 2. )=. BV. 0. ��. )=. 0. 2.3. EXAMPLES OF IDEAL AND DIELER RESURF STRUCTURES. V. � bB. �(. Domain 1. �(. 20. Figure 2.3: Schematic of an ideal RESURF structure example that can be derived from Fig. 2.2 using the geometry shaping procedure in Sec. 2.2.3. The left and right boundaries need to follow the shape of the equipotential lines in order to keep the potential distribution ideal. RESURF solutions, the next section will focus on providing examples of their implementation in several important cases.. 2.3. Examples of ideal and DIELER RESURF structures. In this section several examples of ideal RESURF device architectures are given (see also [27]). In order to design a structure that yields an exact solution of Poisson’s equation and satisfies the ideal RESURF condition (2.1) the following procedure is taken: 1. Choose BV and device length L, making sure that BV L is smaller than the critical field Ecrit (see Sec. 2.5.1) to prevent breakdown. 2. Choose the semiconductor thickness t1 . 3. For field plate RESURF: a) Choose one graded parameter ρ1 , t2 or VFP . b) Fix the other two (non-graded, constant) parameters. c) Determine the gradient (x-dependence) of the graded parameter using equation (2.8). 4. For periodic (superjunction) RESURF: a) Fix ρ1 (x). b) Choose t2 and ρ2 (x) to satisfy equation (2.10). 5. Shape the left and right boundaries according to equation (2.14) making use of (2.6)-(2.7)..

(36) 2. −2.5. 1 2.5. 2. 2. −2.5 2.5. 1 2. Vright2 (b) Vtop−bottom. 11.7 ε0 3.9 ε0 11.7 ε0 1.5 C/cm4 · x 4.9 C/cm4 · x 2.5 µm 2.5 µm 5 µm 0V 136.2 V 54.4 V/ µm· (t1 + t2 − y) 1.5 V/ µm2 · (t1 + t2 − y)2 + 50.6 V/ µm· (t1 + t2 − y) 0V. Figure 2.4: Potential distribution ψ(x, y) in a RESURF device with graded charge. a) Dielectric RESURF. b) pn junction RESURF.. This procedure is demonstrated for several cases in this section. The procedure captures most practical cases, but does not yield all possible types of solutions, since one might also consider to grade more than one parameter, or to grade t1 [33] or the dielectric constants ε [17]. It is noted that the analytical solutions of the potential (2.6)-(2.7) are found to be in exact agreement with numerical solutions of Poisson’s equations using COMSOL [34] within numerical accuracy. A further validation has been reported in earlier work [27] using TCAD simulations for solving the semiconductor equations.. 2.3.1. Field-plate assisted RESURF. By choosing one graded parameter in (2.8) (step 3a in the previous section), the ideal RESURF solutions are demonstrated in some significant cases: (1) graded doping in domain 1 ρ1 (Fig. 2.4), (2) graded field-plate potential VFP (Fig. 2.5), and (3) graded thickness t2 of domain 2 (Fig. 2.6). In each of the 3 figures the solutions are shown for dielectric RESURF (ρ2 = 0, subfigure a) and for pn junction RESURF (ρ2 6= 0, subfigure b). As can be seen, the equipotential lines are equidistant in the x direction, showing that the ideal RESURF condition (2.1) is obeyed throughout the 2D region in all cases.. 2.3.2. Periodic RESURF. Examples of periodic RESURF are shown in Fig. 2.7 for superjunction (Fig. 2.7a) and DIELER (Fig. 2.7b). As discussed in step 4 of the procedure in Sec. 2.3 no graded parameters are needed for ideal periodic RESURF. The charge densities ρ1 and ρ2 , thicknesses and field-plate potentials are therefore taken to be constant.. 21 CHAPTER 2. IDEAL RESURF GEOMETRIES. (b). ε1 ε2 (a) ε2 (b) ρ1 (a) ρ1 (b) t1 t2 L Vleft Vright1 Vright2 (a).

(37) ε1 ε2 (a) ε2 (b) ρ1 ρ2 (a) ρ2 (b) t1 t2 L Vleft Vright. 22. Figure 2.5: Potential distribution ψ(x, y) in a RESURF device with graded field-plate. a) Dielectric RESURF. b) pn junction RESURF. Notice that in the DIELER case in Fig. 2.7b the equipotential lines are not equidistant, meaning that the Ex field is not constant, but decays linearly in the x-direction (because of the quadratic term in ψ1 and ψ2 in (2.11)-(2.12)) and has a trapezoidal shape (as shown in Fig. 2.7b). However, the DIELER solution is better than the 1D case (which also has a linearly decaying field) since the slope of the field decay is lower (Fig. 2.8). As shown earlier [32]. y [µm]. (a). −2 −1. 2 1. 0 1 2 1. 2. 3 x [µm]. 4. 100 50. 2 0. 5. 0. (b) 120. 4. y [µm]. 2.3. EXAMPLES OF IDEAL AND DIELER RESURF STRUCTURES. Vtop−bottom (a) Vtop−bottom (b). 11.7 ε0 3.9 ε0 11.7 ε0 8 · 10−3 C/cm3 0 −8 · 10−3 C/cm3 0.5 µm 0.5 µm 5 µm 0V 136.2 V 27.2 V/ µm· (x − 2.5 µm) 27.2 V/ µm· (x − 0.93 µm). 2. 3 2 1. 100 80. 1. 0 1 2 3. 60 40. 2. 4. ε1 ε2 (a) ε2 (b) ρ1 ρ2 (a) ρ2 (b) t1 t2 (a) t2 (b) L Vleft Vright1 Vright2 (a). 20. Vright2 (b) Vtop−bottom. 11.7 ε0 3.9 ε0 11.7 ε0 0.4 · 10−2 C/cm3 0 −0.4 · 10−2 C/cm3 1 µm 0.24 · (x − 0.71 µm) −1 0.085 µm · (x − 0.71 µm)2 + 0.66 · (x − 0.71 µm) 5 µm 0V 136.2 V 126 V/ µm· (t1 + t2 − y) 1.94 V/ µm2 · (t1 + t2 − y)2 + 21.2 V/ µm· (t1 + t2 − y) 0V. 0 0. 1. 2. 3 x [µm]. 4. 5. Figure 2.6: Potential distribution ψ(x, y) in a RESURF device with graded domain 2. a) Dielectric RESURF. b) pn junction RESURF..

(38) Vtop−bottom (a) Vtop−bottom (b). 11.7 ε0 11.7 ε0 3.9 ε0 3.2 · 10−3 C/cm3 0 −8 · 10−4 C/cm3 0.1 µm 0.4 µm 1 µm 1.4 µm 0V 34.2 V 34.2 V/ µm· (x − 0.02 µm) −6.6 V/ µm2 · (x − 0.03 µm)2 + 33.82 V/ µm· (x − 0.03 µm). Figure 2.7: Potential distribution ψ(x, y) in a periodic RESURF device (three periods are shown). a) superjunction. b) DIELER.. and in Fig. 2.8, the decay rate of the field reduces as the ratio tt12 is decreased (at fixed ρ1 ). In other words, as the semiconductor domain gets thinner, the charge in this domain reduces for a given doping. Theoretically, it would require t1 = 0 in order to satisfy the charge balance condition (2.10) and ideal RESURF condition (2.1). It is worth mentioning that DIELER. Superjunctiona(Fig.a2.7a). DIELER (t1 = 0.05µm) DIELER (t1a=a0.1µm,aFig.a2.7b). Figure 2.8: Comparison between the Ex fields in ideal 2D RESURF (superjunction in Fig. 2.7a, green), non-ideal 2D RESURF (DIELER in Fig. 2.7b, solid yellow) and 1D pn junction (red). The dashed yellow line shows the Ex field in a DIELER structure having half of the thickness t1 compared to Fig. 2.7b.. 23 CHAPTER 2. IDEAL RESURF GEOMETRIES. ε1 ε2 (a) ε2 (b) ρ1 ρ2 (a) ρ2 (b) t1 t2 L (a) L (b) Vleft Vright.

(39) 24. structures can in principle satisfy (2.10) if the dielectric is non-ideal (i.e., it contains fixed charge) or there is trapped charge at the interface between the semiconductor and the dielectric layer. In DIELER and superjunction devices that do not satisfy (2.10) the Ex -field will show a non-zero gradient ∂ Ex ∂x .. 2.4. COMBINED RESURF STRUCTURES. 2.4. Combined RESURF structures. Besides achieving ideal RESURF by grading one parameter, one can also create combined devices. Combining different methods can be useful when the grading of only one parameter requires values that are difficult to achieve in real devices. Figure 2.9 shows a semiconductor-dielectric structure (with ρ2 = 0) where the graded-field plate, graded charge and graded dielectric thickness methods have been combined. Domain 1 is assumed to be an n-type semiconductor with doping concentration ND (ρ1 = qND , where q is the elementary charge). The compound device has been constructed by, in addition to the methods discussed in section 2.3, making sure that the potential is continuous at the interfaces I-II and II-III. Thus the device satisfies equations (2.1) and (2.3) throughout the 2D region.. Figure 2.9: Exact solution of the 2D potential distribution ψ(x, y) in a compound dielectric RESURF device consisting of three regions (I, II and III). Region I (LI = 3 µm) has a linearly-graded field-plate potential from VFP = 0 V to VFP = 67.2 V, ND = 5 · 1015 cm−3 and t1 = t2 = 0.5 µm. Region II (LII = 4 µm) has a linearly-graded doping from ND = 5 · 1015 cm−3 to ND = 7.8 · 1016 cm−3 , VFP = 67.2 V and t1 = t2 = 0.5 µm. Region III (LIII = 3 µm) has a linearly-graded domain 2 thickness from t2 = 0.5 µm to t2 = 1 µm, t1 = 0.5 µm, ND = 7.8 · 1016 cm−3 and VFP = 67.2 V. Leftright boundary potentials: Vleft = 0 V, Vright1 = 246.7 V, Vright2 = 67.2 V + 179.4 V/ µm · (t1 + t2 − y)..

(40) 2.5. Discussion. 2.5.1. Effect of deviations from ideal RESURF on BV. The curved design of the left and right boundaries needed for ideal RESURF increases the total device length along the x axis. In Fulop’s approximation [35] breakdown occurs at a critical field Ecrit = 1/71 1/7 , where Af. L. Af = 1.8 · 10−35 cm6 /V7 is the ionization coefficient (in silicon) and L is the device length. The breakdown voltage of an ideal device with 6/7 curved boundaries is then BV curved = Ecrit L = L 1/7 . If the device has Af. straight boundaries, however, for the same length L the device will have a lower breakdown voltage because the boundaries do not have the ideal shape. The breakdown voltage with straight boundaries can be given by BV BV straight = ηBV curved , where η = BVstraight is defined as the ratio of breakcurved down voltages of a device with straight boundaries and that of a device with ideally curved boundaries with the same length L. The parameter η depends on the device length, geometry and doping profile, and can be extracted in simulations by calculating the ionization integral along the symmetry line y = 0 (where the Ex -field is maximum). In Fig. 2.10 η is shown for a device with graded field-plate voltage and ρ2 = 0 as a function of the length L for different values of the fixed charge ρ1 in Fig. 2.10a) and of the equivalent thickness teq in Fig. 2.10b). It can be seen that η reduces for increasing ρ1 and increasing thicknesses teq (assuming t1 = t2 ). The. Figure 2.10: Ratio between straight and curved Ex breakdown voltage (η = BV straight /BV curved ) for an n-type dielectric RESURF drift extension with graded field-plate potential (as in Fig. 2.5a) having a) different doping charges ρ1 = qND and b) different thicknesses teq (with t1 = t2 ).. 25 CHAPTER 2. IDEAL RESURF GEOMETRIES. In Section 2.3, examples of ideal semiconductor-dielectric structures satisfying the RESURF condition have been shown. Deviations from ideal RESURF and other issues occurring in real devices are discussed in this section, which focuses on the shape of the boundaries (Sec. 2.5.1), linearly graded-potentials (Sec. 2.5.2), and premature breakdown (Sec. 2.5.3)..

(41) 26 2.5. DISCUSSION. reduced values of η in these cases are caused by the more pronounced curvature of the equipotential lines, which increases the difference between the curved and straight device designs and breakdown voltages BV. As the device length increases η approaches unity because boundary shape related effects become less significant for L t1 . The value of η is close to unity also for very short devices, since in the limit of t1 L the electric field will behave as in a parallel plate capacitor and the effect of curvature on BV becomes small. As a result, for the simulated devices in Fig. 2.10, the parameter η reaches a minimum for a device length L ≈ 1 − 5µm. This is a significant result since devices with drift lengths in this range have a breakdown voltage of BV ≈ 20 V − 100 V, which is typical in smart power and automotive applications [3].. 2.5.2. Boundary conditions with graded potential. A gradient is needed to achieve the optimal RESURF condition using the methods shown in Sec. 2.3. Grading the potential at the field-plate, dielectric boundaries and/or at the left and right boundaries is possible. In practice, graded potentials are not easily implemented. A possibility is to split the graded potential in a number of constant voltage field-plates [36], or to use conductive resistive elements [37]. It is also possible to exploit structural symmetries to achieve a graded potential on a boundary without a field plate. For example, the periodicity in the y-direction is exploited in superjunctions resulting in the charge balance condition (2.10). Similarly, a symmetric design around the x = L line can be used to mimic a linearly graded potential on the right boundary.. 2.5.3. Junction, vertical and dielectric breakdown. Besides breakdown caused by the Ex -field, device breakdown could also be caused by the Ey -field [27]. In order to arrive at an optimized device design, it is therefore necessary to design the RESURF device such that the ionization integral along the electric field lines in the y-direction is negligible compared to the x-direction. In addition, avalanche breakdown of the pn junction comprising the pwell (for an NMOS) of the power transistor and the drift extension has to be taken into account. As shown in [27], the condition ND (x = 0) · t1 6 1012 cm−2 [24] limiting the RESURF dose at x = 0 can be used for this purpose in silicon-based devices. In the presence of dielectrics, the magnitude of the electric field should not exceed the critical value for dielectric breakdown. Finally, it is worth mentioning that for electric field magnitudes exceeding 70 V/ µm in silicon band to band tunneling also limits the breakdown voltage [29, 38]..

(42) 2.6. Conclusions. 27 CHAPTER 2. IDEAL RESURF GEOMETRIES. In this chapter, 2D analytical solutions of Poisson’s equation have been derived that satisfy the ideal RESURF condition (2.1). Several examples of how these solutions can be used for ideally shaping the geometry of fieldplate and periodic RESURF devices have been demonstrated. In addition, an analytical solution for optimizing DIELER RESURF devices has been derived. The analytical solutions provide insight in the physics and facilitate device optimization. The different geometry shaping procedures demonstrate the degrees of freedom available for optimizing RESURF devices. Moreover, the derivation of the shape of idealized structures allows analysis of deviations from the ideal shape in practical devices. For instance, it is shown that devices with curved boundaries can have a higher breakdown than devices with straight boundaries. With sufficient technological control over device dimensions and doping profiles, the demonstrated device geometries with curved boundaries and field plates can lead to optimized RESURF drift extensions..

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(44) CHAPTER. B REAKDOWN VOLTAGE AND SPECIFIC ON - RESISTANCE Abstract This chapter focuses on the trade-off between the specific onresistance and the off-state breakdown voltage in RESURF power devices. Analytical equations are derived based on the RESURF theory presented in Chapter 2 to estimate the specific on-resistance as a function of the off-state breakdown voltage in an optimized RESURF drift extension. In order to provide equations that are independent of the device orientation with respect to the wafer plane, the on-resistance times volume (rather than times unit area) is considered. It is shown that a switchable field plate electrode acting on the drift extension can be used to further reduce the on-resistance without affecting the Ex -field distribution in the off-state. Applying a positive potential (in case of an n-type MOSFET) on the field-plate boosts the on-state performance by creating an accumulation layer in the drain extension which reduces the on-resistance. This concept is practically demonstrated in a silicon-on-insulator (SOI) Laterally Diffused MOS (LDMOS) transistor fabricated in NXP’s 140nm Advanced Bipolar CMOS DMOS (A-BCD9 [3]) technology which features a controllable field-plate electrode which is separated from the gate electrode. This device is referred to as the boost transistor. It provides a specific on-resistance Ron V reduction of 15% compared to the single gate device without requiring any process modification, as is demonstrated by measurements and TCAD simulations. The on-state power dissipation with respect to standard LDMOS designs is reduced and a driving circuit is proposed maintaining the breakdown voltage at the nominal value of 70 V in the off-state. This chapter was partly published in the ISPSD Proceedings [39]. For clarity it has been expanded with additional figures and explanations.. 29. 3.

(45) wafer reference frame. L = device length in the current flow direction (x) t = device thickness in the RESURF field direction (y) W = device width in the direction orthogonal to the x-y plane. Domain 2. Domain 2. 3.1. Ron V -BV TRADE-OFF IN RESURF DRIFT EXTENSIONS. Domain 1. Domain 1. Domain 2. t. Domain 2 Domain 1 Domain 2 Domain 2. 30. t. Figure 3.1: Wafer plane and possible spatial orientations for a 2D RESURF device. The half-thicknesses of each domain are denoted as t1 and t2 as in Fig. 2.2.. 3.1 Ron V-BV trade-off in RESURF drift extensions In order to improve the performance of power transistors, the specific onresistance Ron A has to be reduced without affecting the off-state breakdown voltage BV [? ]. In this section, the trade-off between Ron A and BV of the elementary RESURF configurations shown in Sec. 2.3 are analyzed. For this purpose, non-ideal RESURF devices with straight electrodes are considered using the parameter η defined in Sec. 2.5.1 for calculating the breakdown voltage BV straight . The specific Ron A (and therefore the Ron A − BV trade-off) depends on the orientation of the device with respect to the plane of the wafer. In order to provide equations that are independent of the orientation of the device, the product between the on-resistance Ron and the device volume V (V = W · L · t, see Fig. 3.1) is considered and defined as Ron V. From Ron V it is possible to derive Ron A for different device orientations with respect to the wafer plane. The device dimensions are defined as follows: L is the device length in the direction of the current flow (x-direction, see Fig. 2.2), t is the device thickness in the direction perpendicular to the interface plane between layer 1 and layer 2 (y-direction), and W is the device width in the z-direction perpendicular to the x-y plane. The wafer plane is named the xw -yw plane, and zw is the direction perpendicular to it. As shown in Fig. 3.1, three possible device orientations are possible for a 2D device (assuming that the wafer directions xw and yw are equivalent). 1. Lateral device with out-of-plane RESURF: x = xw , y = zw and z = yw [9, 39]. The device area is named ALk = tVav = W · L, where tav is the.

(46) average device thickness along the length L in the x-direction. 2. Lateral device with in-plane RESURF: x = xw , y = yw and z = zw V [32]. The device area is named AL⊥ = W = L · tav . 3. Vertical device: x = zw , y = yw and z = xw [40]. The device area is named AV = VL = W · tav .. Af. where t1 and t2 are half the thicknesses of domains 1 and 2, respectively (see Fig. 2.2). The parameter η represents the ratio between the off-breakdown voltage of a real device with straight boundaries and that of an ideal device with curved boundaries (see Section 2.5.1). Using the definitions (3.1), the Ron V trade-off is estimated for the elementary RESURF structures presented in Sec. 2.3. In order to analytically evaluate the conductance σeff in all cases, it is assumed for simplicity that the mobility µn is independent of the doping charge (ρ1 = qND for an n-type semiconductor and ρ1 = qNA for a p-type semiconductor, where q is the elementary charge and ND and NA are the ionized donor and acceptor concentrations, respectively). The Ron V expressions for field-plate assisted RESURF are:  Af 1/3  7  t2 η 7/3  (graded VFP ) R V = 1 +  on  µn ρ1 t1 · BV  !  Af 1/3 t  teq 2 1+ t2 η7 BV 1 Ron V = ln 1 − BV 4/3 (graded ρ1 ) . ρ2 t2 2ε1 µn 2  V + FP  2ε2   Af 7/3   7  t (BV) Ron V = η 1 + 2,avt1 · BV 7/3 (graded t2 ) µn ρ1 (3.2) The Ron V expressions for periodic RESURF are:  Af 1/3  7  Ron V = ηµn ρ1 1 + tt12 · BV 7/3 (superjunction) . (3.3)  t2 2 Ron V = 1 (DIELER) 1 + · L(BV) µn ρ1 t1. CHAPTER 3. BREAKDOWN VOLTAGE AND SPECIFIC ON-RESISTANCE. In a lateral device, the current flows parallel to the wafer plane, in a vertical device it flows perpendicular to it. Out-of-plane RESURF means that the RESURF field Ey in Fig. 2.1 acts in the direction perpendicular to the wafer plane, while in-plane RESURF means that Ey is in the wafer plane. In a vertical device, the RESURF field is always in-plane. The following definitions are introduced:  RL  t2,av = L1 0 t2 (x) dx      V = W · L · 2t1 · 1 + tt2,av   1     Aflow = 2t1 · W    −1 R L σeff = L1 0 µn ρ11 (x) dx , (3.1)    L  Ron = σeff A   flow  2    Ron V = σLeff · 1 + tt2,av  1    BV = η L6/7 1/7. 31.

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