Adding functionality to microchips by wafer post-processing
Jurriaan Schmitz
*MESA+ Institute for Nanotechnology, Semiconductor Components, University of Twente, P.O. Box 217, 7500 AE Enschede, The Netherlands.
Elsevier use only: Received date here; revised date here; accepted date here
Abstract
The traditional microchip processes, stores and communicates electrical information. Here we review an emerging class of microchips that have additional functionality through extra integrated components in the chip. In the final manufacturing stage, layers are added on top of the chip, with a specific property such as sensitivity to ionizing radiation. This paper reviews the technology underlying these monolithic microsystems, including the incorporation of new materials, the unconventional application of photoresist layers, and low-temperature technology for suspended membranes. The manufacturing of exemplary microsystems, such as the active pixel sensor and liquid-crystal-on-silicon, is detailed. A new class of fully integrated radiation imaging systems is now technologically within reach. © 20216 Elsevier Science. All rights reserved
Keywords: CMOS; microfabrication; microsystems; radiation detectors; particle detectors; radiation imaging. PACS: 29.40.-n; 85.40.-e; 85.60.Gz; 87.59.-e
1. Introduction
The skill required to make an integrated circuit has developed fast since 1959 when Hoerni and Noyce invented planar technology [1][2]. A strongly growing market for silicon-based integrated electronics paved the way for countless engineering improvements, and present-day integrated circuits are fabricated with a dazzling amount of skill. For instance, a contemporary PC microprocessor chip hosts around 108 transistors. Each of these transistors can perform within tight specifications for 10 years. Compared to natural production processes, such as the growth of plants from seeds, the probability of success when making a transistor is beyond imagination.
These technological skills are mainly employed for the manufacturing of components that process and store (electrical) information. Yet, microtechnology allows us to create many other devices and systems, best illustrated by the achievements of the MEMS community. Pressure sensors, accelerometers, ink-jet heads and hard disk drive heads are appealing examples of micromanufactured components. More recently, a considerable research effort is initiated towards lab-on-a-chip and biochip applications [3][4].
Some of today’s most successful microsystems combine a conventional integrated circuit with sensing or actuating functions, offered by adding manufacturing steps at the end of the microchip fabrication stage (“wafer post-processing”, see figure 1). This paper reviews this class of microsystems and sketches the perspective of this
fabrication style for radiation imaging detectors.
Figure 1: conceptual wafer post-processing sequence.
After motivating the wafer post-processing approach, the underlying manufacturing techniques are summarized. Then, a selection of successful sensing and actuating microsystems is treated, with emphasis on the technology
* Tel.: +31 53 4892726; fax: +31 53 4891034; e-mail: j.schmitz@utwente.nl. Internet: http://sc.ewi.utwente.nl .
a. Chip fabrication b. Post-processing c. Wafer dicing a. Chip fabrication a. Chip fabrication b. Post-processing b. Post-processing c. Wafer dicing c. Wafer dicing
aspects. The paper concludes with a perspective of wafer post-processing as a manufacturing approach for radiation imaging detectors.
2. Wafer post-processing
In a conventional integrated circuit process, the silicon wafer is finished after the upper metallization layer is patterned and partly covered by a scratch protection layer. It is then diced (the wafer is physically divided into chips) and chips are mounted into their package. When the wafer is taken out of this process sequence before dicing, additional thin films can be deposited and patterned on top, when a set of processing rules is carefully obeyed. Of course, newly added layers should adhere well and survive subsequent processing. Additional, important guidelines at the end of the metallization stage are:
The wafer temperature should not exceed 425-450 °C, or the pre-existing metallization will degrade through various mechanisms [5];
When a plasma process is employed, the risk of charging of the MOS transistors should be assessed [6] [7];
Additional layers on the wafer should not increase the mechanical stress beyond the point where device and interconnect functionality are affected [8]-[10];
The hydrogen passivation in the MOS transistors should not be disrupted, or alternatively be restored at the end of the process (normally by a forming gas anneal around 400 °C) [11].Here we assume that CMOS is the IC technology of choice for post-processing; but the approach can be employed just as well on other IC technologies like BiCMOS and DRAM. Replacement of the standard metal interconnect by tungsten wiring does increase the thermal limit to ~600 °C [12], but this is a highly disruptive change, affecting the full chain of manufacturing, circuit design, and reliability.
Naturally, to achieve a high yield in manufacturing, one should also obey the best practices of integrated-circuit (IC) fabrication such as the application of high purity materials, regular wafer inspections, and the avoidance of particles and scratches. Baltes et al. gave practical guidelines for the construction of microsensors on a CMOS chip [13], also proposing to stick to the materials regularly used in CMOS fabrication lines. Fortunately, IC manufacturers are introducing new materials at a rapid pace [14], so many materials can be considered even with this constraint. Moreover, when post-processing of wafers takes place in a different manufacturing line than the CMOS formation, the engineer has a wider freedom of choice for materials.
3. Motivation for post-processing
Functions can be added to a CMOS chip in various ways. The chip can simply be electrically connected to a peripheral device, such as a discrete pressure sensor, silicon drift detector or audio microphone. A monolithic approach, i.e. one where all functions are integrated on a single piece of silicon, has several advantages over such a hybrid-assembled system:
Miniaturization offers better performance in terms of sensitivity, speed, and power efficiency in many practical systems;
Planar technology allows a high density of very close by, short electrical connections between the micro-electronics and the other components;
The system will have a small mass and volume;
The fabrication methodology and infrastructure are very advanced, which leads to fast process tuning, high yield, and low additional cost.For most of the microsystems discussed in section 5 of this paper, the monolithic approach is the only viable one to realize a commercially attractive product with competitive specifications.
When creating such a monolithic system, functionality can be added in silicon before, during or after CMOS formation (dubbed pre-CMOS, intermediate processing and post-CMOS). The literature reports on examples of all three – see [15] for further references. Here, the choice is to focus on the post-CMOS approach. CMOS fabrication takes place in a well-shielded environment, where experimentation would go at the expense of productivity and yield of the fabrication line, posing an economic risk. After finishing the CMOS, the wafers can go anywhere (including R&D plants and academic research laboratories) and receive all sorts of treatments without interfering with this IC manufacturing line. Facilities with smaller wafer diameters can be utilized in this scheme when small wafers are cut out of larger ones (even single-chip post-processing is an option, be it at increased piece cost). This routine would not work in a pre-CMOS or intermediate-processing approach. Today, many companies provide MEMS foundry service on silicon wafers, offering a complete infrastructure for post-processing.
It should be noted that wafer post-processing also bears the promise to revolutionize the manufacturing approach of traditional IC’s, through 3-D stacking of integrated circuits, and wafer-level packaging. These topics are beyond the scope of this paper. Several good review papers exist on both subjects; the reader is referred to [16] and [17] for an overview on 3-D interconnect and [18] for a review on wafer-level packaging.
4. Post-processing steps
A finished CMOS wafer has received a hydrogen anneal, typically at 400-450 ºC in forming gas (at atmos-pheric pressure). It is covered with a scratch protection film (usually Si3N4 of several hundred nanometers thickness) that is removed only at the bond pads (Figure 2).
Figure 2: cross-sectional view of an IC after the final wafer-level fabrication step.
It then goes to electrical test and dicing, unless we pull it out of the fabrication line for post-processing. Deposition and patterning of metals and insulators can be continued just as in the last IC fabrication steps. Figure 3 shows a simple example, where a wafer with Medipix2 microchips [19] fabricated in standard 0.25-µm technology is post-processed in the MESA+ clean room. The bond pad array, designed for bump bonding, is modified (using lift-off Al deposition1) to have a larger metal coverage (from 20% to 83%), enabling the use of this chip as a direct anode in a gaseous particle detector [20].
Figure 3: Top-view photographs of 12 Medipix2 pixels, before (left) and after (right) lift-off aluminum deposition. Experimentation by A. A. I. Aarnink (MESA+), picture reprinted from [21].
A wide range of solids can be added in this stage, not only those employed in standard VLSI technology. Dielectrics with excellent insulating properties can be 1 Lift-off was chosen (in spite of its yield issues) to avoid
modification of the chip’s peripheral bond pads.
formed using chemical-vapor deposition (CVD) methods, like ECR-CVD [22][23], ICP-CVD or atomic layer deposition [24]. Metal oxides and perovskites are deposited using low-temperature deposition techniques such as sputtering [25], metalorganic CVD [24], laser ablation [26] or atomic-layer deposition. Sputtered polycrystalline AlN, by merit of its piezoelectric behaviour, is being investigated for high-Q resonators [27].
Polycrystalline and amorphous semiconductors are deposited with various techniques, such as plasma-enhanced CVD or liquid-bath deposition [28]. To employ these semiconductors for devices such as diodes or transistors, n- and p-type regions are to be created. If the semiconducting film is not in-situ doped, either a low-temperature doping technique such as laser annealing can be followed, or Schottky junctions [2] can be formed. Decades of research on thin-film transistor technologies have brought us various complete low-temperature manufacturing processes for electronic components. In recent years this work is further leveraged through attempts to fabricate high-quality electronics on plastic substrates [29].
For conducting layers, several techniques such as sputtering, vapor phase deposition and electroplating can be employed. Integration schemes have been developed for a wide range of metals, such as Al, W, and Cu for standard VLSI interconnect [5][14]; and for magnetic, ferro-electric and phase-change materials for novel solid-state memories [30]-[32]. As aluminum is poisonous to living cells, other metals such as gold, (black) platinum and palladium are employed on the top surface of a biochip. So-called through-wafer vias can connect the metallization through the silicon substrate (see [33] and references therein), enabling very compact mounting of chips in a package, and e.g. chip stacking.
Some photoresists with a high glass temperature, such as parylene2 and SU-8 [34]-[36], are suitable as a constructive material. Polymer thin films also find application in CMOS and CCD imagers, both as microlens material and as color filters (with the appropriate addition of a dye or pigment). Organic semiconductors find applications in organic light emitting diodes (OLEDs), and on microchips for microdisplays [37].
It must be noted that the top layers of an integrated circuit are normally not planar; yet, a flat wafer is more easily post-processed. Non-planar substrates complicate spin coating, the step-coverage and patterning of deposited layers, and may conflict with the limited depth-of-focus of lithography. Chemical-mechanical polishing is a conven-ient planarization technique at this stage [38]; also, one may apply planarizing thin films [39]. For optical functionality such as in LCoS systems (see section 5),
2 Properties of Parylene, Parylene Coating Services.
[Online]. Available: http://www.paryleneinc.com transistors bondpad interconnect silicon scratch protection transistors bondpad interconnect silicon scratch protection
flatness is even more important, and additional measures are taken [40].
While suspended membranes are not available in standard VLSI processes, many sensing and actuating microdevices rely on such membranes. They are employed e.g. in accelerometers [3], the Digital MicroMirror Device™ [41], on-chip microphones [42], and capacitive micromachined ultrasonic transducers [43]. Suspended membranes are conventionally formed by depositing several thin films on top of each other, after which one of the lower films is selectively removed by etching [3]. Typically, in surface- or bulk-micromachined MEMS devices silicon, Al, Si3N4 and SiO2 are used for this purpose, the latter two being LPCVD-deposited at high temperature (around 700 ºC). For post-CMOS fabrication of a suspended membrane, the temperature must remain low. Existing interconnect layers (aluminum or intermetal dielectric) can be selectively etched, or even the silicon substrate can be attacked in this stage, from front or back sides – while the overlaying thin films are released. A more recent, low-temperature approach for suspending a membrane is to apply photoresist [41] or polyimide [44] as the sacrificial layer. When the demands on mechanical properties of the suspended membrane are high, only a few low-temperature materials presently qualify, such as nickel [45] and silicon-germanium [46].
To pattern thin films in post-processing the conventional approach, using photolithography and wet or dry etching, is suitable. However, this requires an etching recipe for the thin film, with sufficient selectivity towards photoresist and the underlying film. This recipe is not always available (or not practical for other reasons). In that case, shadow-mask deposition, lift-off lithography or damascene-patterning can be applied instead. Ion-milling is less attractive because of its violent nature and poor selectivity. Ink-jet printing also allows the local deposition of some materials such as polymers [47].
Not any sequence of manufacturing steps will form a functional device. In many cases, thin films affect each other. Materials in direct contact with each other should adhere, but not intermix or corrode. The residual stress in thin films can influence the properties of other films. A suspended membrane is normally released only in the very final stage of device manufacturing, because it is fragile after release. Hydrogen is a necessary ingredient for the MOS transistor; yet, it can ruin ferroelectric materials [48] [49], and therefore combining these two is not straightforward. The interplay of thin films and their compatibility with the CMOS substrate require a great deal of attention in the research and development stages. 5. Wafer post-processed microsystems
When a microchip is the physical basis for a microsystem, the functional demands for the electronics
define its dimensions, in combination with the process generation. The other functions of the chip, such as sensing or actuating functions, preferably should fit in the given area. This limits the system design freedom, for instance to make a display with a post-processed IC. Such displays are either very small (for viewfinder and headset-type applications) or they are used in a projection system, where the light beam is magnified after the microsystem.
In this section, we will first describe three commercialized display microsystems: the Digital MicroMirror Device™, Liquid-Crystal-on-Silicon, and the organic-LED microdisplay. All three can be considered microchips with a two-dimensional array of actuators. Then, radiation-imaging detectors are addressed, ranging from the CMOS active pixel sensor to a variety of detectors from infrared to X-ray photons, as well as high-energy charged particle tracking microsystems.
5.1. The Digital MicroMirror Device
The Digital MicroMirror Device™ (DMD) [41] is used for projection display systems such as high-definition television and cinema. It consists of a two-dimensional array of moving mirrors on top of a CMOS microchip. Each of the mirrors is held in position by hinges and a yoke, and has two stable positions. The microchip switches the mirror between these positions by electrostatic forces from a bit stored in an SRAM memory cell underneath the mirror.
A 0.8 µm CMOS technology is used as a basis – only 5 V is required to switch a mirror. After planarization (using chemical-mechanical polishing), the hinges, yokes and mirrors are formed in subsequent deposition and patterning steps. The mirror is released just before wafer dicing by dry-etch removal of a sacrificial photoresist layer. Tests showed that the mirrors survive over 1012 switching cycles, as well as shocks, vibration, and high temperatures [50]. Large-scale manufacturing of these microsystems follows the logistics of wafer post-processing. The MicroMirror is fabricated in a planar technology process involving surface micromachining. It takes place well below 400 °C to protect the underlying chip. The custom-developed device package is hermetic and features an optical window and a moisture getter.
5.2. Liquid-Crystal-on-Silicon
A competing technology to the DMD’s is Liquid-Crystal-on-Silicon (LCoS) [51]. LCoS microsystems combine a microchip with a liquid crystal reflective display (Figure 4). The microchip addresses the liquid crystal pixels: a driving voltage of a few volts suffices to change the polarization. Incoming light will be absorbed or passed by an external polarizer, depending on the polarization state of the liquid crystal in a pixel.
The bottom electrode of each liquid crystal pixel is formed in the upper metallization layer of the microchip. Wafer post processing consists of the preconditioning (rubbing) of the surface to enforce a specific orientation of the liquid crystal, and the definition of pillars that define the height of the liquid crystal volume. The system is completed by the mounting of a glass plate with transparent electrodes on top, and filling the gaps with the liquid crystal [52]. Special methods (including spacers) were developed for the parallel placement of the glass plate and the liquid crystal fill step, carried out under vacuum ambient using capillary forces.
Figure 4: cross section view of a nematic- liquid-crystal-on-silicon microsystem. The figure is not to scale: the liquid crystal is a few micrometers thick, its molecules a few nanometers; the glass cover plate measures hundreds of micrometers. It is covered by a transparent electrode material such as indium-tin-oxide [53].
5.3. Organic-LED microdisplay
Both display systems mentioned above are reflective. The organic-light-emitting diode (OLED) display [54] emits light, allowing a much simpler integration into a portable device. An array of white-light-emitting diodes is formed on top of a microchip at low process temperatures using organic semiconductor material and transparent top electrodes, see Figure 5. For color displays, color filters are added to create red, blue and green pixels (or cyan, magenta and yellow in some cases). OLEDs have long suffered from stability issues, but acceptable lifetimes for some applications are now reported [55]. Hermetic packaging can effectively suppress environment-induced device degradation, but the cause and solution to intrinsic degradation of the organic diodes remain to be found.
Figure 5: Cross section of an organic light-emitting diode microdisplay, after [37]. The OLED stack consists of 4-5 thin organic films.
5.4. Visible light imagers: CMOS-APS
The Active Pixel Sensor (APS) or CMOS imager is a microchip that captures, stores and processes color images. It challenges Charge-Coupled-Device technology in its consumer market, originally by competing in cost, size and system power consumption [56], but nowadays even in imaging performance [57]. The device utilizes the intrinsic light-sensitivity of silicon diodes. As diodes are omnipresent in standard CMOS (and other integrated circuit technologies), a two-dimensional array of light-sensitive pixels is readily designed. Typically, each pixel further contains three or four transistors for reset and readout. As these transistors and the inevitable wiring take up some area in the pixel, only part of the pixel (called the fill factor) is fully light sensitive.
A cross-sectional view of a typical CMOS active pixel sensor is shown in Figure 6. Standard electronics are supplemented with color filters and microlenses, manufactured in a wafer post-processing stage, on top of the interconnect. Organic color filters are the most commonly applied solution to separate colors (other techniques are possible, see e.g. www.foveon.com and [58]). The microlenses focus incoming light to the sensitive part of each pixel, enhancing the fill factor and reducing optical crosstalk. The standard dielectric materials in CMOS interconnect are sufficiently transparent to visible light. To suppress unwanted signal from infrared radiation, an infrared filter must be added to the chip. It is usually mounted rather than integrated.
Alignment of the color filters and microlenses with the underlying photodiodes is straightforward by the choice of wafer post-processing. Yet it would pose an enormous technical challenge if this system were to be assembled.
Figure 6: cross section of a CMOS active pixel sensor, showing three pixels and the optical path. The multilevel interconnect stack is partly left out for clarity.
Standard CMOS can be used for an APS sensor, but dedicated CMOS processes do exist. Minor modifications to the CMOS fabrication process can enhance the photoresponsivity and suppress the dark current, measures Upper interconnect Liquid crystal Transparent electrode Glass cover plate Upper interconnect Liquid crystal Transparent electrode Glass cover plate Upper interconnect OLED stack Protective layer Transparent electrode color filters Upper interconnect OLED stack Protective layer Transparent electrode color filters microlens color filters photodiode microlens color filters photodiode
that are especially beneficial in deep-submicron CMOS technologies [59]. The large consumer market for digital still cameras makes such a tailored CMOS process viable.
The APS sensor can be tailored (by circuit design and a different silicon wafer choice) for subatomary particle detection, a development dubbed MAPS [60]. In this particle detector, the sensing element is a part of the silicon wafer, resulting in very low input capacitance of the front-end amplifier and therefore extremely low noise compared to assembled systems. Because of the low noise, the demands on signal strength are less stringent, giving new design freedom for the sensing pixel. The color filter and microlens technologies have no use in this APS, so unmodified standard CMOS can be applied (on special silicon substrates).
5.5. Integrated infrared imaging detectors
The APS sensor can also be employed for the detection of infrared light up to wavelengths around 1 µm. Silicon is transparent to longer wavelengths; photons with λ > 1.1 µm have insufficient energy to form electron-hole pairs in this semiconductor. In the 1-8 µm range, infrared detectors are normally based on the creation of electron-hole pairs in semiconductors with a reduced bandgap, such as Ge, InSb, InGaAs and HgCdTe. Thermal generation of electron-hole pairs rises steeply as the bandgap diminishes, and therefore these detectors must operate well below room temperature to suppress the dark current. Moreover, the semiconductor must be monocrystalline with a low defect density. This latter requirement prohibits the construction of a far-infrared detector using CMOS post-processing as described in section 2. The upper surface of a finished CMOS chip is amorphous; epitaxy on such a surface will not lead to high-quality monocrystalline material. The silicon crystal could be used as a template for epitaxy after etching through the interconnect stack [61], but the preference in VLSI processing for (100) oriented silicon complicates this approach (see e.g. [62]). Hybrid assembly, connecting a CMOS readout chip through bump-bonds to a separate slab of sensing semiconducting material [63], is a more straightforward solution3.
However, in the 100 µm – 1 mm wavelength range bolometry [64] is an attractive sensing technique. Monolithic bolometric imaging sensors were established in the late 1990s [65] and are commercially available. They show attractive properties such as low mass and power consumption, low cost, and room temperature operation. The microbolometer most commonly consists of an array of tiles that act both as absorber and detector, their temperature rise being revealed by a resistance change. Various materials have been successfully applied for the 3 An advanced approach of hybrid assembly using
3D-inte-gration techniques is pursued in the RELAXD project: see
www.nikhef.nl/pub/experiments/medipix/relaxd.html .
sensing tiles, including semiconducting [66]-[68], metallic [69][70], and metal-oxide thin films [71]. The experimentation in this field and subsequent commercialization has proven the integration potential of many solid-state materials onto VLSI circuits.
5.6. X-rays and high energy charged particles
The detection of X-rays and high energy charged particles has its own challenges. Solid-state detectors and gaseous detectors are commonly applied, depending on the application’s requirements. Both can provide position, energy and arrival time information for single particles. They find application in medical systems, astronomy and professional instrumentation (e.g. XRD and XRF equipment [72][73]), as well as in nuclear and high-energy experiments. For a review of X-ray imaging spectrometers we refer to [74]; Heijne [75] has reviewed tracking detectors for high-energy physics, describing the potential of novel microchip manufacturing techniques in these detectors.
The SIAM collaboration has worked on a good example of an ionization imaging detector using wafer-scale processing [76], focusing on minimum-ionizing particles and X-rays. It was shown by this research team that a high-quality amorphous hydrogenated silicon (a-Si:H) layer deposited on top of a readout integrated circuit acts as a sensing material for X-rays or other forms of ionizing radiation. (This approach was earlier investigated for visible-light imaging, see [77] and references therein.) The underlying chip directly reads out each pixel of an array of p-i-n diodes formed in the a-Si:H layer, potentially leading to much higher sensitivity per channel than in many hybrid systems. A wide range of semiconducting materials can be deposited on a sensing chip, so there is plenty of opportunity for further experimentation in this field.
The monolithic gaseous detector, as the ultimate miniaturized multiwire proportional chamber, is presently under active investigation. The path led from the pioneering work of Anton Oed on microstrip gas counters [78] via various micro-pattern gas detectors (e.g. CAT [79], Micromegas [80], and GEM [81]) to the GOSSIP-concept [82]. GOSSIP (Gas On Slimmed SIlicon Pixels) is a monolithic gaseous detector. A microchip with front-end readout electronics is used as a direct anode in a detector gas volume [21][83], and perforated electrodes are positioned on top with wafer post-processing [84]. The result is a cheap, easily manufactured tracking detector with a wide range of foreseen applications, such as X-ray detectors, time-projection chambers and tracking detectors for high-luminosity collider experiments. Fabrication requires a clean room with SU-8 photoresist technology and low-temperature metal deposition. The radiation hardness of SU-8 [85] and deep-submicron CMOS is established. However, sparking resistance and ageing, common concerns in micropattern gas detectors, are still
under investigation. If long-term stable operation is demonstrated, this detector may challenge state-of-the-art silicon pixel detectors in terms of power consumption, mass and simplicity.
6. Perspective on radiation imaging
While silicon offers VLSI microchips, it is not the best active material for sensing radiation. Some imaging detectors require a high stopping power (for efficient X-ray conversion), others a high bandgap (for low dark current) or alternatively a very low one (for infrared imaging) [86]. For tracking, a silicon sensor embodies much more material (in terms of radiation lengths) than gaseous detectors. When high-purity silicon is employed (to achieve large depleted areas), the substrate price can become prohibitive and VLSI can no longer be manufactured on the same wafer. Besides, the high purity leads to hard-to-maintain demands on assembly and operation, through effects like metallic contamination and type-inversion. The alternative approach highlighted here, is to add sensitive layers above the electronic layers in wafer post-processing. A wider choice of materials then becomes available and the fabrication process can be optimized in small-scale laboratories, outside the clean rooms used for deep-submicron CMOS manufacturing. By using standard-CMOS as a backbone, once the detector configuration is chosen, large-scale manufacturing of the entire detector system is quickly set up. The semiconductor industry welcomes such new systems, because they can help to maintain a market for the older CMOS process generations.
Moreover, now that several pixel-organized sensing ASIC’s have been realized (e.g. the readout chips realized by the Medipix, ATLAS [87] and CMS [88] collaborations, and by INFN [89]), these microchips can be utilized as-is for proof-of-concept studies on wafer post-processing. The considerable investment for design and fabrication of a new ASIC can thus be re-used.
7. Conclusions
Advances in integrated circuit manufacturing have brought us to a point where a wide range of microsystems can be produced by wafer post-processing. The commercial success of the Digital MicroMirror, CMOS active pixel sensors and Liquid-Crystal-on-Silicon has shown that the technical challenges for these microsystems can be overcome. Given the broad range of post-processing techniques now available, opportunities lie ahead for the manufacturing of various monolithic radiation imaging microsystems. MAPS sensors, the detectors of the SIAM collaboration and the GOSSIP technology represent only a few of the many possibilities in this broad emerging field.
8. Acknowledgements
Post-processing CMOS requires the scientific knowledge and skills of a multidisciplinary team, and open-minded discussions with many people. I would like to thank my colleagues at the Semiconductor Components group of the University of Twente for their contributions to our research program, the Detector R&D group at NIKHEF Amsterdam, and the many colleagues at the University and at Philips Research for our fruitful discussions. The Dutch Technology Foundation STW made this work possible through funding the projects TEL.6358 and TET.6630. References
[1] R. N. Noyce, US Patent 2981877, applied 30 July 1959. [2] S. M. Sze, Semiconductor devices; physics and technology, John
Wiley and sons, New York 1985.
[3] Marc J. Madou, Fundamentals of Microfabrication, 2nd edition, CRC press, Boca Raton 2002.
[4] Special issue on Microelectromechanical Systems, Proc. of the IEEE 86 (8), August 1998.
[5] S. Wolf, Silicon processing for the VLSI era, Vol. 2: process integr-ation, pp. 267-269, Lattice Press 1990.
[6] I.-W. Wu, M. Koyanagi, S. Holland, T. Y. Huang, J. C. Mikkel-sen, Jr., R. H. Bruce, and A. Chiang, J. Electrochem. Soc. 136 (6) pp. 1638-1645, 1989.
[7] Kin P. Cheung, Plasma Charging Damage, Springer 2000. [8] S. M. Hu, J. Appl. Phys. 70 (6) pp. R53-R80, 1991.
[9] J. T. Yue, W. P. Funsten, and R. V. Taylor, Proc. IEEE IRPS p. 126-137, 1985.
[10] A. Hamada, T. Furusawa, N. Saito, and E. Takeda, IEEE Trans. El. Dev. 38 (4) pp. 895-900, 1991.
[11] J. D. Plummer, M. D. Deal and P. B. Griffin, Silicon VLSI Technol-ogy, Prentice Hall, Upper Saddle River 2000.
[12] J.M. Bustillo, G. K. Fedder, C. T.-C. Nguyen and R.T. Howe, Micro-syst. Technol. 1 pp. 30-41, 1994.
[13] H. Baltes, O. Paul and O. Brand, Proc. Of the IEEE 86 (8) pp. 1660-1678, 1998.
[14] International Technology Roadmap for Semiconductors, 2005 edition, see www.itrs.net.
[15] H. Baltes and O. Brand, Sensors and Actuators A 92 pp. 1-9, 2001. [16] K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, Proc. IEEE 89
(5) pp. 602-633, 2001.
[17] J. D. Meindl, IEEE Micro 23(3) pp. 28-35, 2001.
[18] P. Garrou, IEEE Trans. Adv. Packag. 23 (2) pp. 198-205, 2000. [19] X. Llopart, M. Campbell, R. Dinapoli, D. San Segundo, and E.
Perni-gotti, IEEE Trans. Nucl. Sci. 49 (5) pp. 2279-2283, 2002. [20] M. Campbell, M. Chefdeville, P. Colas, A.P. Colijn, A. Fornaini,
Y. Giomataris, H. van der Graaf, E.H.M. Heijne, P. Kluit, X. Llopart et al., Nucl. Instr. Meth. A540 pp. 295-304, 2005.
[21] P. Colas, A.P. Colijn, A. Fornaini, Y. Giomataris, H. van der Graaf, E.H.M. Heijne, X. Llopart, J. Schmitz, J. Timmermans and J.L. Vis-schers, Nucl. Instr. Meth. A535 pp. 506–510, 2004.
[22] G. I. Isai, J. Holleman, H. Wallinga and P. H. Woerlee, J. Electro-chem. Soc. 151 (10) C649-C654, 2004.
[23] G. I. Isai, J. Holleman, H. Wallinga and P. H. Woerlee, J. Vac. Sci. Technol. B 22 (3), pp. 1022-1029, 2004.
[24] J. E. Crowell, J. Vac. Sci. Technol. A 21(5) pp. S88-S95, 2003. [25] N. Inoue, T. Nakura, and Y. Hayashi, Proc. IEEE IEDM, pp.
[26] O. Nakagawara, Y. Toyota, M. Kobayashi, Y. Yoshino, Y. Kataya-ma, H. Tabata and T. Kawai, J. Appl. Phys. 80 (1), pp. 388-392, 1996.
[27] G. Piazza, P.J. Stephanou, J.M. Porter, M.B.J. Wijesundara and A.P. Pisano, Proc. 18th MEMS, pp. 20-23, 2005.
[28] R. S. Mane and C. D. Lokhande, Mat. Chem. Phys. 65 (1) pp.1-31, 2000.
[29] F. Lemmi, W. Chung, S. Lin, P. M. Smith, T. Sasagawa,
B. C. Drews, A. Hua, J. R. Stern, and J. Y. Chen, IEEE El. Dev. Lett. 25 (7) pp. 486–488, 2004.
[30] C.-U. Pinnow and T. Mikolajick, J. Electrochem. Soc. 151 (6) pp. K13-K19, 2004.
[31] S. Tehrani, J. M. Slaughter, E. Chen, M. Durlam, J. Shi, and M. De-Herrera, IEEE Trans. Magn. 35 (5) pp. 2814-2819, 1999. [32] S. Lai, Proc. IEEE IEDM, pp. 255-258, 2003.
[33] J. H. Wu, J. Scholvin, and J. A. del Alamo, IEEE Trans. El. Dev. 51(11) pp. 1765-1771, 2004.
[34] H. Lorenz, M. Despont, N. Fahrni, N. LaBianca, P. Renaud and P. Vettiger, J. Micromech. Microeng. 7 pp. 121–124, 1997. [35] R. Feng and R. J. Farris, J. Micromech. Microeng. 13 pp. 80–88,
2003.
[36] E. H. Conradie and D. F. Moore, J. Micromech. Microeng. 12 pp. 368-374, 2002.
[37] G. B. Levy, W. Evans, J. Ebner, P. Farrell, M. Hufford, B. H. Allison, D. Wheeler, H. Lin, O. Prache and E. Naviasky, IEEE J. Solid-State Circuits, 37 (12) pp. 1879-1889, 2002.
[38] H. Lee, M.H. Miller, and T.G. Bifano, SPIE 4979 pp. 137–144, 2003. [39] P. Chiniwalla, R. Manepalli, K. Farnsworth, M. Boatman, B. Dusch,
P. Kohl, and S. A. Bidstrup-Allen, IEEE Trans. Adv. Packag. 24 (1) pp. 41–53, 2001.
[40] C. Miremont, G. Bodammer, D. Calton, W. Parkes, W. Zheng and I. Underwood, Displays 23 pp. 115-119, 2002.
[41] P. F. van Kessel, L. J. Hornbeck, R. E. Meier and M. R. Douglass, Proc. of the IEEE 86 (8) pp. 1687-1704, 1998.
[42] G. Stix, Scientific American, 0036-8733, February 1, 2004, Vol. 290, Issue 2.
[43] M. I. Haller and B. T. Khuri-Yakub, IEEE Trans. Ultrason., Ferro-elect., Freq. Contr. 43 (1), pp. 1-6, 1996.
[44] A. Bagolini, L. Pakula, T. L. M. Scholtes, H. T.M. Pham, P. J. French and P. M. Sarro, J. Micromech. Microeng. 12 (4) pp. 385-389, 2002. [45] S. Roy, S. Furukawa, and M. Mehregany, Microsyst. Technol. 2 pp.
92-96, 1996.
[46] A. E. Franke, D. Bilic, D.T. Chang, P.T. Jones, T.-J. King, R.T. Howe, and G.C. Johnson, Proc. 12th MEMS, pp. 630-637, 1999.
[47] T. R. Hebner, C. C. Wu, D. Marcy, M. H. Lu, and J. C. Sturm, Appl. Phys. Lett. 72 (5) pp. 519-521, 1998.
[48] R. Khamankar, J. Kim, B. Jiang, C. Sudhama, P. Maniar, R. Moazza-mi, R. Jones and J. Lee, Proc. IEEE IEDM, pp. 337-341, 1994. [49] R. Moazzami, P.D. Maniar, R.E. Jones, and C.J. Mogab, Symp. VLSI
Technol., pp. 54-55, 1994.
[50] M. R. Douglass, Proc. IEEE IRPS, pp. 11-16, 1998. [51] LCoS special issue, Displays 23 (3), 2002.
[52] A. Choubey, F. Andros, and B. G. Sammakia, IEEE Trans. Compon. and Packag. Technol. 28 (2) pp. 303-310, 2005.
[53] T. J. Drabik, A. H. Titus, M. A. Handschy, D. Banas, S. D. Gaalema, and D. J. Ward, IEEE Micro 15(4) pp.67-76, 1995.
[54] W. E. Howard and O. F. Prache, IBM J. Res. Develop. 45 (1) pp. 115-127, 2001.
[55] H. Aziz and Z. D. Popovic, Chem. Mater. 16 (23) pp. 4522-4532, 2004.
[56] E. R. Fossum, IEEE Trans. El. Dev. 44 (10) pp. 1689-1698, 1997. [57] H. Abe, Proc. IEEE IEDM, pp. 989-992, 2004.
[58] Y. Inaba, M. Kasano, K. Tanaka, and T. Yamaguchi, IEEE El. Dev. Lett. 27 (6) pp. 457-459, 2006.
[59] A. El Gamal, Proc. IEEE IEDM, pp. 805-808, 2002.
[60] R. Turchetta, J. D. Berst, B. Casadei, G. Claus, C. Colledani, W. Du-linski, Y. Hu, D. Husson, J. P. Le Normand, J. L. Riester et al., Nucl. Instr. Meth. A 458 pp. 677-689, 2001.
[61] J. Jiang, S. Tsao, K. Mi, M. Razeghi, G. J. Brown, C. Jelen, and M. Z. Tidrow, Infrared Phys. And Technol. 46 pp. 199–207, 2005. [62] H. Zogg, K. Alchalabi, D. Zimin, K. Kellermann and W. Buttler,
Nucl. Instr. Meth. A512 pp. 440-444, 2003.
[63] R. B. Bailey, L. J. Kozlowski, J. Chen, D. Q. Bui, K. Vural, D. D. Edwall, R. V. Gil, A. B. Vanderwyck, E. R. Gertner and M. B. Gubala, IEEE Trans. El. Dev. 38 (5) pp.1104-1109, 1991. [64] P. L. Richards, J. Appl. Phys. 76 pp. 1-24, 1994.
[65] B. E. Cole, R. E. Higashi, and R. A. Wood, Proc. of the IEEE 86 (8) pp. 1679-1686, 1998.
[66] D. S. Tezcan, S. Eminoglu, and T. Akin, IEEE Trans. El. Dev. 50 (2) pp. 494-502, 2003.
[67] E. Mottin, J.-L. Martin, J.-L. Ouvrier-Buffet, M. Vilain, A. Bain, J.-J. Yon, J.-L. Tissot, and J.-P. Chatard, Proc. SPIE 4369, pp. 250– 256, 2001.
[68] S. Sedky, P. Fiorini, K. Baert, L. Hermans, and R. Mertens, IEEE Trans. El. Dev. 46 (4) pp. 675–682, 1999.
[69] A. Tanaka, S. Matsumoto, N. Tsukamoto, S. Itoh, K. Chiba, T. En-doh, A. Nakazato, K. Okuyama, Y. Kumazawa, M. Hijikawa et al., IEEE Trans. El. Dev. 43 (11) pp. 1844-1850, 1996.
[70] J.-S. Shie, Y.-M. Chen, M. Ou-Yang, and B. C. S. Chou, J. Microelectromech. Syst. 5 (4) pp. 298-306, 1996.
[71] R. A. Wood, Proc. SPIE 2020, pp. 322–329, 1993.
[72] Roelof de Vries et al., Submitted to Nucl. Instr. And Meth A (these proceedings).
[73] K. Bethke, R. de Vries, V. Kogan, J. Vasterink, R. Verbruggen, P. Kidd, P. Fewster and J. Bethke, Nucl. Instr. Meth. A563 pp. 209-214, 2005.
[74] L. Strüder, Nucl. Instr. Meth. A 454 pp. 73-113, 2000. [75] E. Heijne, Nucl. Instr. Meth. A 541 pp. 274–285, 2005.
[76] G. Anelli, S. C. Commichau, M. Despeisse, G. Dissertori, P. Jarron, C. Miazza, D. Moraes, A. Shah, G. M. Viertel and N. Wyrsch, Nucl. Instr. Meth. A 518 pp. 366-372, 2004.
[77] T. Lulé, S. Benthien, H. Keller, F. Mütze, P. Rieve, K. Seibel, M. Sommer, and M. Bohm, IEEE Trans. El. Dev. 47 (11) pp. 2110-2122, 2000.
[78] A. Oed, Nucl. Instr. Meth. A 263, pp. 351-359, 1988.
[79] A. Sarvestani, H. J. Besch, M. Junk, W. Meißner, N. Sauer, R. Stieh-ler, A. H. Walenta and R. H. Menk, Nucl. Instr. Meth. A 410 pp. 238-258, 1998.
[80] Y. Giomataris, Ph. Rebourgeard, J.P. Robert, and G. Charpak, Nucl. Instr. Meth. A 376 pp. 29-35, 1996.
[81] F. Sauli, Nucl. Instr. Meth. A 386 pp. 531-535, 1997.
[82] M. Campbell, E.H.M. Heijne, X. Llopart, P. Colas, A. Giganon, Y. Giomataris, M. Chefdeville, A.P. Colijn, A. Fornaini, H. van der Graaf et al., Nucl. Instr. Meth. A 560 pp. 131–134, 2006.
[83] R. Bellazzini, F. Angelini, L. Baldini, F. Bitti, A. Brez, M. Ceccanti, L. Latronico, M.M. Massai, M. Minuti, N. Omodei et al., Nucl. Instr. Meth. A 535 pp. 477-484, 2004.
[84] M. Chefdeville, P. Colas, Y. Giomataris, H. van der Graaf, E.H.M. Heijne, S. van der Putten, C. Salm, J. Schmitz, S. Smits, J. Timmermans and J.L. Visschers, Nucl. Instr. Meth. A 556 pp. 490– 494, 2006.
[85] M.J. Key, V. Cindro, and M. Lozano, Radiat. Phys. Chem. 71 pp. 1003–1007, 2004.
[86] A. Owens and A. Peacock, Nucl. Instr. Meth. A531 pp. 18-37, 2004. [87] P. Fischer, Nucl. Instr. Meth. A 409 pp. 152–156, 1998.
[88] H.Chr. Kästli, M. Barbero, W. Erdmann, Ch. Hörmann, R. Horisber-ger, D. Kotlinski and B. Meier, Nucl. Instr. Meth. A 565 pp. 188-194, 2006.
[89] R. Bellazzini, G. Spandre, M. Minuti, L. Baldini, A. Brez, F. Cavalca, L. Latronico, N. Omodei, M.M. Massai, C. Sgro’ et al., Nucl. Instr. Meth. A 566 pp. 552-562, 2006.
