On-Chip Scan-Based Test Strategy for a Dependable
Many-Core Processor Using a NoC as a Test Access
Mechanism
Xiao Zhang, Hans G. Kerkhoff
Testable Design and Test of Integrated Systems Group, Centre of Telecommunication and Information
Technology (CTIT), University of Twente, Enschede, the Netherlands
x.zhang@utwente.nl and h.g.kerkhoff@utwente.nl
Bart Vermeulen
Distributed Systems Architectures Group Research / Advanced Applications
NXP Semiconductors Eindhoven, the Netherlands
bart.vermeulen@nxp.com Abstract—Periodic on-chip scan-based tests have to be applied to
a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated into the SoC to function as an ATE. This paper introduces the reuse of a Network-on-Chip as a test access mechanism. Since the scan-based test is performed on-chip via the NoC at application run-time, it needs to share the NoC bandwidth with other applications. Instead of reserving sufficient NoC bandwidth for the test, the authors propose a novel way to carry out scan-based tests by dynamically pausing and resuming the test data flow to accommodate the fluctuating communication bandwidth available on the NoC. The test stimuli application and test response collection processes are decoupled to meet the global timing constraint. The many-core processor, IIP and the NoC have been implemented in synthesizable VHDL. Simulation results show the correct application of standard structural test patterns to the processing tiles and the test response collection at run-time using the proposed approach.
Keywords- Scan-based test, dependability, many-core processor, reconfiguration, test wrapper, network-on-chip (NoC), test access mechanism (TAM)
I. INTRODUCTION
Recent advances in the semiconductor industry enable the integration of very large scale electronic systems on a single chip (System-on-a-Chip, SoC). For example, by incorporating more than one processing core on a single die, the traditional micro-processor has been evolving into many-core processors with hierarchical IP cores and subsystems. As the complexity of modern SoCs grows, testing of these SoCs is becoming a huge challenge. Recent work proposed test planning [1] and test wrapper design [2] for the testing of hierarchical SoCs. IEEE Std. 1500 further enables a standard approach for core-based testing [3].
A direct consequence of the ever growing IC transistor density is the rapid volume increase of the test data. Test data compression methods, such as deterministic BIST (DBIST) [4], have been proposed by combining a linear-feedback shift
register (LFSR) to reduce the volume of test stimuli patterns and a multiple-input signature register (MISR) for test response compaction. External automatic test equipment (ATE) is used to store the LFSR seeds and to compare the test response signatures with those from a known fault-free design.
For a many-core processor with many identical processing cores (tiles), the test responses from several identical fault-free tiles are the same given the same test stimuli are applied to each of these tiles. Assuming that only one tile becomes faulty at a time, one can identify this faulty tile by comparing the test responses from all tiles-under-test to the responses from a Known-Good-Tile with no need for DBIST signature data storage [5].
The idea proposed in [5] has been adopted to design a highly dependable many-core processor for mission-critical applications. The system dependability attributes such as reliability, availability and maintainability have been greatly improved as a result of the proposed Design for Dependability (DfD) approach [6]. The DfD approach featured incorporating an Infrastructural IP (IIP) into the SoC [7][8] to perform a periodic test to the selected few ones of an array of Xentium tile processors (from Recore Systems [9]). Deterministic test patterns can be reproduced by the test pattern generator (TPG) in the IIP which only stores a small amount of seeds for the LFSR. Test responses from the selected tiles-under-test then return to the test-response evaluator (TRE) of the IIP. The faulty tile processor (if any) can be detected by majority-voting the responses and be eventually isolated from the system by the dependability software [6]. An advantage of this method is that the system can maintain its functionality while performing the periodic on-chip test when the running application does not need the full computing resources of the many-core processor.
A key issue which previous work has not addressed is an efficient and flexible test access mechanism bridging the IIP and the processing tiles. Network-on-chip (NoC) has been proven to be a promising approach for tile-to-tile interconnection in a SoC owing to its ease of reconfiguration and scalable bandwidth for selected applications [10]. The idea of reusing the NoC as a test access mechanism (TAM) instead of dedicated wires is also becoming attractive as a result of the This research is conducted within the FP7 Cutting edge Reconfigurable ICs
for Stream Processing (CRISP) project (ICT-215881) supported by the European Commission.
flexibility and capability of a NoC to route the test stimuli data to target cores and to receive the test responses [11][12].
This paper completes the previous DfD approach by describing the on-chip scan-based test strategy using the NoC as a TAM. The remainder of this paper is organized as follows. Section II formulates the research goals and gives a brief introduction to the many-core processor as a research example. Section III focuses on our novel methods to perform an on-chip scan-based test by decoupling the test pattern application and test response collection operations and adapting to the fluctuating communication bandwidth available on the NoC. The test wrapper design for the Xentium tile processor is explained in Section IV. The complete many-core processor and the embedded IIP have been designed and implemented in synthesizable VHDL, for inclusion in a chip which will be manufactured in 2010. Section V shows the simulation results of some test cases. Some conclusions are made in Section VI.
II. GOAL OF RESEARCH
Previous research works have proposed ideas on the efficient bandwidth utilization of the NoC as a TAM. Since their testing was done off-line with an external ATE, they focused on maximizing the utilization of available NoC bandwidth for transporting test data by reducing the “idle bits” [13] or by using a Time-Division-Multiplexed NoC [14].
Different from their approach, we have replaced the external ATE with an infrastructural IP embedded into the many-core processor because the dependability test needs to be applied to the processing tiles periodically in the field. The test is carried out by the IIP using e.g. three processing tiles such that the untested tiles can continue with their normal functionality. This can be regarded as a hybrid form of on-line and off-line test.
In this form of test, the NoC bandwidth is shared between the normal applications and the testing task. It is required that our test approach intrudes as little as possible on the NoC communication of other applications. To achieve this, the testing task should be kept simple and able to adapt to the varying amounts of spare NoC bandwidth available at run-time. Ideally, one can suspend the testing task to release the NoC bandwidth and give priority to other applications and resume the test afterwards when the bandwidth requirements of other applications are lower.
This paper presents several novel methods to achieve this goal. First, the test stimuli application and test response collection processes are decoupled in order to simplify the top-level control of the scan-based test. Second, a new method is presented to pause and resume the scan-based test depending on the on-going traffic on the NoC by using network flow control information.
Since all test data is transported via the NoC, an important assumption for our approach is that the NoC is fault-free. Otherwise it becomes difficult to identify whether a faulty response is introduced by a faulty tile, or by the faulty NoC. The correctness of the NoC is periodically tested by executing special NoC test software in the general purpose processing device (GPD) in the many-core processor. The NoC test
strategy is not the focus of this paper and is addressed in another paper.
The DM is a key element in the dependability test scenario and its correctness is also periodically verified. Debug pins have been reserved for DM verification after chip tape-out. DM verification software is also periodically executed in the GPD to check and ensure the correct behavior of the DM.
It is assumed that only one fault will take place at a time. The stuck-at fault model was chosen as a starting point for our fault detection research, as they can be tested by the classical scan-based test. More fault types can be considered in future to enhance the effectiveness of the DM.
III. TESTING MULTIPLE TILE PROCESSORS USING THE NOC Three important elements can be identified in a conventional structural test scenario: (1) a circuit under test (CUT), (2) automatic test equipment (ATE) and (3) a Test Access Mechanism (TAM). In the context of this paper, each Xentium tile processor is a potential CUT at run-time, the IIP (Dependability Manager) functions as an ATE and the NoC is reused as a TAM.
A special wrapper has been designed and is instantiated around each Xentium tile processor. This Xentium Tile Wrapper (XTW) can switch between functional mode and dependability test mode as requested by the DM. While in functional mode, the XTW delivers the data from the NoC to the functional inputs of the tile. In dependability test mode, it delivers the NoC data to the test inputs (scan-chain input and primary input) of the tile. The same operation applies to the tile output data. Design details of the XTW are explained in Section IV.
A. The Network-on-Chip
The NoC transports the huge amount of data among the processing tiles. Our NoC features a packet-switched router architecture, which has 32-bit wide data channels operating at 200MHz. Each router has five data ports to five directions (North, East, South, West and Local) and each data port supports four time-multiplexed virtual channels [15]. Each virtual channel provides an even share (25%) of the total bandwidth of a data port. An application can gain more NoC bandwidth by using more virtual channels. The virtual channel allocation is governed by the run-time mapping software [6] running on the GPD. Mission-critical applications with higher priority get a larger bandwidth.
The IP cores on the SoC communicate to the NoC via a network interface (NI). The NI packs the data from a core with the routing information to the destination, and delivers it to the NoC. The NI also unpacks the data package it receives from the NoC and delivers its payload to the core. Dedicated NIs have been designed for both the DM and the Xentium tile processors in order to allow them to communicate via the NoC. B. Testing a Single Xentium Tile Processor via the NoC
The Xentium tile processor is a hierarchical core with a standard logic cell part and embedded memories. All embedded memories have a BIST function. While the XTW is in
dependability test mode, the DM starts the memory BIST and collects the memory BIST results after completion via the NoC (see Figure 1).
Scan-based tests are used for the logic part (data path and control) of the Xentium tile processor. Given the fixed number of scan registers in one tile, it takes less clock cycles to fill multiple parallel scan-chains than one long serial scan-chain. So it is preferable to insert multiple parallel scan-chains into the Xentium logic part. On the other hand, the data channel of the NoC is 32-bit wide, which means that one 32-bit data word can be transported via the NoC in every clock cycle. A natural approach is to insert 32 scan-chains of equal length into the logic part of the Xentium so that each bit of the 32-bit data word delivered via the NoC can be shifted into one scan-chain in one clock cycle for maximum efficiency.
A block diagram of the testing scenario for one Xentium processor is shown in Figure 1 (the DM-NI, Xentium tile primary inputs and outputs are not drawn due to limited space).
The original deterministic test patterns for the Xentium logic part (with 32 parallel scan-chains) have been generated by using a commercially-available ATPG tool. These deterministic test patterns are then compressed and can be reproduced by the LFSR combined with the reseeding technique. Due to the area constraint for the DM, 1002 out of 1275 deterministic patterns are reproduced. The generated patterns are evaluated in the ATPG tool with the Xentium logic part and they can achieve a fault coverage of 90%. This fault coverage is sufficient for the current dependability test though a higher fault coverage is still possible to reach at the cost of more silicon area for the DM. A phase-shifter (PS) is used to construct the 32-bit word test patterns which are then transported via the NoC and shifted into the parallel scan-chains in the Xentium logic part. The footprint of the DM logic and the storage of “seeds” is about 1% of the total silicon area of the many-core processor.
NoC NI XTW
Xentium Logic Part scan chain 0 scan chan 1 scan chain 31 . . . Embedded Memory (BIST) NoC NI XTW 0 1 31 . . . P S L F S R S e e d 1 S e e d 2 S e e d N BIST Control T R E 0 1 31 . . . Test Stimuli Test Response FSM DM BIST Start BIST Result
Figure 1. Testing one Xentium tile processor via the NoC
Test patterns for primary inputs (PI) of the logic part are also generated and applied to the Xentium PI (explained in Section IV) after the scan-chains are completely filled. Then the XTW will generate the necessary control signals (e.g. the scan enable signal) to drive the scan test. Finally the test
responses are transported back to the TRE of the DM via the NoC, where they are compared.
C. The Modified Scan-Based Test
It appears straight forward to perform a scan-based test for the cores-under-test via the NoC. However, problems do arise when the packet-switched NoC is reused as a TAM instead of a dedicated set of test wires.
In a conventional structural test, the scan-in and scan-out operations are performed in a parallel way to minimize the test time. It means the “shift-in” operation of the current test pattern occurs at the same time as the “shift-out” operation of the previous test response. This test approach is possible because both operations take exactly the same number of clock cycles to complete (see Figure 2 (a)).
If the packet-switched NoC is used as a TAM, the test data (both the scan patterns and primary input patterns) are packed as 32-bit “data flits” to travel through the NoC. As the Xentium tile PI and PO numbers are both larger than 32 bits, the application of the primary input patterns can not be accomplished in one clock cycle anymore. It will take several more clock cycles for the full PI data flits to arrive from the NoC and fill the corresponding primary input signals of the Xentium tile. The same applies to the unloading of the primary output responses. This is illustrated in Figure 2 (b). If new scan patterns arrive and are shifted into the scan-chain before all the primary output responses are unloaded, some scan test responses will be overwritten.
(a)
(b)
Figure 2. Scan-based test scheme. (a) conventional case (b) decoupled case. “S” denotes the scan-in vectors; “O” denotes the scan-out responses. “PI” represents the primary input vectors and “PO” represents the primary output
responses. The grey area means “don’t care” state.
Therefore, system level constraints are needed to guarantee that the number of clock cycles to load the PI and to unload the PO matches the test pattern generation and test response collection operations. Unfortunately, things become even more complicated when one considers the on-going functional traffic on the NoC because of other applications, which can add more dynamics to the predictability of the test data travel time on the
NoC. For this reason, it is proposed to decouple the test pattern application and test response collection operations.
As shown in Figure 2 (b), the test pattern generation and test response collection process now take place in a serial fashion. The test pattern generator in the DM will not generate a new test pattern until the responses from the previous pattern have been fully received. A drawback of this method is the doubling of the test time. On the other hand, the simultaneous NoC bandwidth requirement by the DM and the system-level communication complexity are reduced by half. To summarize, while the total test pattern and response throughput stay the same, the decoupling makes it far easier to match the test pattern generation and test response evaluation operations. D. Pause/Resume of Scan-Based Test
Based on the discussion in Sections III B and C, it becomes clear that one can test a single Xentium tile processor by using the DM as an ATE and the NoC as a TAM. It should be noted, though, that the “correct” test responses of the scan-based test are not stored in the DM. Instead, the scan test responses from multiple Xentium tiles are compared with one another in the TRE of the DM to identify the possible faulty tile (by means of majority-voting).
As mentioned in our dependability approach, a test is periodically scheduled for the idle tiles (if any) in the many-core processor. The run-time mapping software [6] can make tiles idle by shifting their workload to other tiles. Normally three tiles are tested as a group while the application continues to run on the other processing tiles. Some important features are required from the NoC besides its basic specifications:
• Support for both point-to-point and multicast communication
• In-order delivery
• Dynamic bandwidth allocation (by virtual channel) according to the application priority
• Router buffers enabling “back-pressure” data flow control
Since the same test patterns need to be applied to every Xentium tile under test, a multicast function of the NoC is very useful. The DM then only needs to generate the test patterns once, and broadcast these patterns to multiple destinations (i.e. the tiles to be tested). For the test response collection, a point-to-point communication is important to ensure all test responses arrive at the input ports of the TRE of the DM.
It is essential that the NoC delivers all data in a single virtual channel “in-order”. Such a NoC exhibits a in first-out (FIFO) behavior between the source and destination of the communication and guarantees the correct order of test pattern application and test response collection.
Compared to the running applications in the many-core processor, the dependability test of Xentium tiles is a relatively low-priority task. It is possible that a higher priority system task will claim a NoC resource which is used by the DM for test pattern delivery. As shown in Figure 3 (a), originally, two virtual channels (VC1 and VC2) are allocated for test data. In
Figure 3 (b), all the virtual channels (four in total) of the east port of Router 1 are occupied by a higher priority task.
Test Data DM Router 2 Router 1 …... Buffer Register VC1 VC2 (a) (b)
Figure 3. “Back-pressure” driven test data flow (a) data channel is free; sufficient bandwidth (b) data channel (east) in router 1 is occupied by a more
important task (south); DM test is paused.
In this case, the DM needs to be notified and has to stop generating the test patterns to avoid NoC congestion and loss of the test patterns. Buffer registers have been implemented in the NoC router in each direction to hold data which can not be delivered to the outlet port in time. This undelivered data will start to accumulate in the router buffer registers until they are fully filled. Then a “buffer full” signal is generated to the previous router down the routing path. When the buffer in the last router is full, a “Pause” signal is issued to the DM by the last router and the test pattern generation is paused by disabling the LFSR in the TPG. The LSFR state is recorded and the scan-based test is pending until the routing path is freed again. This “back-pressure” driven way to control the test data flow on the NoC is fully illustrated in Figure 3. A simulation of this scenario is shown in Section V.
Figure 4. Test responses matching from 3 Xentium tiles
Similarly, test response data flow control is also necessary for test response evaluation. An example scenario is depicted in Figure 4. Due to SoC layout limitations, only two routers (R1 and R2) are available for the DM to access the NoC. These two routers provide the total input and output NoC bandwidth which the DM can utilize. As shown in the figure, Xentium tile
3 (X3) can send back test responses to the DM-TRE at a double rate as compared to Xentium 1 and 2, because X3 has the full bandwidth of the east data port of Router 1 (R1), while Xentium 1 and 2 share the east data port of Router 2 (R2). However, the comparator (CMP) in the DM-TRE will execute a single response comparison only if the test responses of the “same position” (in the total test response) from the three Xentium arrive in its local buffer. As a result, the test response transportation from X3 is actually paused periodically to match the pace of the test response delivery of the other two Xentium processors. A simulation of this scenario is also shown in Section V.
IV. XTW DESIGN A. Overview
The Xentium Tile Wrapper (XTW) wraps a single Xentium tile to allow access to its test infrastructure. Figure 5 shows a high-level block diagram of the XTW, showing its main components and the Xentium tile it wraps.
Test Stimuli (from NI)
Xentium Logic Part scan chain 0 scan chain 1 scan chain 31 ... Embedded Memory (BIST) Test Response (to NI) BIST Start
(from NI) BIST Results(to NI)
SIM SIU .. . .. . . . . . . . SOU Primary
Inputs OutputsPrimary Wrapper Controller CG .. . Clock Test Stimuli (from NI)
Xentium Logic Part scan chain 0 scan chain 1 scan chain 31 ... Embedded Memory (BIST) Test Response (to NI) BIST Start
(from NI) BIST Results(to NI)
SIM SIU .. . .. . . . . . . . SOU Primary
Inputs OutputsPrimary Wrapper Controller CG .. . Clock Figure 5. Block Diagram of the Xentium Tile Wrapper
The XTW has three operating modes; (1) a functional mode, (2) a manufacturing test mode, and (3) a dependability test mode. In functional mode, the wrapper is transparent for the Xentium tile’s functional signals, allowing each Xentium tile to interface normally with the rest of the SoC. This mode is selected by default upon power-up of the SoC.
Manufacturing test mode is selected by asserting a dedicated test mode port on the wrapper. All logic in the XTW and the Xentium tile subsequently become fully scan testable. This mode is used after manufacturing of the SoC to test the entire SoC as a single, flat design for manufacturing defects.
The XTW can be switched to dependability test mode under control from the DM, by accessing one of two control registers. These control registers are accessible via a dedicated network interface. This interface is connected to the on-chip network, allowing any initiator on the network, including the DM, to configure each XTW. At run-time, these control registers permit the activation of the scan test and memory
BIST operations of the Xentium Tile and associated memories from the DM.
B. Building Blocks
The Xentium Tile Wrapper consists of five components. The Scan Input Multiplexer (SIM) is responsible for multiplexing the manufacturing test and dependability test scan inputs to the inputs of the scan chains in the Xentium tile. The Surround Input Unit (SIU) takes care of providing the input signals to the primary inputs of the Xentium tile. The Surround Output Unit (SOU) captures test responses from the functional output of the Xentium. The Clock Gate (CG) is responsible for gating the clock to the scan chains in the Xentium tile, whenever test patterns do not arrive at the XTW network interface on time, or when the test responses are not read fast enough from the XTW network interface. As such, the CG decouples the test operations in the Xentium tile and its wrapper from the communication on the on-chip network, significantly reducing the timing constraints at the SoC top-level. Care is taken during post-synthesis layout and clock tree insertion to ensure that the additional delay introduced by the CG does not cause problems in the communication between the Xentium tile and other top-level blocks, e.g. the NoC. The Wrapper Controller orchestrates the test operations of the Xentium tile and associated memories, interfacing the scan chains and BIST engines with the on-chip network, with support from the SIM, SIU, and SOU components.
C. Wrapper Control and Status Registers
An initiator on the NoC can access control and status registers via the wrapper’s network interface to control and observe the dependability scan test and BIST operations. When dependability scan test mode is enabled, an initiator has accesses to four additional data registers inside the wrapper; writing a single, 32-bit test pattern word to Data Register 1 causes the bits in this word to be shifted into the 32 scan chains in the Xentium tile in parallel, one bit per written word. Writing a single, 32-bit primary input stimulus word to the Data Register 2 causes the bits in this word to be written into the SIU, for application on the primary inputs of the Xentium tile during dependability normal mode. When all primary input stimuli and test pattern bits have been written to the wrapper, the wrapper controller autonomously transitions the Xentium tile to dependability normal mode, and captures the Xentium tile primary outputs in the SOU. Subsequent read operations on Data Registers 3 and 4 retrieve respectively the captured primary output values, and the test response bits in the scan chains for comparison between the different Xentium tiles under test by the DM.
BIST operations on the memories associated with the Xentium tile can also be performed, although due to I/O isolation limitations, not in parallel with the dependability scan operation. During the BIST operation, the Wrapper controller configures all eight BIST engines and monitors the execution of the BIST algorithm. Upon completion, the wrapper controller captures the test results from the BIST engines, and makes those available in a wrapper status register. The DM is then able to retrieve these results by reading this register through the network interface.
V. SIMULATION AND VERIFICATION RESULTS A many-core processor with nine Xentium tiles and the IIP has been implemented in synthesizable VHDL. Figure 6 shows the complete dependability manager synthesized with TSMC 90nm technology. The DM gate count is around 40000 with a minimum speed constraint of 400MHz. A testbench is designed using SystemC and the complete dependability approach has been simulated and verified. The simulation results of some important test cases mentioned in Section III are shown in this section.
Figure 6. DM synthesized with TSMC 90nm technology
A. Test pattern generation and response collection
Figure 7 shows the simulation results of the complete process of generating one test pattern, applying it to the Xentium tiles and collecting their test responses. The test pattern is generated by the TPG and packed into many 32-bit data flits in the DM. These data flits are then multicast over the NoC to the three target Xentium processing tiles. When the complete test pattern is received and unpacked by the Xentium network interface, the scan-registers and the primary input of the Xentium tile are loaded with the correct test stimuli. The XTW switches the Xentium tile to normal mode for one clock cycle and the test responses are produced. The test responses from all three Xentiums are then collected and compared by the DM.
In principle, the test patterns entering one Xentium tile and the produced test responses are of similar data volume. However, the bandwidth available for test responses collection is half of that for test pattern generation due to limited number of routers connected to the DM. Therefore, the time it takes to transport the test responses to the DM is twice as long as to generate the test pattern, as shown in Figure 7. This timing mismatch is acceptable in our approach as the scan-based test is modified in such a way that the test stimuli application and test response collection processes have been decoupled. Either process can even be suspended if necessary without causing a disorder of the entire scan-based test.
Figure 7. Simulation results: generate one test pattern and collect the responses
B. Test response matching
Due to NoC latency and bandwidth restrictions, the test responses from the 3 Xentiums do not arrive at the DM at the same pace (as explained in Section III D, Figure 4). As shown in Figure 8, the test response flit “0F0F0F0F” from Xentium 3 arrives first at the DM and the one from Xentium 1 arrives last. The DM monitors the incoming response data so that the response comparison (in white circle) does not start until all the three responses in one group have arrived.
As illustrated in Figure 4, Xentium 3 has more NoC bandwidth to the DM than Xentium 1 and 2. Because the test responses of Xentium 3 are not “consumed” sufficiently fast by the DM, its test responses accumulate in the FIFO buffers of the routers along its virtual channel to the DM. When all the buffers are full, Xentium 3 is periodically paused and resumed by the “back-pressure” from the NoC so that it can match the “pace” of Xentium 1 and 2.
VI. CONCLUSION
In this paper, a novel strategy for performing on-chip scan-based test is presented by using the functional communication (NoC) as a TAM at application run-time. In principle, this strategy is applicable to any SoC with multiple identical cores given a similar NoC as introduced in this paper. Dedicated test wrappers for the cores-under-test are needed to support the “back-pressure” driven NoC data flow. Simulation results of a simplified many-core processor with DM and the NoC have proven the feasibility of this new strategy. Silicon of this system is expected soon in 2010.
ACKNOWLEDGMENT
The authors would like to thank Mark Westmijze for the DM network interface design, Pascal Wolkotte for the NoC design, Jeroen Flierman and Jordy Potman (both from Recore Systems) for the SystemC testbench design.
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