A course on field programmable logic

A course on field programmable logic

Citation for published version (APA):

van der Eijnden, P. M. C. M. (1985). A course on field programmable logic. (EUT report. E, Fac. of Electrical Engineering; Vol. 85-E-148). Eindhoven University of Technology.

Document status and date: Published: 01/01/1985

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A Course on

Field Programmable Logic

By

P.M.C.M. van den Eijnden

EUT Report 85-E-148 ISBN 90-6144-148-X ISSN 0167-9708 April 1985

EINDHOVEN UNIVERSITY OF TECHNOLOGY Department of Electrical Engineering

Eindhoven The Netherlands

A COI}RSE ON

FIELD

PROGRAMr~ABLE

LOGIC

by

P.M.C.M. van den Eijnden

EUT Report 85-E-148

ISBN 90-6144-148-X

ISSN 0167-9708

Coden: TEUEDE

Eindhoven

Apri 1 1985

First printing January 1983. Second printing April 1985. Third printing July 1985.

CIP-GEGEVENS KONINKLIJKE BIBLIOTHEEK, DEN HAAG

Eijnden, P.M.C.M. van den

A course on field programmable logic / by P.M.C.t'l. van den

Eijnden. Eindhoven: University of Technology. Fig.

-(Eindhoven University of Technology research reports /

Department of Electrical Engineering, ISSN 0167-9708;

85-E-148)

r4et lit. opg., reg.

ISBN 90-6144-148-X

SISO 664.2 UDC 681.325.65.02 UGI 650

Acknowledgements

In these course notes logic diagrams of available programmable

devices are used in order to clarify the structures of these

devices. For the diagrams of IFL devices the "Signetics Integrated

Fuse Logic" handbook (Ref.

1)

of Phil ips has been used. The diagrams

of the PAL's are from the "PAL Handbook" (Ref. 2) of Monol ithic

Memories Inc. (MMI).

Signetics Corporation,

811 East Arques Avenue,

P.O.

Box 409,

Sunnyvale, CA 94086

Monolithic Memories,

2175 Mission College Blvd.,

Santa Clara, CA 95050

ABSTRACT

This report gives a survey of programmable logic components that can be used to real ize both combin,atlonal and sequential logic circuits. A general structure for these components is determined starting with boolean equations and state diagrams respectively. The considerations with respect to optimization and decomposition of a'circuit, that play an important role when designs are made with these components are discussed. To complete the survey several commercially available products are passed in review.

Eijnden, P.M.C.M. van den

A COURSE ON FIELD PROGRAMMABLE LOGIC.

Department of Electrical Engineering, Eindhoven University of

Technology (Netherlands), 1985.

EUT Report 85-E-148

Address of the author:

ir. P.M.C.M. van den Eijnden,

Digital Systems Group,

Department of Electrical Engineering,

Eindhoven University of Technology,

P.O. Box 513,

5600 MB EINDHOVEN,

The Netherlands

CONTENTS

1. INTRODUCTION 1

2. COMBINATIONAL LOGIC 3

3. REALIZATION OF SWITCHING FUNCTIONS 5

3.1 Singular standard gates 5

3.2 Hypothetical programmable array for logic functions 5 3.3 Programmable arrays versus standard parts 21

3.4 Programming the array 23

4. AVAILABLE PROGRAMMABLE ARRAYS 4. 1 (P) ROM

4.2 (F) PLA 4.3 (F)PGA 4.4 PAL (HAL)

5. DESIGN PROBLEMS USING PROGRAMMABLE ARRAYS 5.1 Product term expansion

5.2 Output expansion 5.3 Input expansion 6. SEQUENTIAL LOGIC 34 34 36 46 51 65 65 73 75 81

6.1 General model for sequential circuits 81

6.2 Memory elements 82

6.3 Synchronous and asynchronous sequential circuits 84 6.4 Representation of synchronous sequential systems 86

7. REALIZATION OF A SYNCHRONOUS CIRCUIT 91

7.1 Singular gates 91

7.2 Progammable arrays 92

7.3 Hypothetical programmable array with state register 97

8. AVAILABLE PROGRAMMABLE SEQUENCERS 8.1 (F)PLS 8.2 PAL (HAL) REFERENCES 99 99 III 119

1. INTRODUCTION

Until now digital circuits for small production volumes could economically be realized only using so called standard parts: small scale and medium scale integration (SSI/MSI).

At the moment however new components are available which

may be regarded as a replacement of the parts mentioned above. They all have got a matrix structure and are known as:

Programmable Arrays.

Because digital circuitry can be divided into two major

categories:

Combinational Sequential

the total number of arrays may also be grouped according to this classification. Therefore these course notes have also been divided in two major parts. The first part (chapter 1 - 5) deals with combinational logic. the second part (chapter 6 - 9) with sequential logic.

However before going into detail about the components (arrays) we will first have to study the reasons for using them and the logical reasoning that is behind their structure. Hence part one starts with a short overview of combinational logic. From this a general array structure is determined. Knowing this general structure available components will be studied. The

second part has been arranged in the same way. In this part we

start with a short overview of sequential logic from which a general sequencer structure is determined. Then the available sequencers are studied.

2. COMBINATIONAL LOGIC

From switching theory i t is known that any sWitching function of n variables f(xi ,x2' •••• ,xn) may be expressed as a sum of products, where in each product every input variable appears in either its true or complemented form.

Example: xlx2 x3x 4 f (xl ,x2,x3,x4) _{xlx2 x 3 x 4}

+

+

-

-xlx2 x 3x 4

+

xlx2 x 3 x 4

+

xlx2 x 3x 4

+

xlx2 x 3 x 4

This form is called: standard normal form, full disj unctive

normal form or sum of minterms, and is generally expressed as:

mt = minterm; 81 = 0, 1 It is also known, that because of the duality principle, any switching function of n variables f(xi ,x2' •••• ,xn) may be

expressed as a product of sums, where in each sum every input

variable appears in either its true or complemented form. Example:

The function of the previous example may also be written as:

f(xI,X2,X3,X4) (xl

+

x2

+

x3

+

x4) • (xl

+

x2

+

x3

+

x4) • (xl

+

x2

+

x3

+

x4)· (xl

+

x2

+

x3

+

x4)· (xl

+

x2

+

x3

+

x4) • (xl

+

x2

+

x3

+

x4) • (xl

+

x2

+

x3

+

x4) • (xl

+

x2

+

x3

+

x4)· (xl

+

x2

+

x3

+

x4)· (xl

+

x2

+

x3

+

x4)

This form is known as:

conjunctive normal form

generally written as:

stan,dard product of sums, full

or product of maxterms, aQd is

Mi = Maxterm; Gi Z 0, !

Neither of these standard forms is minimal. That is to say the number of product terms or sum terms as well as the nU!q}).e.r Q-f

variables contained in these product terms or sum terms may be reduced. The mathematical rules according to which thi~

reduction may be accomplished are given by Boolean alg~b~~.

Applying these rules to the example given above leads tQ:

3. REALIZATION OF SWITCHING FUNCTIONS 3.1 Singular standard gates

It may implemented function of

be stated that any switching function can be using standard (TTL) AND, OR and NOT gates. The

our example may be realized as:

f

(a)

f

(b)

Figure 3.1 Realization of example function (a) sum of products

(b) product of sums

3.2 Hypothetical programmable array for logic functions 3.2.1 General Considerations

Considering the statement of paragraph 3.1, we may say i t really would be practical to have one standard part only which comprises a number of the three types of gates in such a way that

any switching function can be realized with this device by some

wiring. Such a standard part might be realized in three stages. Stage 1 consists of a set of inverters (NOT) to generate the complemented form of input variables. The next stsge uses the output sigma1s of the first stage. This stage consists of a number of AND gates. These NOT-AND combinations generate the product terms. The third stage consists of an OR gate using the

from one stage may be used as input signals for the next stagE!' The signals are applied to the next stage by means of switches. When a switch is closed a term is appl ied to the next stagE!. when i t is open no signal is applied. The structure is shown in figure

3.2. The switches allow for selective (programmable)

connections. With this device the example function may be realized as shown in figure 3.3

11

. l { : ) ' ) o t r t r t r

-12

4>~+-+-t---+-H'-r---+++-r---In

L.{>::»+t-+t--f-1

I

r-++H--t-T---++++--+t--I

'tY--

,\1'

l'\I"~

-_

1\'

y

--Figure 3.2 General structure of a device which can realize any logical function

In

l{)

1-

"-/ '

L

_v

_"

L

i'-/ '

l{)

,\

,,,

II"

,\

,I,

,\,1

,\

- -

--Xl~X3

X3

X

4

-

I

-Figure 3.3 The example function realized with the general device

If more than one function has to be realized simultanously, the previous structure can easily be expanded to more outputs. Figure 3.4 shows the general device structure for a multiple output configuration.

In

l{>-4>

It

_I

,

.\,\(-

,\ I' ,

_''/'(.

,\ "

,\

'\I\I~--

,\ 1\

I

-

--

-

-

----.

--

_,

,

I

,

,

-fm

Figure 3.4 General device structure for a multiple

So far a programmable (switch selectable) device has been

studied in which three stages can be recognized, viz:

1. Input stage

2. Programmable AND gates (switches

+

AND gates) 3. Programmable OR gates (switches

+

OR gates)

3.2.2. Realization of the programmable array

The problem we are now dealing with is: I1How can this switch

structure be realized in One part only'l?

3.2.2.1 The programmable AND gates

Let us first consider the AND part of the total scheme. An AND function of two variables can easily be built by means of a simple diode network as shown in figure 3.5.

+

P!roduct term)

Figure 3.5 Two input AND function with diodes

Expansion for more variables can be done by adding more diodes, see figure 3.6

The (programmable) switches may be implemented by means of fuses which can be blown. Figure 3.7 shows this idea.

+

12

In

P(roduct term)

P=lr 12.13 ·I_n

Figure 3.6 n-input AND function with diodes

+

12

In

fuse P

For example product follows: 12 term P

13-kJ-= is now realized +

Figure 3.8 Implementation of a product term

Repetition of the structure of figure 3.7 leads to a programmable AND array, see figure 3.9.

+

+

+

+

In---4~--+-~----r-~---+---~--~

For convenience of drawing the conventions for arrays shown in figure 3.10 could be used. With these conventions a very simple drawing for the programmable AND array results (see figure 3.11).

replace

with

and

Figure 3.10 Drawing conventions for diode crossings

+ + +

+

[

[

- - - -

[

I I I I I I I

In

Figure 3.11 The programmable AND array drawn according to new conventions

3.2.2.2 Input stage (inverters)

The input stage should consist of inverting and non inverting lines. Inverters may simply be added to the inputs. This leads to the general structure of figure 3.12. All possible input combinations per input variable on a product line are summarized in figure 3.13.

+ + +

+

~JJ

0

-.4)

I{;

I

,

,

,

,

,

I I

In

It>

Figure 3.12 Programmable AND array with inverters

Figure 3.13 Input combinations per input

Any combination of product terms can be realized with this AND array. For example the two product terms of the example function:

are implemented like shown in figure 3.14.

Note that all fuses of unused P-terms (product terms) are

l e f t intact. This means that the output of these P-terms is

always

"Q",

because both xi and it appear 1n these P-terms

(compare figure 3.13).

+ + +

+

1

1

-x,

4>

lr>

4>

lr>

I I I I I I I I

4>

P,

P2 P3

Pp

P,=X,X2 X3;

P2=X3~;

P3=··· .=Pp=O

Figure 3.14 Realization of two product terms with the programmable AND array

3.2.2.3 The programmable OR gates

The same procedure used for AND gates is applicable to the OR gates. An OR function of two variables can be realized by means of a simple diode network as shown in figure 3.15.

~4

O(r term)

Figure 3.15 Two input OR function with diodes

Expanding this structure in two dimensions leads to more

input variables and more output functions respectively. Again

fuses are connected in series with the diodes to make a

programmable OR array (see figure 3.16). Using drawing conventions indicated in figure 3.17 greatly simplifies the drawing of the OR array as may be seen from figure 3.18.

o

o

o

o

A2--~--~~--~~---+---~---r

Ap--~---+--~--+-~--~---4----~

°1

replace

.,," ---+

and

.,," ---+

Figure 3.17 Drawing conventions for diode crossings

o

0 0

o

[

J

- - - - ~-- - ~ -I I I I I I I

Figure 3.18 The programmable OR array drawn

3.2.2.4 The complete array

The AND- and OR-array may be put together now by assigning:

Both arrays cannot be directly connected. Buffering is required. because of the load of the OR-array on the AND-array. Buffering of the outputs of the OR-array is also required because of the load of other parts of a total circuit on this array. This buffering leads to the following structure (with all fuses intact):

In

o

o

o

1

+ + +

1

-4)

Y?

_I I I I I I I

l-£)

P.

\

/ \

/ \ /

I

A-

_I ---I

Figure 3.20 The complete array

+

1

~

~buffers

7·

0,

°2

I I I I I I I I

Om

The example function

might be implemented as shown 1n figure 3.21.

4>

4>

4>

4>

₁ I I I I I I I

4>

In

1--1

o

o

1--1 I I I I I I I I

o

-l

+ + +

0[0

-+

V \ / ' /

Figure 3.21 Example function realized 1n the complete array

O,=f

°2

3.3 Programmable arrays versus standard parts

Now that a programmable array has been developed, let us look at the sdvantages such an array has over the well known standard parts/singular gates (eg. 7400 series).

Standard parts have a few advantages. One of these advantages is that they are very cheap because of large production volumes. A second advantage is that a circuit may be realized very fast. Not only because one can buy standard parts almost anywhere, but particularly because a large variety of components is available (AND, OR, NOT, NAND, NOR, EX-OR etc). However, this last point may also be seen as a disadvantage. The more components there are the more random a choice of components is done .. Often you see a deSigner turn Over the leaves of his databook chOOSing randomly gates that best fit to a certain part of his circuit (random logic). This design method leads to non-structured deSigns or realizations. Testability and reliability of non-structured designed circuits are often

poor. Circuits require many interconnecting Wires, due to the

fact that only a few singular gates are available within one package. Each wire is a possible error source. If a non-structured circuit with many interconnecting wires is malfunctioning testing may be a hard job.

This extensive wiring has another consequence. Circuits are generally realized using printed circuit boards (PCB's). Design of these PCB's is expensive, because many inter-connections require a complex PCB layout in more layers. A great deal of expensive PCB-area is lost to the wiring.

Summarizing the advantages and disadvantages of standard

parts leads to the following table:

advantage:

ad van tage/

cheap

almost anywhere for sale

fast circuit realization

disadvantage: large variety of components disadvantage: non-structured design

many packages per circuit poor testability

poor reliability

expensive and comlex PCB's

Table 3.1 Advantages and disadvantages of standard parts

All the advantages mentioned for standard parts apply to programmable arrays as well. However, for programmable arrays the disadvantages may be strongly reduced. Designs may be well structured using programmable arrays because gates are not randomly chosen. PCB's are less complex and expensive. This is due to the fact that wiring is brought onto the chip. A reduction of the chip count of 1:6 - 1:20 is possible. Pin assignment for input variables and output functions may be done to make the best fit to the PCB layout. The reliability of a circuit increases because the number of interconnecting wires becomes much less.

A small disadvantage of programmable arrays is the fact that special programming equipment is needed to blow the fuses of the array. This programming is discussed in the next paragrsph.

3.4 Programming the array

3.4.1 Programmer

As was pOinted out in the previous paragraphs programming of an array means "blowing fuses according to a given fuse pattern". To program our logic array we need special equipment: "a programmer" which accepts as its input the designed fuse pattern (for the logical function) and generates programming pulses to blow the fuses in the logic array. Figure 3.22 illustrates the programmer concept.

DESIRED

FUSE

PATTERN

LOGIC

PROGRAMMER

DEVICE

TO BE

PROGRAMMED

programmlng

intor ... ,ation

programming

signals

Figure 3.22 The Logic Programmer concept

This leaves us two problems, viz:

1. How can the programmer be loaded with the desired fuse pattern?

2. In what format should the fuse pattern be presented to the programmer?

3.4.2 Editor and format

The first problem hss been solved by building the

pro-grammer using a microprocessor and memory_ The microprocessor

program accepts input from a keyboard, terminal or host computer. This program is generally called an: "editor".

One way to enter the programming data is manually by typing

a datatable in the form of one's and zero's. A· one might for example mean: "blow fuse" and a zero: "don't blow fuse". A

program table would thus look like the one shown in figure 3.23. In this table two example functions have already been entered, viz:

fl

=

xl x 2 x 3 + xl x 4 £2

=

xl x 3

+

x2 x 4

AND-ARRAY OR-ARRAY 1

f

.

.

.

I

f

I

f

I

f

I

I

F

...

F F F n n 3 3 2 Z I I 0 0 m 2 I 0 Po I I I I 0 I 0 I 0 I 0 0 1 0 PI 1 1 0 1 I I I I 0 1 0 0 I 0 Pz 1 I I I 0 1 I I I 0 0 0 0 I P3 1 1 I 0 I I 0 I [ _{I 0 0 0 I} P4 0 0 0 0 0 0 0 0

a a

0 0 0 0, Pp 0 0 0 0 0 0 0 0 0 0 0 0

a

0

u u

x it x it x it x it U U f f 4 4 3 3 2 2 I [ _{2 I}

Figure 3.23 Program table (U denotes unused)

Each entry in this table corresponds to a specific fuse in the complete array. A row in the AND-array table represents a product term (P). A "0" in a row in the OR-array table selects the product term to be used in a specific function. So FO contains Po and PI. and F[ contains P2 and P3 in the given example. Note that the fuses of unused inputs and product terms are left intact (0). so design changes may be done if necesssry. Filling out a table with one's and zero's is a boring task

and is prone to errors. This table of course must be present in the programmer to be able to blow the fuses. However we would

like to have another coding scheme to tell the programmer what to do. A built in translation program can then translate this "higher level coding scheme" into a table containing one's and zero"s only.

3.4.3 Higher level coding scheme

Let us now look for a more sophisticated coding scheme. For one input varisble four different combinations. indicating fuses blown or unblown. might occur. These are summarized in figure 3.24 together with their one/zero codes from our first program table.

'~-

:: 00

P=I·I =0

'~

= 01

P=I

'~-

=10

Figure 3.24 Interpreting the following shorthand patterns:

P=I

:: 1 1

P=don'! care

The possible input combinations per input variable on a product line together with their one/zero coding

codes by means of this figure leads to the

notation to code the different fuse

00 = both fuses unblown. So the input variable is inactive.

Let us denote this with an "0".

01

=

the input variable is present in the product term in

its true form. In other words the variable is active high. Let us denote this with an "H".

10

=

low active state of input variable. So let us assign

the code "L" to this state.

11 = don't care for the input variable. Both fuses are

blown, so the variable is not present in the product

term. This will be indicated with a "-"

P=don't care

Figure 3.25 The possible combinations per input variable on a product line together with the short hand coding

For the output functions two possible situations may occur.

A fuse is to be blown or not. Figure 3.26 illustrates the coding we have used in our first programming table.

Figure 3.26 The possible combinations per product term on an output line together with their one/zero coding

An unblown fuse indicates that the product term is present in the output function. In other words the product term is active for that funtion. We will code this with an "A" (Active). A blown fuse indicates that that product term is not present in that specific function (inactive). This will be indicated by means of a "." (dot). Figure 3.27 summarizes this coding for the OR-array.

•

Figure 3.27 The possible combinations per product term on an output line together with the short hand coding

With this short hand coding we have created the program

table shown in figure 3.28. Again the same two example functions

are already entered in this table.

I

. . .

I I I I F

...

F F F n 3 2 1 0 m 2 1 0 Po

-

-

H H H A A

.

A PI

-

H

- -

H A A

.

A P2

-

-

H - L A A A

.

P3

-

L - H

-

A A A

.

P4 0 0 0 0 0 A A A A Pp 0 0 0 0 0 A A A A U x x x x U U f f 4 3 2 I 2 1

.-Figure 3.28 Program table with new conventions (U denotes unused)

3.4.4 Boolean assembler

We now might go one step further and not even enter a table at all. Why not installing a translator program that accepts Boolean expressions as its input and translates them to a table consisting of one's and zero's. Let us call this translator

program "Boolean translator". The three programs are linked as

indicated in figure 3.29.

MANUAL INPUT FROM

KEYBOARD, TERMINAL OR HOST COMPUTER

IN FORM OF BOOLEAN EXPRESSIONS

EDITOR

FILE

WITH

BOOLEAN

EXPRESSIONS

BOOLEAN ASSEMBLER

/

PROGRAM

1

TABLE

<

"1", "0")

PROGRAMMER

/

PROGRAMMED

/

DEVICE

Figure 3.29 Different programs required in the logic programmer

We are now left with a new problem:

The Boolean assembler only knows physical pin names, eg 10' I l' FO' Fl etc.

Would i t be posible to use symbolic (user defined) names, eg. Xl' x2' f etc.

Adding more intelligence to the assembler enables us to use symbolic names. Now the input for the assembler consists of different parts, viz:

1. COMMENT part

This is a number of lines in which the user may describe for example what the functions of the circuit are.

2. INPUT PIN ASSIGNMENT part

In this part user defined input names are assigned to physical pin names.

3. OUTPU.T PIN ASSIGNMENT part

In this part user defined function names are assigned to output pins.

4. BOOLEAN EXPRESSION part

In this part of the input the Boolean expressions are given as statements.

The structure of such a description for the two example

BEGIN

COMMENT

This is an example to indicate a possible circuit

description which might be used as input for a Boolean assembler

INPUT PIN ASSIGNMENT

10 := xl 11 :

-

x2 12 := _x3 13 : = _x4 14 : = unused In := unused

OUTPUT PIN ASSIGNMENT

FO :- fl Fl := f2 F2 :- unused Fm := unused BOOLEAN EXPRESSIONS END

Now we have got a nice solution of the array programming problem. However there are s t i l l two problems left to solve: 1. Checking for typing errors or even worse design

errors

2. Testing of the programmed device to verify

whether i t functions correct or not

3.4.5 Simulation and test

Checking for typing errors may partly be taken care of by the editor. For example suppose no other operators as +, := and. are allowed. A simple syntax check might look for undefined operators. However an erroneously interchanging of xl and x2 for example, can not be discovered by the syntax checker. The result is that a complete different circuit has been defined. 3.4.5.1 Simulation

A simulation program is required to detect this kind of errors. This program uses two kinds of input, viz:

1. Boolean expressions after they have been translated

2. Testpatterns (input/output patterns)

The first of these two is the output generated by the Boolean assembler. The second input part must be provided for by the user. In a testpattern a user defines an input combination together with the desired output pattern.

Suppose for example that the following two functions are entered into the system:

fl

=

xl x 2 x 3 + xlx4 f2 m xlx3 + x2x4

Possible testpatterns for these two functions might look like: x x x x f f

4 3 2 1 2 1

0 0 0 0 0 0 testpattern I

1 0 0 1 0 1 test pattern 2

0 1 0 0 I 0 testpattern 3

The simulator uses the given Boolean expressions and input patterns and calculates the resulting values for the output functions. The resulting output patterns are compared to those given by the user in the testpatterns. If they match simulation continues else errors are listed. From the output of the simulator a user may determine whether his circuit is correctly functioning or not.

For example during the problem definition phase a user has got a truth table. From this table he determined a set of minimal Boolean expressions. He thinks these expressions are correct. Suppose no typing errors are made. The next step is to present the truth table from the problem definition stage to the simulator. As a result the simulator detects output patterns that are not matching the original truth table and lists the errors. The user may now go back to the original truth table and try to find the correct Boolean expressions.

The simulator may thus be run on the program table before the actual programming is done. Possible typing errors or design errors may be discovered prior to programming the device.

3.4.5.2 Testing

After the device has been programmed one would like to test the programmed device to verify whether i t is a good device or not. So another program is required with which we can test a programmed device. This test program uses two kinds of input, viz:

1. The programmed device 2. Test pst terns

The testpatterns may be the same as those used by the simulator. The test program applies the given input patterns to the programmed device. The output patterns that the test program reads from the programmed array are compared with those given in the testpatterns. If both are equal the device is correctly functioning, else errors will be listed.

Linking it all together we get the following overall picture:

MANUAL INPUT FROM

KEYBOARD, TERMINAL OR HOST COMPUTER

IN FORM OF BOOLEAN EXPRESSIONS

. EDITOR

FILE

WITH

BOOLEAN

EXPRESS IONS

BOOLEAN ASSEMBLER

PROGRAM

TABLE

(111"1"0" )

CORRECT

PROGRAM

TABLE

GOOD

DEVICE

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Figure 3.30 Overview of software needed in the Logic Programmer

4. AVAILABLE PROGRAMMABLE ARRAYS

In the previoua chapter we have developed the general structure for a programmable array to implement combinational logic. In practice four major types of programmable arrays are

available, resulting from different design strategies or

applications. These are:

(P) ROM (F)PLA (F)PGA PAL / HAL

(Programmable) Read Only Memory (Field) Programmable Logic Array (Field) Programmable Gate Array

Programmable Array Logic / Hard Array Logic

These components will now be discussed to see where they are

based on and what applications they are best suited for.

4.1 (P)ROM

A (P)ROM is a memory device in which the selection of the words is implemented, using all minterms of a given number of input variables. The minterms are realized in the AND-field. The AND-array is therefore fixed. The minterms are connected to a programmable OR-array. In case of a ROM this OR-array is programmed by the manufacturer according to a pattern defined by the user. Programming is done in that case during production (mask programming). A PROM may be programmed by the user (in the

field) by blowing fuses. The structure of a PROM is given in

figure

4.1-So one or more functions may be realized in their standard normal form by means of a PROM. As we know the standard normal form is not optimal. So because of redundancy a lot of chip area is lost when realizing switching functions with PROM's. Only switching functions where no real reduction by combination of minterms is possible (EX-OR like functions) are optimally realized using PROM's. Applications of PROM's are thus limited to:

Memory

EX-OR like functions

(P)ROM's are offered by many manufacturers, ego Intel, Motoro1s, Texas Instruments, Signetics, Monolithic Memories

Inc., National Semiconductors etc.

PROM programming is usually done using a microcomputer development system expanded with s PROM programming module. A program developed with the system is loaded into Random Access Memory (RAM) and then copied into PROM.

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4.2 (F)PLA

The design strategy for (Field) Programmable Logic Arrays is exactly the same we have seen in chapter 2. The AND- and

OR-array are both programmable. PLA's are programmed during

production by the manufacturer according to a pattern defined by the user (mask programming). FPLA 's may be programmed by the user (in the field).

There are several manufacturers of FPLA ' s . The leading ones

are: Signetics, Texas Instruments, Fairchild and National

Semiconductor. Their FPLA's only differ in the number of input and output pins or product terms.

For example Signetics/Philips offers two FPLA's: 82S100 / 82S101

82S152 / 82S153 4.2.1 82S100 / 82S101 4.2.1.1 Logic diagram

The 82S 100/82S 101 is a 28-pins device. There are only a few minor differences between the hypothetical array of chapter two and these devices as may be seen from figure 4.2 (next page) which shows the logic diagram of the 82S100/82S101. Note that in

this logic diagram though all fuses are originally intact no dots are indicated. This enables the user to use this logic diagram as a programming scheme.

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The first difference we note is the output configuration. The FPLA is provided with a programmable output stage. Output functions may be programmed independently active high or active low. This is done using an Exclusive-OR as indicated in figure 4. 3.

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Figure 4.3 (a) active high programming of output

(b) active low programming of output

As an extra feature the outputs may be tri-state (828100) or open collector (828101). The tri-state outputs are well suited to be used in bus organized systems. Open collector outputs may be connected in parallel (wired-OR). In this way the number of product terms msy be expanded (see paragraph 5.1.1). 8een from another point of view, a common signal line may be driven by several open collector outputs without further requirements

(e.g. think of bus-request line in multiple processor

applications).

Another difference from the hypothetical array may be seen in the implementation of the FPLA (figure 4.4). In this figure we see that the non-inverted input lines are also buffered. This buffering reduces the load on previous circuits. The delay times for inverted and non-inverted inputs are now equal. Another difference is the absence of separate buffers between the AND- and OR-array. Buffering is now accomplished by means of the transistors of the OR-array.

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The example functions:

f1

=

x1 x 2 x 3 + x1 x 4 f2 x1x3 + x2 x 4

may be implemented (using the 82S100/82S101) as shown in figure 4.5

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4.2.1.2 Program table

Programming specification for the FPLA 825100/825101 is in accordance with the high level coding we have seen in paragraph 3.4.3. 5ymbolic notations are used to indicate a certain fuse configuration. The coding conventions used for this FPLA are summarized in figure 4.6

In future (4th quarter 1983) it will be possible to specify the programming pattern for the FPLA in Boolean expressions which will be translated by a Boolean assembler.

Figure 4.7 shows the program table used for the FPLA 825100/825101. In this table the two example functions:

f1

=

x1 x 2 x 3 + x1 x 4 f2 =

x1

x 3 + xZ x 4

have been programmed.

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STATE CODe STATE

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STATE

INPUT VARIABLE

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PROGRAM TABLE ENTRIES

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Figure 4.7 Program table for the FPLA 82S100/82S101 with example functions entered.

4.2.2 82S152 / 82S153

The 825152/82S153 is another FPLA offered by Signetics. It is a 20 pins device. The 825152 has open collector outputs whereas the 82S 153 has tri-state outputs. Figure 4.8 shows the logic diagram. The programming options are equal to those of the FPLA 82S100/82S101 (figure 4.6).

As may be seen in the logic diagram bidirectional I/O lines are now available giving more flexibility to the designer. The bidirectional I/O lines may be controlled independently by special product lines of the AND. array (Control Terms). This provides for the possibility to use these lines as input or

output depending on Some input combination. Of course

bidirectional I/O lines may be programmed to be fixed input or output lines. The designer then has a maximum of 17 input lines

and 1 output line, or 8 input lines and 10 output lines.

Multilevel networks and asynchronous sequential circuits (see chapter 6) may be realized without loosing input pins, because if a line is programmed as an output line, i t is s t i l l available in the AND array part of the circuit.

Figure 4.9 shows the program table for this device. Note that the influence of the control terms on the behaviour of the circuit may easily be determined from this table (product terms DO_ 9) •

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4.3 (F)PGA

Sometimes we are dealing with switching functions

consisting of one product term only. A good example of this is a chip select signal in computer circuitry. In this case the use of an FPLA would not be economically. For this reason a special array has been designed which does not have the OR-field, and can perform single level AND logic functions. This array is called: (Field) Programmable Gate Array «F)PGA). The PGA again is the mask programmable device.

in:

FPGA's serve as universal logic elements and may be applied

machine state decoders fault monitors

code detectors

peripheral selectors

Signetics/Philips offers this array in its 28 pin series as part no. 82S102(0.C.)/82S103(T.S.) and in its 20 pin series as 82S150(0.C.)/82S151(T.S.). Figures 4010 and 4.11 show the

logic diagrams of the 82S102/82S103 and 82S150/82S151

respectively. As an example the logic programming options and program table of the 82S150/82S151 are shown in figures 4.12 and 4.13 respectively. Note that the programming options for the outputs (active high/active low) are opposite to those of the FPLA's, due to the presence of NAND gates rather than AND gates. As may be seen from their respective logic diagrams the 828150/82S151 is much more flexible than the 825102/825103. The 828150/828151 has bidirectional I/O lines and the output lines may be controlled in groups of four, whereas the 82S102/825103

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PROGRAM TABLE ENTRIES: -j NOTES

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828150/828151

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4.4 PAL (HAL)

The maj or problems in designing with (P)ROM's were the non optimal realization of functions (min terms) and the presence of glitches in the output. This is due to the fact that the AND-array is fixed and different propagation delays exist from

inputs to the outputs, because address decoders often are used

instead of a real AND-array. Both problems can be eliminated by making the AND-array programmable too, like in FPLA's. However making both arrays (AND and OR) programmable resulted in a large chip area. Furthermore the programmable OR-array is not optimally used if the output functions realized, have no

product terms in common.

From these considerations Monolithic Memories Inc. (MMI) decided to develop a device with a programmable AND-array and a fixed OR-array. MMI called their products Programmable Array Logic (PAL). They also started the production of mask programmable devices fully compatible with their PAL's and called these Hard Array Logic (HAL) (Compare with PROM and ROM). Nowadays PAL's are offered by other manufacturers like Advanced Micro Devices (AMD) , National Semiconductor and Texas Instruments (TI). The strategy behind the PAL's is the same. Here we will study the PAL's offered by MMI.

4.4.1 Logic diagram of PAL's

Because of the fixed OR-array a lot of flexibility is lost. To meet this shortcoming a whole family of different PAL's has been designed. Two different PAL's with Active High and Active Low outputs are available, as well as PAL's with complementary outputs (true and inverted output). PAL's are available in two pin configurations, viz: 20 pins and 24 pins. These three PAL types all have totem-pole outputs, shown in figure 4.14.

40" NOM

---0 OUTPUT

Figure 4.14 Totem-pole outputs present with active high and active low PAL's and PAL's with complementary output Figures 4.15 gives an overview of all active high PAL's that are available to implement combinational logic (only in 20 pin series) •

Logic: I)/aOr8fII PAL t OHI

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-- f - ,

c-:::--4--I

' II

I

II

; I

I

I

't '

._,,-

_,-I,

_';'·1

_{-th ' Jj}

_{II: -}

--::.:1--,

..

_"

", ... ,-- '''' """,. """j """"

_.

=

- _il

I

,

=

- =====.:1 -1"'-_ ---

-11

==.:1---I --J;$.

I I

I'

I,

I~

ill

,:-t\ll '

I

IT]

j

==1----'I·

1[,

I ,',

fill

i

il

,

Ii I: 111 ,',

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,,: iii:

'Iii ,:1 :111 ' _"

"

, 1,1 '" _"

Figure 4.15 Logic diagrams of all active high PAL's to implement combinational functions

The logic diagrams shown in figure 4.15 may be used as coding schemes. Now the "x" symbol is used to indicate a fuse that is left intact. The symbology used with PAL's is summarized in figure 4.16. A short hand notation is given in this figure for product lines that have all fuses intact.

Conventional Symbology

PAL Symbology

1

FUSE BLOWN

t

j! /

''---'fA)

FUSE NOT BLOWN

--:i"

-+1W:i""~'"---l

--1-1-

1112+1112

" *-Tt

-r

:-~lD

" .. "

::--.-[ -Fj---;g---r) --)--"

i2.;'" vee LOGIC STATE H L L H INPUT

L--{::E==t4

HIGH INPUT

L--t:~=::j:+W

lOW'::"

~

PRODUCT WITH ALL FUSES BLOWN REMAINS HIGH

ALWAYS

H

" - - PRODUCT WITH ALL FUSES INTACT REMAINS lOW ALWAyS SHORTHAND NOTATION_\

FOR ALL FUSES INTACT \

III~

Figure 4.16 PAL symbology

The two example functions: