Power Amplifiers in CMOS Technology: A contribution to power amplifier theory and techniques

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POWER AMPLIFIERS IN CMOS TECHNOLOGY:

A CONTRIBUTION TO POWER AMPLIFIER

THEORY AND TECHNIQUES

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Samenstelling Promotiecommissie:

Voorzitter: prof.dr.ir. T.J. Mouthaan Universiteit Twente

Secretaris: prof.dr.ir. T.J. Mouthaan Universiteit Twente

Promotor: prof.dr.ir. B. Nauta Universiteit Twente

Assistent-promotor: dr.ir. A. J. Annema Universiteit Twente

Leden: prof.dr.ir. F.E. van Vliet Universiteit Twente

prof.dr. J. Schmitz Universiteit Twente prof.dr. J.R. Long TU Delft

prof.dr.ir. D.M.W. Leenaerts TU Eindhoven

Title: POWER AMPLIFIERS IN CMOS TECHNOLOGY: A CONTRIBUTION TO POWER AMPLIFIER

THEORY AND TECHNIQUES Author: Mustafa Acar

ISBN: 978-90-365-3138-2 ISSN: 1381-3617

DOI-number 10.3990/1.9789036531382

The work described in this thesis was supported by the Dutch Technology

Foundation STW (Reliable RF, TCS.6015) and carried out in the IC Design Group, CTIT Institute, University of Twente, The Netherlands.

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POWER AMPLIFIERS IN CMOS TECHNOLOGY:

A CONTRIBUTION TO POWER AMPLIFIER

THEORY AND TECHNIQUES

PROEFSCHRIFT

ter verkrijging van

de graad van doctor aan de Universiteit Twente,

op gezag van de rector magnificus,

prof.dr. H. Brinksma,

volgens besluit van het College voor Promoties

in het openbaar te verdedigen

op woensdag 2 februari 2011 om 14.45 uur

door

Mustafa Acar

geboren op 02 februari 1979

te Gaziantep/Turkije

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Dit proefschrift is goedgekeurd door

de promotor prof.dr.ir. B. Nauta

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Only when

the last tree has died,

the last river has been poisoned

and the last fish has been caught,

will we realize that we cannot eat money

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List of Figures

1.1 Three main approaches to the design of RF CMOS power

am-plifiers in this thesis . . . 2

1.2 A generic schematic of RF PA . . . 3

2.1 Gate oxide breakdown in a MOS transistor [2] . . . 6

2.2 Hot carrier degradation in a MOS transistor [2] . . . 7

2.3 (a) Punchthrough in a MOS transistor. (b) The effect on the I-V curve [2] . . . 8

2.4 Degraded MOSFET model as it is used in the simulator for describing both oxide breakdown and hot-carrier degradation . 10 3.1 (a) Single-ended Class-E PA (b) Idealized model of single-ended Class-E PA . . . 14

3.2 Drawing to show the relations between the elements of the de-sign set K . . . 16

3.3 Normalized switch voltage and switch current of RF choke Class-E PA for d = 0.8, 1 and 1.2 . . . 17

3.4 (a) p(q, d) and (b) ϕ(q, d) as a function of q for d = 0.8, 1, 1.2 . 21 3.5 Elements of the design set KP(q), KC(q), KL(q) and KX(q) as a function of q for d = 0.8, 1, 1.2 . . . 23

3.6 Normalized Output Power as a function of q for d = 0.8, 1 and 1.2 23 3.7 Normalized (a) switch voltage, (b) switch current (c) load cur-rent (d) capacitor, C curcur-rent (e) inductor, L curcur-rent for diffecur-rent values of q for d = 1. . . 25

3.8 RMS value of the normalized switch current IS/I0as a function of q for d = 0.8, 1 and 1.2 . . . 26

3.9 Normalized (a) switch voltage and switch current for q = 2.422, (b) switch voltage and switch current for q = 3. For both (a) and (b) d = 1 is assumed. . . 27

3.10 Design-1, Class-E Design Optimization Flow Chart . . . 32

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4.1 (a) Single-ended Class-E PA (b) Model of Class-E PA with fi-nite dc-feed inductance and switch-on resistance (c) Normalized switch (transistor) voltage and current for the model of Class-E PA . . . 38 4.2 (a) Design set K = KL, KP, KC, KXand drain efficiency (η) as

a function of q for m = 0, 0.1, 0.2 . . . 42 5.1 Operation classes of single ended switching PA . . . 48 5.2 (a) Single-ended Class-EV S PA (b) Model of Class-EV S PA (c)

Switch voltage normalized to VDD and switch current

normal-ized to supply dc current, I0, of Class-EV SPA with finite dc-feed

inductance with the turn-on slope of k = −1.5, k = 0(Class-E) and k = 1.5 . . . 50 5.3 Elements of the design set KP(q), KC(q), KL(q), KX(q) as a

function of q for different values of k . . . 54 5.4 Loss-factors (a) (F

2 IF

2 V

KP ) for limited size transistor Class-EV Sand

(b) (F

2 I

KC) for freely chosen size transistor Class-EV S PA . . . . 56

5.5 (a) Class-EV V PA including driver and matching network (b)

Model of Class-EV V PA (c) Normalized switch voltage and switch

current of Class-EV V PA with turn-on voltage of α = 2, α = 0

(Class-E) and α = 1 . . . 60 5.6 P AE and Pantennausing technology and design parameters in [80] 65

5.7 Simulated (cadence, pss) normalized drain voltage waveform vs. analytical model of Class-EV V for (a) α = 0, (b) α = 1, (c)

α = 2 for QL= 5, 10, 20. The chosen duty-cycle= 50%, R = 1Ω,

q = 0.01, VDD= 1V and m = 0.01 . . . 66

5.8 Simulated (cadence, pss) (a) Efficiency and (b) Normalized Out-put Power (KP) vs. analytical model for QL = 5, 10, 20. The

chosen duty-cycle= 50%, R = 1Ω, q = 0.01, VDD = 1V and

m = 0.01 . . . 66 5.9 Measurement Results for α = 0, 1 and 2 . . . 67 5.10 Schematic of the PA circuit design, used for evaluating the

sim-ulator . . . 70 5.11 Simulated drain voltage and drain current signals for the upper

NMOSFET in the circuit of Fig. 5.10, in three different opera-tion modes. The α = 0 mode coincides with Class-E operaopera-tion 71 5.12 Output power plotted against stress time for the three

differ-ent operation modes of the Class-EV V PA used in this paper.

The dashed horizontal line shows the 22.5mW criterion used for defining circuit failure in this chapter . . . 71 5.13 PAE plotted against stress time for the three different operation

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5.14 Failure probability plots of the Class-EV V PAs used in this

chap-ter. Clearly the α = 1 mode and α = 2 mode have superior performance in circuit lifetime over the α = 0 mode . . . 73 6.1 Cross section drawing of (a) Standard Thick Oxide NMOS

tran-sistor (b) Extended-Drain Thick Oxide NMOS (ED-NMOS) transistor.The oxide thickness (tox) = 50 ˙A . . . 76

6.2 (a) Sub-optimum E PA (b) Model of sub-optimum Class-E PA . . . 76 6.3 According to the sub-optimum Class-E model, (a) drain

effi-ciency (η) (b) PAE and output power ratio of standard thick oxide NMOS and ED-NMOS. Break-down voltage (BVGD) of

ED-NMOS is assumed to be 2 times higher than NMOS and m for ED-NMOS is 0.0147 and for NMOS 0.0074 at 2GHz. The m values from the compact model was calculated data that agrees with the measurement results by ≈80−90% . . . 78 6.4 A generic layout drawing showing the scalable layout

optimiza-tion approach of the ED-NMOS RF power devices. Each unit transistor has 5µm finger length (E). Some connections are not drawn for the sake of simplicity of the layout picture . . . 79 6.5 (a) Classical symmetric multi-fingered layout (b) asymmetric

multi-fingered device layout . . . 80 6.6 General description of the measurement set-up using an active

harmonic load-pull system and the measured drain waveform of the NMOS power device to show the sub-optimum Class-E operation. VDD= 2.9V . . . 80

6.7 Measured power added efficiency (PAE) and Transducer Gain (=POUT/PAV) of ED-NMOSI, ED-NMOSII, ED-NMOSIIIand

Standard Thick-Oxide with respect to output power at 2GHz operation frequency. ED-NMOS’ have 6V supply voltage while Standard Thick-Oxide has 3V . . . 81 6.8 Measured maximum PAE and the corresponding output power

of ED-NMOSI at 2, 3 and 4 GHz with 5.5V supply voltage . . 82

6.9 Measured PAE and output power under sub-optimum Class-E operation of Standard Thick-Oxide NMOS with 3V supply voltage for 6 hours operation and ED-NMOSI for 5.5V for 4

hours and 6V for 2 hours. The thick-oxide NMOS shows a reliability problem by gradually losing its PAE, whereas ED-NMOSI shows no sign of reliability problem. The increase in

VDD after 4 hours increases the output power of ED-NMOSI . 83

6.10 Die photos of the ED-NMOSI, ED-NMOSII, ED-NMOSIII, and

Standard Thick-Oxide NMOS power devices. The shaded re-gions in the chip photo have designs that are not related with this work . . . 83

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7.1 (a) Conventional cascode PA, (b) Segmented PA to increase lifetime . . . 88 7.2 Simulated probability mass function for 107 breakdown events,

uniformly distributed over 16 segments: the median and mean of the fullest segment is much higher than those over all segments 89 7.3 Simulated POUT and PAE as a function of the number of

break-downs (operation time) for 3 situations: continuously using 16/16 segments resulting in EOL=110 events, constant-area re-dundancy using 8/16 + 8/16 segments yielding EOL=190 events (+70% lifetime), switching off the worst segment using 16-15-14-13 segments for which EOL=400 events (+260% lifetime) . . 90 7.4 Circuit schematic of each of the 16 PA segments including

break-down detection monitoring circuitry, digital control logic and decoders not shown. . . 91 7.5 Measured breakdown-indicating sense-voltage as a function of

stress time, under accelerated conditions. For each of the 4 op-eration modes the corresponding effective circuit configuration of the segment is shown . . . 92 7.6 Measured performance of 1 out of the 16 PA segments, at 900

MHz without harmonic tuning . . . 92 7.7 Micrograph of the demonstration vehicle in 90nm: the total PA

is subdivided into 16 segments with their own OBD monitor cir-cuitry. Digital control used for addressing each segments state. Total chip area is 3.0mm2 _{. . . .} ₉₃

8.1 (a) Supply Voltage-Resistive Load (b) Idealized Class-E PA . . 111 8.2 Probability mass functions over all sections, and of the fullest

two sections; For both figures the same defect density but dif-ferent number of sections . . . 121 8.3 The ratio between the number of breakdowns in the fullest

sec-tion and the average number of breakdowns, as a funcsec-tion of the number of section for 2 total number of events . . . 122 8.4 The ratio between the number of breakdowns in the fullest

sec-tion and the average number of breakdowns, as a funcsec-tion of the number of breakdowns for 16 sections . . . 123

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List of Tables

3.1 Known explicit design equations for Class-E . . . 16

3.2 Design set for (0.6 < q < 1) . . . 29

3.3 Design set for (1 < q < 1.65) . . . 29

3.4 Design set for (1.65 < q < 1.9) . . . 29

3.5 Design set for maximum output power . . . 30

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Chapter 1

Introduction

Since the introduction of the first analog cellular phone in 1971 the communi-cation industry in general and wireless industry in specific has followed a fast growth. More and more electronic equipment communicating wireless with other devices at ever higher communication speeds are presented to modern consumers. Some examples of this include, GSM, Bluetooth, WLAN, UMTS, ambient networks, femtocells, car-radio, and future 100Mb/s cellular systems. With the advent of new evolutions in wireless communications such as 3G, 4G1 _{the demand from the market on low-cost, miniaturized, low-power, and}

highly integrated wireless communication devices has increased. In order to meet these demands integration of RF building blocks into mainstream CMOS technology has been an ongoing trend [1].

One of the most challenging RF blocks to implement in mainstream CMOS technology is the power amplifier(PA). So far, many RF building blocks of mobile communication devices have been implemented successfully in CMOS technology except for the PA. This is mainly because mainstream CMOS tech-nology is optimized for low voltage while power amplifiers operate at high voltages2. Low breakdown voltages of CMOS transistors pose many reliability challenges for PAs.

In this thesis, three new approaches are introduced in order to enable the design of reliable RF PAs in CMOS technology, see Fig. 1.1. These three new approaches will be explained by using a generic schematic of an RF PA in Fig. 1.2, which shows the basic trade-offs in the design of PAs.

An important trade-off is seen between the the peak drain voltage (N ·VDD)

1_{4G (also known as Beyond 3G), an abbreviation for Fourth-Generation, is a term used}

to describe the next complete evolution in wireless communications. A 4G system will be able to provide a comprehensive IP solution where voice, data and streamed multimedia can be given to users on an ”Anytime, Anywhere” basis, and at higher data rates than previous generations.

2_{As an example, the supply voltage for GSM phones ≥ 3V [2], requiring at least 6V}

transistor breakdown voltage whereas the maximum reliable voltage for 65nm CMOS thin-oxide transistors is 1.2V.

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Reliable RF CMOS PA (chapter 6) Exploration of High-Voltage RF transistor Techniques Extended-Drain Variable-Slope Class-E (chapter 3 - chapter 5) Exploration of Switch-Mode

Power Amplifier Classes

Variable-Voltage Class-E

Exploration of Degradation Detection and Elimination Techniques

Segmented Power Device (chapter 7)

Fig. 1.1: Three main approaches to the design of RF CMOS power amplifiers in this thesis

and the tuning or class of operation of the PA. The peak drain voltage on the transistor of the PA depends on the tuning or the class of operation3_{. The}

voltage factor N varies between ≈ 2 (Class-F) and ≈ 4 (Class-E) for switching PAs, showing how significantly the tuning can influence the reliability limits of PAs. In this thesis, the tuning methods of switching PAs has been explored and new classes of switching PAs are found, allowing the optimum operation of RF PAs under given reliability, output power and efficiency conditions has been found ( [3]- [7]).

Another important trade-off is between the supply voltage VDD and the

load resistance R. The output power, POUT, is proportional to VDD2 /R in RF

PAs. In sub-micron CMOS technology if standard thin oxide transistors are used the allowed reliable supply voltage will be lower than 0.5V4. If the PA is directly connected to an antenna of 50Ω the output power will be only 5mW, which is too low for many of the wireless applications5_{. In order to be able}

to reach to POUT ≥ 1W the required load resistance R would have to be only

0.25Ω, which would decrease the power efficiency of the PA to unpractically low values [8]6_{. For high power (≥ 1W) RF amplifiers it is essential to increase}

the supply voltage to be able to preserve efficiency and have wide-bandwidth. In this thesis, also high voltage transistors in standard sub-micron CMOS technology were explored and it is found that drain-extension [9] allows a trade-off between matching network efficiency and power added efficiency, (P AE =

3_{The main focus of this thesis is switching PAs.}

4_{the reliable gate-drain voltage for 65nm CMOS standard thin-oxide transistors is 1V.}

Therefore, the allowed supply voltage will be lower than 0.5V.

5_{The required output power of wireless systems for example for GSM is more than 3W}

and for HyperLAN is 1W.

6_{A load resistance of 0.25Ω would mean a transformation ratio of n= 200 (from 50Ω}

antenna resistance) and the matching network efficiency would be less than 60%, for an assumed passive quality factor of 20 [13].

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η − PIN/PDC) where η = POUT/PDC is drain efficiency.

The third concept introduced in this thesis is degradation detection and elimination. For PAs, the typical definition of reliable operation time as ”the time until the occurrence of the first failure (breakdown) of the gate dielectric in a transistor” [10] is overly strict7. Due to large size of power transistors the effect of a single breakdown, that can be modeled as a resistance in the order of a few kΩ between gate-drain, gate-source or the gate-channel [10], on the performance is small. Recently, it has been shown [11] that e.g. a cascode Class-E PA can still function properly after a number of oxide-breakdowns. Transistor degradation can be monitored by e.g. oxide degradation, threshold voltage-shifts and mobility reduction. Lifetime of PAs can be increased signifi-cantly by segmenting the power transistors into many lower-power segments in parallel, all with their own breakdown detection circuitry, and switching off the sections with the most breakdowns [12]. This segmentation technique allows system level reliability monitoring by degradation detection and elimination.

Tuning/Matching Networks P_in P_out VDD/R 2 ~ R=R /n_L R_L V_DD P_DC NVDD

Fig. 1.2: A generic schematic of RF PA

The next chapter will address the main reliability issues and modeling of RF CMOS power amplifiers. Afterwards, an analytical model linking known and new sub-classes of Class-E PAs is presented in chapter 3. The analytical solution in chapter 3 is extended by including switch-on resistance in chapter 4. Likewise, the theory in chapter 4 is extended to cover sub-optimum operation in chapter 5. Chapter 5 is followed by example implementations benefiting from the low peak drain voltage of the new classes of operation in chapter 6. An RF PA implementation in standard 65nm CMOS technology with 3W output power and 70% PAE at 2GHz is presented. Afterwards, the degradation detection and elimination concept in RF CMOS PAs is introduced in chapter 7. In chapter 7, digital detection of oxide breakdown and life-time extension in CMOS technology are explained. Chapter 8 ends the thesis with conclusions.

7_{Generally in order to obtain high output power, CMOS RF PAs are designed at the}

edge of their reliability limits, which can cause reliability issues (e.g. oxide breakdown) in the presence of antenna mismatch, mistuning etc.

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Chapter 2

Reliability Issues and

Modeling of RF CMOS

Power Amplifiers

Several degradation mechanisms can significantly affect the performance of CMOS power amplifiers. Estimating the influence of the degradation mech-anisms on the life-time of the RF power amplifiers and dealing with them through careful design is essential in the implementation of RF power ampli-fiers in CMOS technology.

This chapter describes the most well-known degradation mechanisms: gate-oxide breakdown, hot carrier degradation, punch through, drain-bulk break-down and negative bias temperature instability (NBTI) that can significantly influence the performance of CMOS power amplifiers. Moreover, a degraded NMOS transistor model and simulator taking into account both oxide break-down and hot carrier degradation are presented.

2.1 Gate-Oxide Breakdown

Gate-Oxide breakdown is the sudden formation of a conductive path in the gate-oxide of a MOS device as a result of application of a high voltage. The allowable gate-oxide voltage becomes smaller as the gate oxide thickness is reduced in each process generation1_.

As can be seen in Fig. 2.1, the channel voltage varies from the source to drain. As a result, the oxide stress, the voltage difference between the top of the oxide and the bottom of the oxide is a function of position. The highest stress areas occur at the source and drain oxide edges and therefore from a design standpoint, we must ensure that the gate-source and the gate-drain

1_{The rule of the thumb is 5MV/cm oxide thickness, for example 250nm CMOS 2.5V and}

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source-side stress= drain-side stress= Distance Voltage V_D VG-VT VS Bottom of Oxide Top of Oxide VGD V_GS (VG) Channel Depletion

Fig. 2.1: Gate oxide breakdown in a MOS transistor [2] voltages (VGS and VGD) never exceed pre-specified values, by design [2].

Although it is often assumed that oxide breakdown occurs instantly at a predetermined ”breakdown voltage,” in fact the failure is a probabilistic event, with increasing probability as voltage, stress time, or oxide area are increased [2].

Oxide breakdown is considered a two-step process [14]. A gradual build-up of damage occurs in the oxide before the sudden formation of a breakdown path. The anode-hole injection model [15], the anode hydrogen release model [16] and the thermochemical model [17] have been proposed for describing the degradation of oxide breakdown.

After a breakdown path has been formed it can manifest itself in different ways [18]:

• In hard breakdown, a large gate current increase can be observed. This type of breakdown is typically found in thick oxide devices and high voltage stress, which is not addressed in this thesis.

• In soft breakdown [19] a small sudden gate current increase and a sudden gate current noise increase is observed.

• Progressive breakdown [20] is the term used for the non-instantaneous formation of a hard breakdown path.

Hard breakdown has the most disastrous effect on device performance. The effect of progressive breakdown is similar, but only after the degradation has progressed significantly.

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2.2 Hot Carrier Degradation

Hot carrier degradation is an effect caused by high energetic charge carriers flowing in the channel of a mosfet. In short channel devices, the lateral field can be extremely high, and consequently carriers can achieve a very high en-ergy before losing momentum to a collision with the crystal lattice. Some of these ”hot energy carriers” collide with the lattice before arriving at the drain with sufficient energy to result in impact ionization, see Fig. 2.2 [2]. This, in addition to potential avalanche multiplication, can result in surface defects, resulting in a reduced carrier mobility in the channel. This can also result in trapped charge in the gate oxide or oxide/silicon interface, shifting the local threshold voltage. Usually this damage occurs in the drain region where the electric field is very high, causing the damage to manifest itself as an increase in on-resistance and knee voltage, reducing the power amplifier performance. Unlike the gate oxide breakdown, the hot carrier degradation is not intrin-sically catastrophic. Instead, it causes a gradual degradation in the device performance over a period of time [2].

Fig. 2.2: Hot carrier degradation in a MOS transistor [2]

Although hot carrier degradation is caused by a different mechanism than gate-oxide breakdown, the damage due to hot carriers can result in an increased rate of gate oxide damage [2]. For hot carrier degradation to be noticeable, it is necessary to have high drain-source voltage, and substantial drain current, at the same time. Thus, from a circuit design perspective, the hot carrier degradation can be prevented by avoiding channel current when drain voltage is high. This happens ordinarily in a switching amplifier (e.g. Class-E power amplifiers), where high efficiency is achieved by having a small transistor volt-age while the transistor conducts current and vice versa, making switching power amplifiers less prone to hot carrier degradation. However, hot carrier degradation can be a serious issue in linear power amplifiers [2].

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2.3 Punch-Through

Under normal circumstances the drain-source current of a MOS transistor flows close to the surface when a large enough gate bias is applied to create an inversion channel. In the absence of a gate bias, very little current flows because the drain-bulk and the source-bulk diodes are effectively connected back-to-back with opposite polarities. As larger voltages are applied to the drain, the drain-bulk depletion region extends farther to accommodate the electric potential drop. This depletion region will eventually extend all the way to meet the depletion region of the source-bulk junction, thereby diminishing the potential barrier that stops the direct flow of current between the drain and the source, as depicted in Fig. 2.3(a) [2]. This punch-though process results in a large current flow that can occur even in the absence of any significant gate bias (Fig. 2.3(b)). This punching effect already gives rise significant increase in drain current before the depletion regions touch: When they approach each other, the potential barrier height drops rapidly, increasing current from one side to the other. Punch-though is exacerbated by smaller channel length, and larger VDS. The significance of punch-through reduces rapidly with increasing

channel length [2].

V

DS

I

DS

Fig. 2.3: (a) Punchthrough in a MOS transistor. (b) The effect on the I-V curve [2]

Punch-through is not intrinsically destructive, although the simultaneous occupance of high voltage and high current can easily result in thermal failure if sustained. However, the process can generate its own hot carriers, potentially causing similar reliability issues as discussed in section 2.2. From a design perspective, punch-through can be dealt with by making sure that VDS and

VDB of a single transistor remains at all times below a certain pre-specified

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2.4 Drain-Bulk Breakdown

In a standard CMOS process the bulk is connected to a fixed electrical poten-tial and the drain-bulk diode experiences a reverse bias directly proportional to the absolute drain voltage, VD. This diode has a reverse breakdown

volt-age primarily determined by the doping of the bulk (the lightly doped side). Therefore, it is important to make sure that the drain-bulk voltage does not reach this breakdown voltage in addition to maintaining smaller than its crit-ical level [2]. Fortunately, this breakdown voltage is relatively high in todays CMOS processes (e.g., ≥ 10 V in 65 nm CMOS).

2.5 Negative Bias Temperature Instability

Negative Bias Temperature Instability (NBTI) effect is created by trap gen-eration at the Si/SiO2interface in PMOS transistors under the negative bias

condition at elevated temperatures and degrades the device driving current. The interaction of inversion layer holes with hydrogen passivated Si atoms can break the Si-H bonds, creating an interface trap and one H atom that can diffuse away from the interface (through the oxide) or can anneal an existing trap [21]. The broken bonds act as interfacial traps and increase the threshold voltage of the device, thus affecting the performance of the integrated circuit. A similar mechanism can be observed in NMOS transistors labeled PBTI [18]. NBTI impact gets more severe in scaled technology due to higher die tem-peratures and utilization of ultra thin gate oxide [21]. When PA topologies involving PMOS transistors are used NBTI effect should be taken into account.

2.6 RF CMOS Power Amplifier Breakdown Simulation

Methodology

The occurrence of a breakdown event in the gate-oxide of a MOS transistor, may not necessarily lead to circuit failure, first shown in [10] for digital circuits. In [22]- [24] the impact of breakdown paths on RF Power Amplifier (PA) per-formance was investigated and the results showed a very high robustness, even to multiple gate oxide breakdown events. If multiple breakdown events can be accurately taken into account for predicting circuit lifetime of such circuits, de-sign guidelines may be relaxed, allowing higher voltage levels and hence higher output power of the power amplifiers or longer life-time for the same voltage levels. Therefore, a reliability simulator that incorporates multiple breakdown effects is a very beneficial tool for RF power amplifier design.

In this section, the simulation methodology of Guido Sasse [25] for assess-ing circuit-level failure probability of RF circuits that can withstand multiple oxide breakdown events is introduced. The simulation methodology makes use of the model shown in Fig. 2.4 and Spectre as circuit simulator. Up to present such a simulator has never been shown before [25]. This simulator can be used by circuit designers in order to increase performance of RF circuits as the re-striction on the maximum allowable voltage levels can be relaxed for individual

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circuits. The simulator combines both multiple gate-oxide breakdown effects and hot carrier degradation. The model used for degraded MOS operation is based on well-accepted models for these effects.

Fig. 2.4: Degraded MOSFET model as it is used in the simulator for describing both oxide breakdown and hot-carrier degradation

Present-day reliability simulators [26], [27] typically only include effects of hot-carrier degradation and/or NBTI. Modules for incorporating gate-oxide breakdown have been developed such as in [28], but here circuit failure was assumed to coincide with the first breakdown event in a circuit. In this relia-bility simulator, a new methodology is presented in which multiple breakdown events can accurately be taken into account for predicting the lifetime of RF CMOS circuits.

The simulation model described in this section takes into account the effect of gate-oxide breakdown and hot-carrier degradation. The simulation model makes use of the model shown in Fig. 2.4 for modeling degraded MOS tran-sistor operation. The two conductances GBD,D and GBD,Sare used to model

gate oxide breakdown, while the voltage source ∆VT and the current controlled

current source (CCCS) Ac· ID take into account hot-carrier degradation.

The model used for describing post-breakdown behavior of MOS transistor is based on the work done by [10]. In that work, the breakdown path was modeled as a conductive path of ∼1 mS and the effect of this conductive path on MOS transistor performance was related to the location of the path with respect to the channel. Breakdown paths located near the drain and source regions proved to exhibit the most disastrous effect on device performance. Breakdown paths in the middle of the channel are manifested as conductive paths with a conductance ≪1 mS. Only breakdown events occurring at the overlap regions are considered in the model in Fig. 2.4. This assumption is allowed for the circuits put under investigation in this thesis: in these circuits the probability of inducing breakdown paths in the overlap regions exceeds the probability of inducing them elsewhere by far, due to the relatively high levels

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of the gatedrain voltage VGD in the MOS transistors used in these circuits.

Degraded MOS transistor performance after hot-carrier stress is assumed to originate completely from the generation of interface states. The model takes into account a threshold voltage shift as well as a reduction in the channel mobility; these are both related to the number of generated interface states through [9]: ∆VT = 1 ηV T q∆Nit AGCox (2.1) 1 µi = 1 µ0 1 +Kµ∆Nit AG (2.2) In these expressions ∆Nitis the number of generated interface states. AG

is the total gate area of the device, ηV T and Kµare technology dependent

pa-rameters, q is the elementary electron charge and Coxis the oxide capacitance

of the device. Furthermore, µ0refers to the channel mobility of an undegraded

device and µito that of a degraded device. The degradation in channel

mobil-ity is accounted for by the CCCS Ac· ID in Fig. 2.4. The following expression

can be derived:

Ac =

α∆Nit

1 + α∆Nit (2.3)

Here, α is a constant, dependent on parameters µ0, Kµand AGin equation

(2.2). The oxide breakdown parameters GBD,D and GBD,S are given by:

GBD,D= nBD,D· 10−3 S (2.4)

GBD,S= nBD,S· 10−3S (2.5)

Here nBD,D and nBD,Srefer to the number of breakdown events that have

taken place at the gatedrain respectively gatesource overlap region.

For simulating circuit performance of circuits that have been under opera-tion for a given amount of time, the appropriate values of the model parameters of Fig. 2.4 if Nit, nBD,D and nBD,Sare known.

Further details of the modeling of the degradation rate of the simulator and the implementation of the simulator can be found in [18] and [25]. The RF reliability simulation model is used in chapter 5 in life-time prediction of different classes of power amplifiers.

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Chapter 3

Theory: Class-E Power

Amplifier

3.1 Abstract

This chapter presents the analytical solution in time domain for the ideal single-ended Class-E Power Amplifier (PA). Based on the analytical solution a non-iterative procedure for choosing the circuit parameters is presented for Class-E PAs with arbitrary duty-cycle and finite dc-feed inductance (e.g., con-tinuously ranging from Class-E with small finite drain inductance to Class-E with RF choke). The obtained analysis results link all known Class-E PA design equations as well as presenting new design equations. An important reliability concern ”peak drain voltage” is shown to be dependent on the duty-cycle. The result of the analysis gives more degrees of freedom to designers in their design and optimization by further expanding the design space of Class-E PA1_.

3.2 Introduction

The Class-E tuned power amplifiers introduced by [29], [30] offers a means of highly efficient power amplification. The Class-E power amplifier consists of a load network and a single transistor that is operated as a switch at the carrier frequency of the output signal. The most simple type of load network consists of a capacitor shunting the transistor and a series-tuned output circuit, which may have a residual reactance shown in Fig. 3.1. Note that the total shunt capacitance C is due to the intrinsic transistor capacitance (Cint) and the load

network capacitance (Cext). The Class-E PA eliminates the power losses due

to the discharge of the output capacitance of the transistor in an elegant way

1_{This chapter was published in IEEE Transactions on Circuits and Systems I}

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by making sure that the voltage (VC) is zero at the moment the switch is closed see Fig. 3.1. Cint Cext L C0 L0 X R C L _C 0 L0 X R IR IC IL IS V_C VC (t)/V D D

V

DD

V

DD tuned at

time

Fig. 3.1: (a) Single-ended Class-E PA (b) Idealized model of single-ended Class-E PA

After the first introduction of Class-E PAs by Ewing [29] in his doctoral thesis in 1964 many papers analyzing Class-E power amplifier have been pub-lished [30]- [49] and many different aspects of Class-E power amplifier (PA) has been analyzed. The published papers can be categorized in two main groups: Class-E PA with RF choke [29]- [38] and Class-E PA with finite dc feed inductor [39]- [49].

The ideal Class-E PA with RF choke has been analyzed and the analytical design equations are given in the literature [30, 31].

An early analysis of Class-E PAs with finite dc feed inductance is published by [39] in 1987, followed by e.g. [40] and [41]. The common property of all these papers [47] is that the procedure for obtaining the final circuit design elements is either long, complex and iterative [39], [40] or does not provide much insight into the circuit design or is not analytically exact [41]. The inclusion of some effects such as finite switch-on resistance, finite load quality factor etc. are

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reported to turn the design procedure into an even more lengthy and iterative process [44]- [46].

This chapter presents an analytical solution for the ideal Class-E PA, show-ing the relation between the circuit elements and the input parameters. The solution reveals the existence of infinitely many design equations for the ideal Class-E PA shown in Fig 3.1b due to freedom in the value of the dc-feed inductor and in the switch duty-cycle. Based on the analytical solution a non-iterative procedure for choosing the circuit design elements is presented in this chapter. The given design equations in [31], [49] and [50] are subsets of the analytical design equation in this chapter. The presented analytical design equations expand the design space of Class-E PA, thereby offering much more freedom in the design procedure of a Class-E PA.

In this chapter:

• The analytical design equations for ideal single-ended Class-E and their derivation are given. An arbitrary switch duty-cycle is allowed which is very important in Class-E PA design [52] whereas only 50% duty-cycle case is considered in [3].

• A design optimization routine for Class-E PA is introduced; this helps design optimal Class-E PA under certain boundary conditions.

The outline of this chapter is as follows. Known Class-E PA design equa-tions are briefly discussed in section 3.3. The derivation of the Class-E PA equations as well as the assumptions, the circuit description and the main highlights of the derivation are explained in section 3.4. The Class-E wave-forms obtained as a result of the analysis are shown and interpreted in section 3.5. A number of applications utilizing the infinitely many solutions of Class-E are given in section 3.6. Section 3.7 summarizes the most important findings in this chapter.

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3.3 Known Design Equations

Tab. 3.1: Known explicit design equations for Class-E

[31] [49] [50]

In literature, design equations for Class-E PA can be found that can be used to set the correct values for components in a Class-E PA circuit. For the circuit in Fig 3.1 different design equations are reported in [31], [49] and [50]. These different design equations form different design sets K = {KL, KC, KP, KX},

each consisting of values KL, KC, KP and KX that relate circuit component

values to input parameters such as supply voltage, operating frequency and output power2_{as illustrated in Fig. 3.2.}

w C LXorCX POUT R L VDD 2 KP(q,d) KL(q,d) KX(q,d) KC(q,d)

Fig. 3.2: Drawing to show the relations between the elements of the design set K

The design sets in [31], [49] and [50] are summarized in Table 3.13

The three design sets K given in Table 3.1 are specific forms of the Class-E PA shown in Fig 3.1, with their specific assumptions:

• the design set corresponding to the work in [31] assumes an RF-choke: L → ∞,

2_L₀ _{and C}₀ _{seen in Fig 3.1 can be determined from the chosen quality factor (Q} L =

ω0L0/R) where ω0= 1/√L0C0. For the physical meaning of the design set elements K see

Appendix-A.

3_{In [31], some symbols (e.g. ψ, B) similar to the design set K elements are used. In order}

to prevent any confusion we find it wise to show the relation between the given symbols in [31] and in this chapter ψ = tan(KX), B = KC/R.

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• the parallel circuit Class-E PA in [49] and [48] assumes a zero reactance for X.

• the even harmonic resonant Class-E PA in [50] assumes that 1/√LC = 2n where n = 1, 2, 3, ...∞.

All of these three subclasses of the Class-E PA (in Fig 3.1) have their specific advantages and disadvantages. It is reported that the Parallel Circuit Class-E PA [48], [49] and the Class-Even Harmonic Resonant Class-Class-E PA [50] are more size-efficient than the RF-choke Class-E PA [31]. In comparison to RF-choke and Even Harmonic Resonant Class-E the Parallel Circuit Class-E PA allows using higher load resistance, which typically results in a more efficient output matching network and in a possible reduction in the required supply voltage, which might enable the implementation of the Class-E PA in low-voltage tech-nologies. On the other hand, using an RF-choke reduces the sensitivity of the Class-E PA to drain inductance variations.

This chapter presents an analytical solution for the design set K for Class-E PAs. This solution shows the existence of not only the aforementioned 3 design sets, but of infinitely many design sets K due to freedom in both the value of dc-feed inductance and in the switch duty-cycle. This yields much more design freedom and much more opportunities to trade advantages and disadvantages of the many design sets K.

3.4 Analytical Analysis of Class-E PA

5 3 4 2 0 1 4 2 3 1 0 0 0 0 d=1.2 d=1 d=0.8 d=1 d=0.8 d=1.2 p/w 2p/w p/w 2p/w 0 switch-on switch-off

V

C

(t)/V

D D

I

S

(t)/I

0 switch-on switch-off

time

Fig. 3.3: Normalized switch voltage and switch current of RF choke Class-E PA for d = 0.8, 1 and 1.2

Analysis of the Class-E PAs are already described in literature, see e.g. [31], [39], [46], [48], [49], [50] and [51]. In [31], [49] and [50] an analysis only for

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one sub-class of Class-E PAs is done. The analysis given in [39], [46] and [51] are based on Laplace transform technique and provide only particular solutions with the presentation of the load network parameters in a table format [48]. In the analysis given in [48], only 50% switch duty-cycle operation is considered and numerical solution techniques are used to derive design equations. In this chapter, a complete analytical derivation is done for ideal Class-E PAs with finite dc-feed inductance and arbitrary duty-cycle. This section presents the analytical derivation of design sets K for Class-E PAs. The complex math-ematical results of the current section are simplified and discussed in some detail in sections 3.5 and 3.6.

3.4.1 Circuit Description and Assumptions

The circuit schematic of the Class-E PA is given in Fig. 3.1. In the analysis and derivations in this chapter a number of assumptions are made:

• the only real power loss in the circuit occurs on load R

• the switch is lossless with zero on-resistance and infinite off-resistance • the loaded quality factor (QL) of the series resonant circuit (L0and C0)

is high enough in order for the output current to be sinusoidal at the switching frequency

Fig. 3.3 illustrates the switching behavior and the switch definition used in this derivation: in the time interval 0 ≤ t < d · π/ω the switch is closed and in the time interval d·π/ω ≤ t < 2π/ω it is opened. This switching action repeats itself with a period of 2π/ω. Note that the chosen value of d determines the switch duty-cycle. For example, d = 1 corresponds to conventional 50% switch duty-cycle operation.

In order not to have any switching losses it is necessary to satisfy the following well-known Class-E conditions 3.1 and 3.2 [30, 31]:

VC(2π/ω) = 0 (3.1) dVC(t) dt _t=2π/ω = 0 (3.2) 3.4.2 Circuit Analysis

Two fundamental boundary conditions (e.g. continuity of the capacitor voltage and the continuity of the inductor current) are used together with the Class-E conditions ((3.1) and (3.2)) in order to solve the relation between the input parameters and the circuit element values in Class-E PAs.

In the analysis, the current into the load, IRsin(ωt + ϕ), is assumed to be

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resonant network consisting of L0and C0. It is however a widely used

assump-tion that simplifies analysis considerably: In the time interval 0 < t < d · π/ω, the switch is closed and hence the capacitance voltage VC(t) = 0 and the

cur-rent through the capacitance IC(t) = C · dVC(t)/dt = 0. In this time interval,

the switch current IS(t) is

IS(t) = IL(t) + IRsin(ωt + ϕ)

=VDD

L t + IL(0) + IRsin(ωt + ϕ) (3.3) where IL(0) = −IRsin(ϕ)

In the time interval d · π/ω < t < 2π/ω, the switch is opened. Then, in the Class-E PA the current through capacitance C is

IC(t) = 1 L Z t dπ/ω (VDD− VC(t)) dt + IL dπ ω + IRsin(ωt + ϕ) (3.4)

Relation (3.4) can be re-arranged in the form of a linear, nonhomogeneous, second-order differential equation after substituting IC(t) as C · dVC(t)/dt and

differentiating both sides with respect to t. LCd

2_V C(t)

dt2 + VC(t) − VDD− ωLIRcos(ωt + ϕ) = 0 (3.5)

which has as solution

VC(t) = C1cos(qωt) + C2sin(qωt) + VDD− q2 1 − q2pVDDcos(ωt + ϕ) (3.6) where q = 1 ω√LC (3.7) p = ωLIR/VDD (3.8) C1= nq2cos (2 qπ) cos (ϕ) 1 − q2 p + (3.9) sin (2 qπ) q sin (ϕ) 1 − q2 p − cos (2 qπ) o VDD C2= nsin (2 qπ) q2cos (ϕ) 1 − q2 p − (3.10) q cos (2 qπ) sin (ϕ) 1 − q2 p − sin (2 qπ) o VDD

The coefficients C1 and C2 follow from the Class-E equations (3.1) and (3.2).

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of VDD and ω only if d, q, p and ϕ are known. In Appendix-A, the physical

meaning of d, q and p are explained. The derivation of these four parameters is the next step in the derivation of the Class-E design equations.

To derive expressions for the four unknowns so far, d, q, p and ϕ initial off-state conditions: VC(dπ/ω) = 0 and IL(dπ/ω) = VDDdπ/(ωL) − IRsin(ϕ)

can be used.

The following two non-linear relations for ϕ, p, q and d follow from the initial off state conditions. These two relations can be used to solve ϕ and p analytically in terms of q and d which yields, together with (3.6), (3.3) the solution of any Class-E PA. Therefore, here q and d are chosen as free design variables. In theory, q can take any positive real value and d can take any real value4_{in the range 0 < d < 2. The two relations for ϕ, p, q and d are:}

f1(p, ϕ, q, d) = p a1(q, d) sin(ϕ) − (3.11) b1(q, d) cos(ϕ) − c1(q, d) = 0 f2(p, ϕ, q, d) = p a2(q, d) sin(ϕ) − (3.12) b2(q, d) cos(ϕ) − c2(q, d) = 0

The functions a1(q, d)...c2(q, d) and the details of the analytical solution for p

and ϕ are given in the Appendix-B.

3.4.3 Design sets for Class-E operation

The mathematical derivation of the existence of infinitely many solutions due to freedom in the value of dc-feed inductor and in the switch duty-cycle leading to true Class-E operation can be simplified considerably, yielding an easy-to-use design procedure for Class-E PAs. In the previous subsection, it was men-tioned that p and ϕ both can be solved as a function of q and d; the resulting relations are shown in Fig 3.4. Using the relations for ϕ, p, q and d design set K = {KL, KC, KP, KX} can readily be derived.

KL : The expression for KL can be derived by using the fact that (with the

assumption of an ideal switch) the conversion efficiency from DC power to AC power is 100%:

IR2

R

2 = I0VDD (3.13)

4_{In practical designs, the useful range of both q and d are limited as will be shown later}

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d=1.2 d=1 d=0.8

p

q

j

d=0.8 d=1 d=1.2

q

Fig. 3.4: (a) p(q, d) and (b) ϕ(q, d) as a function of q for d = 0.8, 1, 1.2 In this relation, I0 is the average supply current5:

I0= ω 2π Z 2π/ω 0 IS(t) dt = IR πd2 4p − d 2sin(ϕ) − cos(dπ + ϕ) 2π + cos(ϕ) 2π (3.14) Substitution of (4.9) and (3.8) in (3.13) yields

KL(q, d) = p d2_π 2p − cos(dπ+ϕ) π − d sin(ϕ) + cos(ϕ) π (3.15) Since p and ϕ both are functions of q and d as given in the Appendix-B and plotted in Fig 3.4, KL(q) is a function of e.g. only q and d.

KC: KC follows directly from (3.7) and (3.15):

KC(q, d) =

1 q2_K

L(q, d)

(3.16) KP: An expression for KP as a function of p and q can easily be found using

IR =p2POUT/R and (3.8): KP(q, d) = 1 2 p2 KL(q, d)2 (3.17)

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KX: An analytical expression for KX can be derived using two

fundamen-tal quadrature Fourier components of VC(t). The analytical expression for

KX(q, d) in terms of q and d is given in Appendix-B.

VR= 1 π Z 2π/ω 0 VC(t) sin(ωt + ϕ) dt VX = 1 π Z 2π/ω 0 VC(t) cos(ωt + ϕ) dt KX(q, d) = VX VR (3.18)

The values for KL(q, d), KC(q, d), KP(q, d) and KX(q, d) are plotted in

Fig. 3.5 as a function of q for d = 0.8, 1 and 1.2. Fig. 3.5 shows that all the elements of the design set K depend very much on both q and d. For example, the maximum value of KCfor d = 0.8 can be about 4.2 times higher

than the maximum value of KC for d = 1.2; allowing using wider transistors6.

Besides, the peak value of the switch voltage, VC(t), for d = 0.8 is observed

to be smaller than that for d = 1.2, which is an important feature for Class-E PA design in technologies with low break-down voltages.

In Fig.3.6, normalized output power (U = POU T

IM AXVM AX) is given as a function

of q for d = 0.8, 1 and 1.2. Fig.3.6 shows that U is a strong function of both q and d; U is maximum for d = 1.

6_{Generally, in Class-E PA design the parasitic output capacitance of the switch}

(transis-tor) should be smaller than C = KC/(ωR) ; implying that higher KCallows wider transistors

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d=1.2 d=1 d=0.8 d=0.8 d=1 d=1.2 d=1 d=1.2 d=0.8 d=0.8 d=1.2 d=1

q

K

_P

K

_C

K

_L

K

_X

Fig. 3.5: Elements of the design set KP(q), KC(q), KL(q) and KX(q) as a

function of q for d = 0.8, 1, 1.2 0.06 0.02 0.1 0.08 0.04 2 1.5 1 0.5 0 0.12 q d=1.2 d=1 d=0.8

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3.5 Waveforms

Section 3.4 showed that the design set K = {KL, KC, KP, KX} is a function

of q and d therefore, there exist infinitely many Class-E realizations for a chosen value of d. Although the switch voltage waveforms of all these Class-E realizations satisfy (3.1) and (3.2), the Class-E waveforms for different design sets are different. The Class-E waveforms and the implications on Class-E design are discussed in this section.

3.5.1 Achievable Waveforms

For different values of q and d, the Class-E waveforms exhibit significantly different peak voltage and peak current values, having their own pros and cons in circuit design. Therefore, investigation of Class-E waveforms is important from an application point of view. Implementing a Class-E PA using a single transistor, as in Fig 3.1a, the following properties of Class-E waveform are important:

• the peak value of the switch voltage should be sufficiently low not to exceed the breakdown voltage limits of the transistor.

• the value of the switch current at turn-off moment should be sufficiently low when the switch (transistor) is driven by a sinusoidal driving signal7_.

• the rms value of the switch current8, the inductor, L, current, the capac-itor, C, current and the load current should be low to minimize resistive power losses.

As mentioned, Fig 3.3 shows that the waveform of the switch voltage and the current strongly depend on d. For d = 0.8 (40%), the peak value of normalized switch voltage is about 30% lower than the peak value of switch voltage for d = 1.2 (60%). However, it should also be noted that both the maximum value of the switch current and the value of the switch current at the turn-off moment are much higher for d = 0.8 than for d = 1.2.

Fig 3.7 shows a number of normalized signal waveforms in the Class-E PA as a function of time for different values of q for d = 1 (50%). In the figure, the switch voltage is normalized with respect to the supply voltage; the switch current, the load current, the capacitor, C, current and the inductor, L, current are normalized with respect to the dc current (I0).

As q goes from the conventional 1.412 to 2.2 the peak value of the nor-malized switch voltage increases from 3.56 to (approximately) 4. Fig 3.7b shows that for high values of q the switch current, at the moment the switch is opened, increases. Fig 3.7d and Fig 3.7e show that the rms current in the capacitor, C and inductor also increase rapidly with increasing q.

7_{For sinusoidal driving signals of the switch (transistor) it is difficult to provide high peak}

values of the switch current when the input driving signal is going to zero [48].

8_{The on-resistance of the switch (transistor) is usually dominant over other resistive}

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V

C

(t)/V

D D

I

S

(t)/I

0

I

L

(t)/I

0

I

R

(t)/I

0

I

C

(t)/I

0 q=2.2 q=2 q=1.7 q=1.4 q=0 q=2.2 q=2 q=1.7 q=1.4 q=0 q=2.2 q=2 q=1.7 q=1.4 q=0 q=2.2 q=2 q=1.7 q=1.4 q=0 q=2.2 q=2 q=1.7 _q=1.4 q=0

Fig. 3.7: Normalized (a) switch voltage, (b) switch current (c) load current (d) capacitor, C current (e) inductor, L current for different values of q for d = 1.

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d=1.2 d=1 d=0.8

q IS_RMS/I0

Fig. 3.8: RMS value of the normalized switch current IS/I0 as a function of q

for d = 0.8, 1 and 1.2

The relation between q and the normalized load current shows a different behavior than that for the capacitor and the inductor current. The lowest rms value of the normalized load current occurs for q ≈ 1.4.

The rms value of the normalized switch current is shown in Fig 3.8 as a function of q. Fig 3.8 shows that from q = 0 to q = 2 the rms value of the normalized switch current decreases monotonically; from q = 2 to q = 2.2 the rms value of the normalized switch current increases.

It can be concluded from the results obtained above that there is no value of q that can satisfy all the four points of the ”wish list” above at the same time. However, depending on the importance of design criteria a reasonable value of q can be selected.

3.5.2 Extreme Waveforms

In the infinitely many Class-E solutions, some are very useful while others appear to be quite impractical because of their extreme waveform behavior. This section discusses the (regions of) most extreme behavior; for simplicity reasons d = 1 assumed. This value corresponds to conventional 50% switch duty-cycle. It was shown in this chapter that any q-value corresponds to a specific Class-E solution. Extreme behavior occurs for values of q where either

1. p(q, d = 1) → ∞, resulting in ϕ(q, d = 1) = 0 The design set K for this condition is {KL→ ∞, KC= 0, KP = 0, KX→ −∞}

2. ϕ(q, d = 1) = π/2, corresponding to p(q, d = 1) = π/2. The design set K for this condition is

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It can be shown that both of these situations occur once in every range 2n < q ≤ 2n + 1 where n = 1, 2, 3... Note that the first extreme Class-E PA has zero output power, while the second one has non-zero output power.

For the range 2 < q ≤ 3 the extreme behavior occurs for q = 2.422 and q = 3. Fig 3.9 shows the normalized voltage and the current for these two cases. Fig 3.9a shows that the peak value of the normalized switch current, for q = 2.422, approaches to ±∞ while the peak value of the normalized voltage reaches to 4. Fig 3.9b shows the same voltage and current for the case that q = 3: the peak value of the voltage reaches to ±∞ whereas the peak value of the current is around 3.5.

In the design of E PA, design sets K corresponding to extreme Class-E behavior should be avoided in order not to encounter infinitely high voltages or currents. Note that while only distinct q-values result in true extreme behavior, a small q-region around the distinct values result in impractical Class-E behavior.

IS(t)/I0 VC(t)/VDD

IS(t)/I0

VC(t)/VDD

Fig. 3.9: Normalized (a) switch voltage and switch current for q = 2.422, (b) switch voltage and switch current for q = 3. For both (a) and (b) d = 1 is assumed.

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3.6 Design Optimization

In this section, useful examples are given to help engineers in designing Class-E power amplifiers. The simplified versions of the analytical equations for only 50% switch-duty cycle operation given in this section allow the designers to design Class-E PAs without the need to use the analytical solution. However, by using the analytical solution, it is quite straightforward to derive simple design equations for arbitrary switch duty-cycle operation.

Section 3.5.2 discussed Class-E realizations with infinite currents or volt-ages; these infinitely large signals make it impossible to implement these Class-E PAs in any technology. However, also Class-Class-E realizations with finite sig-nals may be not feasible because of technology limits. This section discusses also practical, technology related, limitations to Class-E realizations. The technology-related limitations taken into account in this section are

• the breakdown limits of the active device (the switch), which sets the maximum value for VDD,

• the minimum value of the parasitic capacitance C, which is determined by the output capacitance of the active device,

• the minimum value of the load resistance R, which determines (with the quality factor of the components in the output matching network) the maximum acceptable losses of the output matching network,

• the parasitic inductances present in the circuit, which set the lowest value of inductors that can be used in the Class-E PA, and

• the tolerable physical sizes of passives, which sets an upper bound on the quality factor and maximum value of the reactive components.

Clearly these boundary conditions narrow the useful range of q, by excluding certain regions of q for a chosen d. The analytical design equations in this chapter enable the selection of the best performing true Class-E PA inside the remaining design space. A simplified approach as well as an example are provided in this section.

3.6.1 Simplified Design Equations

The exact analytical expressions are somewhat hard to handle. However, using the total design space for Class-E PAs typically is not very useful. A restriction to values of q that result in reasonable power output for manageable component values and quality factors enables a significant simplification for a chosen value of d.

In this section d = 1 which corresponds to the traditional 50% duty-cycle operation; clearly depending on the performance benefits different values of d can also be chosen and curve fitted by using the analytical solution given in this chapter. As explained, the switch duty-cycle has important impact on the

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performance of Class-E PAs especially at high frequency of operation (> 1GHz) [52]. The design space for which output power and component properties are very well suited for today’s applications and technologies corresponds roughly to the q-range 0 < q < 1.9 for d = 1.

For this q-range, the exact analytical expressions can easily be fitted to (four) simple polynomial expressions, each covering a part of the range.

1. for the range 0 < q < 0.6 and d = 1

the design elements KC, KP, KX don’t change significantly and KL >

10. Therefore, in this range the design equations for the RF-choke Class-E PA [31], see Table 3.2, can be used.

2. for the range 0.6 < q < 1 and d = 1

the exact results can be fitted reasonably well using second order poly-nomials. The resulting (fitted) design set relations are shown in Table 3.2.

Tab. 3.2: Design set for (0.6 < q < 1)

3. for the range 1 < q < 1.65 and d = 1

a reasonably accurate fit is presented in Table 3.3.

Tab. 3.3: Design set for (1 < q < 1.65)

4. for the range 1.65 < q < 1.9 and d = 1

a reasonably accurate fit is presented in Table 3.4.

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The difference between the fitted design equations and the exact analytical relations is in the order of ≈ 2%. The difference can be further reduced by curve fitting with higher order of polynomials.

In [47], similar simplified design equations for Class-E PA is obtained by applying polynomial curve-fitting techniques on the interpolated numerical solutions for the set K. The technique used in [47] depends on numerical solu-tion methods and the design equasolu-tions given don’t take into account capacitive values for X.

3.6.2 Optimum design sets

The choice for using one of the infinitely many possible design equations de-pends on the boundary conditions imposed by the operating conditions and by the technology. For example, the maximum output power for given R and VDD

is obtained for q = 1.412 where KP(q, d = 1) reaches its maximum. The

cor-responding design set K was already published in e.g. [49] through numerical solution methods:

Tab. 3.5: Design set for maximum output power

Similarly, for given R and C the maximum operation frequency is reached at q = 1.468 where KC(q, d = 1) reaches it’s maximum. The design set K for

maximum operation frequency is given in Table VI.

Tab. 3.6: Design set for maximum operation frequency

The design equations given in Table 3.4 for 1.65 < q < 1.9 is very useful in the design of integrated low power Class-E PAs. Mainly, there are two design challenges for low power Class-E (e.g. Biomedical applications or Low Power Sensors Systems etc. [53], [54]) PAs;

• Low output power with high power-added efficiency (PAE) • Small size

Two conventional approaches seen in the literature to design low power PAs are either to lower supply voltage [53] or to use a matching network to step-up the 50Ω antenna impedance to higher values in order to lower the output

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power. The former solution may require DC-DC converter like additional circuits increasing size, design complexity and cost while the latter solution may decrease the efficiency due to the loss in the matching network depending on the required impedance transformation ratio [55].

Using the design set in Table 3.4 for 1.65 < q < 1.9 will help to decrease the output power without the need to resort to methods such as decreasing the supply voltage or increasing the load resistance. Since POUT = KPVDD2 /R,

decreasing KP nearly to zero as q approaches to 1.9 helps to design low-power

Class-E PAs. Besides, the decrease in the rms value of the switch current for 1.65 < q < 1.9 as seen in Fig 3.8 helps decreasing the power loss on the switch; increasing PAE.

Clearly many more optimum design sets can be derived, each optimizing for some operating condition, for some component value or for some (in)sensitivity. 3.6.3 An Optimization Strategy

In the design phase of a Class-E PA, all the component values must be found for some target operating conditions. These operating conditions are in terms of (angular) frequency, output power and supply voltage. In this section, all the component values and operating conditions are grouped into a set P . For true Class-E operation the component values and operating conditions are linked together via the design set K(q, d). Note that X may be inductive or capacitive, depending on the sign of KX(q, d) or on the value of q: for example

for d = 1 if q < 1.412 then X = ωLX while for q > 1.412 X = −_ωC1_X.

K = {KC(q, d), KL(q, d), KP(q, d), KX(q, d)} = ωCR,ωL R , POUTR V2 DD ,X R P = L, R, C, POUT, VDD2 , ω, X

Inspection of the relations for the elements in K, shows that every element in K links three elements of P together; Fig 3.2 shows these relations graphically. In Fig 3.2, each circuit element or input parameter is placed in the corners of a triangle and the related design set element is shown in the inner part of the triangle. In the triangles for KC(q, d), KL(q, d), KX(q, d) two elements

are shared by the other triangles, whereas in KP(q, d) only one element R is

shared. Therefore, either VDD or POUT must be known in order to be able to

make a uniquely defined Class-E PA design. At the same time the set P turns into a smaller set P′ ₌n_{L, R, C,}POU T

V2

DD , ω, X

o .

It can be shown with the help of Fig 3.2 that if any two elements of the set P′ _{are known, the rest of the elements can be expressed in terms of q. For a}

chosen d the selection of a proper q, a q-value that satisfies possible boundary conditions in terms of e.g. component values, then fixes the total design. The next subsection presents two optimization examples.

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3.6.4 Design Examples

This section presents two applications of the analytical design equations to the circuit design of Class-E PAs. The design flows of these two examples are given in Fig 3.10 and Fig 3.11. In each of the flows two elements from P′ _are

assumed to be known a priori. The remaining variables then can be expressed in terms of q for a chosen value of d. A suitable q value that satisfies some particular boundary conditions can easily be selected from the graph, after which the Class-E design is completed.

pre-specified values: I =1 A V =1 V max max 0 0.06 0.02 0.1 0.08 0.04 2 1.5 1 0.5 0.12

P_OUT=V_{max max}I U(q,d)

d=1.2 d=1 d=0.8 PO U T q

Fig. 3.10: Design-1, Class-E Design Optimization Flow Chart

The aim in the first design example in Fig 3.10 is to demonstrate a proce-dure to find the maximum output power that can be obtained from a discrete transistor when it is designed as a Class-E PA. In this procedure, a discrete transistor with a certain maximum drain current (Imax= 1A) and drain

volt-age (Vmax = 1V) is assumed to be used for Class-E PA design. For power

amplifier designers it is very important to know in advance how much power can be obtained from a discrete transistor. The maximum output power can be determined from the transistor utilization factor (normalized output power), as POUT(q, d) = U (q, d)ImaxVmax. For the chosen duty-cycle a range of q can

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with arrow in Fig 3.10) q is restricted to the range 0 < q < 1.2 for d = 0.8. 12 10 8 6 4 2 pre-specified values: w = 1G rad/s P_OUT/V_DD2 = 1W/1V2 0.6 0.8 1.0 1.2 1.4 1.6 1.8 1 0.5 0 -0.5

q

R=K (q)

P

W

L=K (q)

L

C=

K (q)

K (q)/K (q)

X K (q)K (q)

P C P X P

=

nH

nF

W

L

R

C

X

Unknown design parameters

as a function ofqford=1

Fig. 3.11: Design-2, Class-E Design Optimization Flow Chart

In the second design given in Fig 3.11, the goal is to design a Class-E power amplifier with the angular frequency ω, output power and supply voltage are as ω = 1 G rad/s, POUT = 1 W and VDD= 1 V respectively. By using the design

set K the other design parameters are obtained in terms of q and plotted in Fig 3.11. Choosing a value for q finalizes the design. In this example d = 1 is assumed. A suitable q depending on the boundary conditions for the rest of the design variables can be chosen to determine all the design parameters. For example, the maximum load resistance R = 1.35 Ω is obtained for q = 1.412 for which the inductor (L), the capacitor (C) and the excess reactance (X) are 0.99 nH, 0.51 nF and j0 Ω respectively. Depending on the chosen value of QL the of L0and C0 can easily be determined and the design is finalized.

Power Amplifiers in CMOS Technology: A contribution to power amplifier theory and techniques

POWER AMPLIFIERS IN CMOS TECHNOLOGY:

A CONTRIBUTION TO POWER AMPLIFIER

THEORY AND TECHNIQUES

POWER AMPLIFIERS IN CMOS TECHNOLOGY:

A CONTRIBUTION TO POWER AMPLIFIER

THEORY AND TECHNIQUES

PROEFSCHRIFT

ter verkrijging van

de graad van doctor aan de Universiteit Twente,

op gezag van de rector magnificus,

prof.dr. H. Brinksma,

volgens besluit van het College voor Promoties

in het openbaar te verdedigen

op woensdag 2 februari 2011 om 14.45 uur

door

Mustafa Acar

geboren op 02 februari 1979

te Gaziantep/Turkije

Dit proefschrift is goedgekeurd door

de promotor prof.dr.ir. B. Nauta

Only when

the last tree has died,

the last river has been poisoned

and the last fish has been caught,

will we realize that we cannot eat money

Contents

List of Figures

List of Tables

Chapter 1

Introduction

Chapter 2

Reliability Issues and

Modeling of RF CMOS

Power Amplifiers

2.1

Gate-Oxide Breakdown

2.2

Hot Carrier Degradation

2.3

Punch-Through

V

I

2.4

Drain-Bulk Breakdown

2.5

Negative Bias Temperature Instability

2.6

RF CMOS Power Amplifier Breakdown Simulation

Methodology

Chapter 3

Theory: Class-E Power

Amplifier

3.1

Abstract

3.2

Introduction

V

V

time

3.3

Known Design Equations

3.4

Analytical Analysis of Class-E PA

V

(t)/V

I

(t)/I

time

time

p

q

j

q

q

q

q

q

K

K