Redesign of a computer control for a spark erosion machine
Citation for published version (APA):
vd Hombergh, P. J. F. J. (1982). Redesign of a computer control for a spark erosion machine. (TH Eindhoven. Afd. Werktuigbouwkunde, Vakgroep Produktietechnologie : WPB; Vol. WPB0004). Technische Hogeschool Eindhoven.
Document status and date: Published: 01/01/1982
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REDESIGN OF A COMPUTER CONTROL FOR A SPARK EROSION MACHINE
Pieter van den Hombergh WPB 0004
Erata bij rapport WPB 0004
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REDESIGN OF A COMPUTER CONTROL FOR A SPARK EROSION MACHINE
BY:
Date
Pieter van den Hombergh
December 1982
Summary
This report describes a few details of a redesigned interface between a dual processor micro computer system and an ~xperimental
spark erosion machine. Then fundamentals of sparkerosion are explaned, as well as some of the hard and software implementation details. An appendix is added which gives futher detail of the software involved.
For an exiting three years at the laboratory of 'Fysische Bewerkingen' at the University of Technology of Eindhoven I want to thank Ir. Kees Heuvelman and Frits Theuws. They. gave me enough, and sometimes to much, freedom to broaden my view of the proper usage of microcomputers in mechanical engineering applications. Also in the social aspect is worth noting.
Table of Contents
1 Introduction 1
2 The use of electro discharge machining 3
3 The process 4
3.1 The physical description of the process 4
3.2 The parameters to be considered 6
4 Control Theory 10
5 Performance Demand 17
6 The microcomputer system - 19
6.1 Motivations for multiple microprocessor computer systems 19
6.2 Dual bus architecture 20
6.3 The iSBC 80/20-4 22
6.4 The iSBC108A 25
7 Design of a busextension in a microcomputer controlled E.D.M
Machine 27
7.1 Definition of the problem 27
7.2 The status Quo 28
7.3 Bus definition 29 7.4 Functional characteristics 31 7.5 Universality 32 7.6 Additional features 32 7.7 Principals of operation 33 7.7. 1 Address decoding 34
7.7.2 The Interrupt and Interrupt Acknowledge 37
8 The monitor and loader software " , , .41
8.1 The major functions."." , .. , , 43
9 Software for the fybbus interface , ,., 45
9.1 Programming the process interfaces ,., 47
10 The Arithmetic Processing Unit, Software description 49
10,1 Data types , , , 49
10.2 Data storage , 49
10.3 Parameter passing 50
11 Evaluating expressions with the Arithmetic Processing Unit . . . . 51
12 Conclusions , 53
12.1 Optimizing strategies" .. , , .. , .. , , 53
12,2 Variable sample frequencies 56
12.3 User Interface , ,., ".,", " . , . , . 5 7
Introduction
1 Introdu¢tion.
page 1
In this r~port we want to present an introduction to a possible way of controlling a spark erosion machine. The complexity of the
1 Electrode 2 Workpiece 3 Servomotor 4 Dielectric system 5 Computer 6 Analy~er 7 Pulse generator 8 Servo amplifier 9 Power supply 10 Terminal
Fig 1. Spark erosion system.
process encourages the use of a programmable controller. Also most of the information in the process is available as electric signals, so a signal conversion (in energy type) is not necessary. These, and the fact that with the advent of more powerfull and cheaper (micro)computers programmable controllers are widely available and easily made enforce the use of microcomputers in this very application.
The use of microcomputers also allows new control strategies to be implemented rather easily, in contrast to the situation with hardware (hardwired) controllers. Amongst the strategies mentioned can be those which use some way of parameter adaptation
Introduction page 2
to optimize the process. Also the computers can be used to gather data on the process, which could be used for better understanding of the process and necessarry technology as well as to improve the available models on the process.
The main course of this report is a redesign of a computer to machine interface, which enables very flexible control program implementation. The main improvements can be found in the more flexible usage of a multi processor (micro)computer system.
Introduction
2 The use of electro discharge machining.
page 3
The spark~rosion process is gaining more and more impetus in the
toolmakin9 workshop. The physical properties of sparkerosion allows mO$t conducting materials to be machined, including very hard alloys, used for dies in metal working and plastic molding. In the die sinking way of machining, the erosive action of a great number of pulses is used to negatively copy an electrode shape into the tool to be. (Commonly the tool in for instance plastic molding is the workpiece in sparkerosion.) In only few applications, the sparkerosion process is used in mass production. The expence of the more commonly machined tools or dies enforces the usage of a well controlled and protected process, to defeat the possible loss of the workpiece due to process faults. Also many aspects of the sparkerosion process still have to be investigated. These points call for an automated machine which will allows both testing of control and protection strategies as well as to search for optimal machining conditions to enlarge the contents of a database on sparkerosion.
Process page 4
3 The process.
3.1 The physical description of the process.
carriers particles charge as the cause elementary momentum, which
Momentarily the most accepted theory describing the erosive mechanisme of sparks is a thermal process model. Across the gap between t~o electrodes, (workpiece and tool) which are placed in a dielectric fluid, a voltage is applied. As soon as, a for each combination of electrode materials, dielectricum and gap size characteristic voltage is reached, a spark will emerge. If the supplied energy per spark is sufficient, a small crater will be produced on each electrode surface. The life history of a spark is as follows:
The applied voltage will' (electrons and ions) to gain
1 channel building 2 ignition 3 discharge Phase! 1 I 2 3
Fig 2. Phases in spark history
Process page 5
lower ene~gy form of heat. (Phase 1) This heat development will locally heat the fluid. After a short time, the locally accumulated heat will cause vapour bubbles to appear. (Phase 2)
Fig 3. Spark Phase 1
Such a vapour bubble increases the electric field st~ength, and thereby allows the charged carriers to gain enough kinetic energy, to cause neutral atoms to be smashed to new electrons and positive ions. The cascading effect of producing charge carriers largely
Fig 4. Spark Phase 2
increases the current, and the discharge or breakdown occurs. The electron and ion currents hit the respective positive and negative electrode surfaces, and loose their momentum in return for the metal to get overheated, causing melting and vapourisation.(Phase
Process
3
, Fig 5. Spark Phase 3
page 6
The process involves two surfaces between which the sparks exist. The arisal of the electric discharge is introduced by the formation of a vapour channel, necessary for the actuation of a gas discharge.
3.2 The parameters to be considered.
The sparkerosion process is controlled by a number of parameters. Of these parameters some have to be considered fixed (defined by workpiece shape and material), others are controllable as machine settings, but remain fixed during machining, and again others are controllable during machining. The last mentioned can be used to optimize the process behaviour in terms of cost effectiveness through time efficiency, and terms of quality through dimension accuracy, roughness and surface integrity. However these process qualities cannot be measured during the process or on-line. They are so called offline measurement data. The data which can be measured
in
line have a relation to the final process quality (much of which is still under investigation), and can be used in the process control system to determine the optimal inline input parameters.Process page 8 u r- 1""""""'"\ I
.
t-O! ...--- .... ---'-'-'-j--.-
. ...._-...-. ! I :l I <Il ! .j,'"
I:
I , ItIl , Ie ! I I Ii 10 I 10 I I I I ,:rL---...
_-r-_~_-...- - - - -~ I , I l.. _ _... .. _ _ _ _ _ ... 1 __(1) : . $ I I I I I ti pulse duration to pulse interval tp pulse periodte efective spark duration
t
d ignj.tion delay
tr pulse rise (fall) time
U average working voltage
Ue average discharge voltage
Ui open circuit voltage
ie discharge current
ie average discharge current
I average working current
determined from the shape of of pulses, as is shown in the figure.
the (voltage) waveform of the A spark analyzer has been
1
LlO_D
nO
Standard td=O
Conditions u >u
e e
built into our machine which derives [6J As can be comprehended delay and pulse quality are the spark erosion machining.
Erosion these shapes. only ignition usable during Arc Open ee)UO td=t i A1 t <t n r r A3 no plasma noise
the pulse qualities from easily, of these data measurable in line, and The time from applying the pulse voltage untill breakdown occurs is called the ignition
Process page 9
delay. Tne average ignition delay proves to be a strong function of the ga~ conditions. These gap conditions are:
- fluid velocity.
- fluid temperature, contamination and dielectric strength. - gap width.
- first t±me derivative of the gap width or electrode speed. - pulse interval time.
These conditions are all very closely coupled to the electrode movement Cexept for pulse interval time) and thus the control loop of the electrode servo mechanism.
Apart from the ignition delay, other qualities can be recognized from the pulse shape. These quality characteristics allow the successive pulses to be ordered into several classes, which could be used in a control strategy. Some investigations show that there can be relations between the occurence of certain pulse classes and for instance electrode wear. As can be concluded from [ 4 ] the pulse quality classification should be considered in a control strategy design.
The timing and energy control of the pulses have significant effect on several important parameters in the process. For instance, the pulse interval time to has a direct relation to the ignition delay, due to the diffusion and spread time of dielectricum temperature and contamination.[ 1 ],[ 4] Pulse energy is by nature directly related to the material removal rate and roughness. Several investigators [4] show relationships between Tau= t.l<t.+t )=1 t It and relative electrode
1 1 0 0 P
wear. It is said that the start of the breakdown is the location where the main mechanisme for electrode wear is to be found. Therefore the increase of the number of pulses to achieve a certain material removal (apply a certain energy) will increase the wear function.
Control theory page 10
4 Control,Theory.
This chapter will describe the control theory which should form the fundaments for the functionality of the system blocks.
To design a system which controls a physical process, we must first get as good an idea of the behaviour of this process and the building blocks of the system in terms used in general control theories. We must therefore modelize the system at hand to derive the modules that interact with each other, as well as the parameters which influence the models behaviour. We are primarily concerned, not with the microscopic behaviour of a single spark, but with the macroscopic effects of a great number of sparks spread over a relativily (related to pulseduration) large time and space span. We therefore will only take macroscopic phenomena into consideration. The purpose of these brief investigations in literature is to fill in the parameters in the block we call the process. The ignition delay time t d is a function of the pause
flUSHIN; DOmCTRIe :.RCUIT , . I I i I
-1
'--_...J ---~ I I I $1_tIlIITWDl fIIDIIllT... I SYSTEM ~-I I I (LECTWO( I I ;£lUATDII IMPUlSES~-.-_lllIII'(__
1 r~---I , I , .. Ff_LIIlIP ,,
I I IFig 6. Block diagram control loops
time to the current electrode velocity v
f ' last two the local
i e and the voltage ui l as well as the dielectricum flow rate F and through the
Control theory page 1 1
dielectricum band T. Also electrode materials and dielectric characteristics of the dielectricum are of influence.
t d
=
f(ti,to,ie,ui,vf,F,b)The same goes for the other output variables E,B,O,K and A of the pulse analyzer, as well as the local contamination. The local contamination should be understood as a combination of both actual debris and a temperature rise. We immediately recognize a closed loop, the local contamination loop, which is of influence of the next pulse, as well as i t is a function of the spark quality and energy. ~he importance of the local contamination to the process has been shown in l i t [ 2,15,16]. There i t is mentioned that the local contamination greatly influences the breakdown of the next pulse. The concentration of debris, as well as the dielectricum temperature are very important to the process. A certain ammount of debris is necessary to enable the ignition; to much debris will cause arcing and short circuit or abnormal pulses. Less obvious, but also explicable is the influence of the electrode movement on the debris concentration. Two electrodes moving towards each other decrease the volume as well as the expelsion
!
Rfmi
Fig 7. Flow and servo interaction.
area through wich the dielectricum flows. This causes the local flow rate to be linear in the electrode speed.
major three comprises machine sparkereosion The complete subsections:
Control theory page 12
The flushing system to rinse the workpiece-electrode gap. The pulsegenerating subsystem.
Although ~hese systems interact through the actual sparkerosion process, they are as such independent of each other, and may be described seperately.
control loop consists of The inner~ost loop, closest to
electrode~workpieceGap control. the folloWing elements:
the This
actual process, is the
3 computers 4converters 1 process 2analyzer
+
""
g
''''''-
I-/
Fig 8. Servo control loop
1. Process which converts the electrode to workpiece gapsize and other parameters into gap voltage pulses with a certain shape. 2. Pulse analyzer which derives the ignition delay from the pulse voltage shape. The pulse analyzer can be considered an analogue to digital converter with a zero order hold circuit. The sample rate is directly coupled to the pulse frequency. 3. The servo micro computer which converts samples of the
td-value into a control voltage Ug with an algorithm yet to be
deriv~d. It can already be said that several parameters in
this algorithm are controlable by layer 4.
4. The Digital to analogue converter with its zero order hold circuit, power amplifier, hydro-electric valve, hydraulic linear servo motor and its transfer functions.
Control theory page 13
The linear motor consist of a cylinder with piston construction. The transfer function has been experimentally determined. The natural frequency wo appears to be 345 Hz. A Dowty Moog series 21
primary piston
Fig 9. Hydraulic servo
hydraulic servo valve is used to convert the electric signal from the power amplifier to a hydraulic value. This low flow servo valve employs a polarized linear electric force motor. The motor actuates a beam which controls two variable orfices or nozzles in a so called flapper nozzle construction. The regulated oil presure is balanced if the flapper is in its center position. The pressure difference between the two nozzles when the flapper is actuated by the linear electric motor is used to move the primary piston in its cylinder. This piston movement is translated into an oil flow to and from either connection channel with the main hydraulic motor. In this way the signal is hydraulically amplified. The transfer function of the valve assembly is a first order in series with a time delay. The electric amplifier is currently under construction. The old amplifier suffered from a rather low bandwidth. (The - 3 dB frequency was approximately 20 kHz) The phase angle of this amplifier was therefore of significance to the total loop transfer function. The new design has an improved bandwidth of approximately 100 kHz. The loop gain
Control theory page 14
frequency peak is therefore lower. A full description of this part of the hardware is available in [18].
The digital to analogue converter converts the 8 bit binary value applied by the servo micro computer to its zero order hold circuit or latch. The servo micro computer applies the servo voltage Ug through the Fybbus interface.
As a part of the control loop the pulse analyzer can be described as an analogue to digital converter with a zero order hold circuit. A brief description of the analyzer may look like this: The voltage across the gap during a spark pulse is compared to
-t I I I I f count enable
--JlllJill-r:---Jillnnnnnil-:--
.
I I ItJ...
c_o_u_n_t_s _ I. Fig 10. Functionallity analyzer.
to be processed
three voltage levels. The boolean output of the comparisons is used to enable counters, which count clock pulses of a 20 MHz clock. While the voltage is over level 3 counter 3 is enabled.
Control theory page 15
pulse qualities. (levels 2 and also enable values are compared in hardware with those types, and will classify each pulse. For a discription see lit [ 6 ]
As soon as the voltage drops below the level 3, the counter is stopped, and at the end of the pulse transferred to a latch (the zero order hold circuit). The value contained in this latch is equal to the ignition delay time expressed in increments of 0.05 microseconds. The count value will al~o be used to derive other counters). The of standard pulse more detailed
The resulting values for ignition delay and spark class can be read by the computer at seven successive addresses in the memory mapped i/o space. To enable correct measurement data, several programmable parameters for the digital pulse analyzer must be applied by initializing procedures in software. The detection levels Un can be altered manually, so that a certain degree of flexibility in pulse classification for experimental data gathering may be acheived.
On the same level as the servo control loop, the flow control loop also has a very direct interface to one of the parameters ~n the process, and should also always be controling its parameter, the dielectric flow rate, to prevent i t from going astray due to changes in the process because of changing gap shape, and thus flow resistance. The process is very sensitive for changes in local temperature and debris concentration, so i t is important to retain a constant flow rate in the gap. This control loop also employs a micro computer using an algorithm to control the flow rate. The flow rate and possibly a certain periodicity should be controlable from the higher integration levels.
We can now put the system together again, and we represent this as a kernel, formed by the actual process, covered with shells of increasing system integration. Sectorial cross sections represent the signal and or energy flow of each parameter of importance.
Control theory
Fiq 11. Inteqration levels.
page 16
The inner layers consist mainly of hardware, the process and its direct interfaces. The layers from two outward consist of computer hardware and soft (or firm-) ware. Three computers are involved in this experimental setup, the flow microcomputer, the servo micro computer and the main micro computer. Communication between the seperate layers can somewhat restricted, but generally all outer layers have a way to prescribe what the inner layers should do. All communication to the actual process flows through layer 1. Sectorial (like a pie) cross sections are defined as those hard and software parts which are involved ln controlling one of the parameters. For instance the dielectricum flow can be an optimizing parameter or an operator setting (given by technological information or test procedure), both of which have to be conveyed to the process through layers 2 and 1. Some sections may be very hard to recognize in the inner layers. (Such as electrode wear.)
The combination of the rings and the sectors can be consider as possible control loops which actuate the entire process.
Performance
5 Performance Demand.
page 17
To envisage the computational and data handling performance needed in our application, we will present some numbers.
Sparks can be produced in rates ranging from 500 Hz to a distance between pulses of a mere 2 microseconds. (500 kHz.) Although, as has been mentioned in previous chapters, we do not want to (or even can) look at every spark seperately, we want to loose as little of information as possible. Also, as the bandwidth of the servosystem is about 350 Hz, we want our system to produce a new control datum at least twice as fast, that is once per 1400 microseconds. This implies that the samples must be taken at about equal rates.
It is even advantegeous to set the sample time below half the shortest significant time constant, for this allows the use of standard contineous discription theories. Apart from controlling the servomechanism, several housekeeping and supervisory tasks, as well as to run some kind of control strategy program, has to be performed. Amongst these housekeeping task ~s the operator interface by means of a CRT terminal. This should not have any impact on the controlling performance in the inner process loops.
From these arguments a design goal was formulated for a system with following performance. (some of these specifications go beyond the information supplied in this text.)
Process:
Currents from 1 to 65 Amperes in 1 Ampere steps.
Pulse and Interval durations from 1 to 999 microseconds. In future: Pulse shape control.
Multi axis Control. Measurement:
Pulse data (ignition delay and quality) to be determined with 0.05 microsecond discrimination. Control:
Performance page 18
~nd 500 microseconds.
These data enecourage the use of a multiprocessor computer system as presented in this and previous reports [13J.
Computer system
6 The microcomputer system.
page 19
In the experimental system at hand three microcomputers are currently involved in controlling the entire process. Two of these computers share the same cabinet and are off the shelf OEM Intel iSBC80/20-4 single board computers. A third computer is an in house built single board computer. The two computers sharing the same cabinet are Multibus (a Intel defined multi master micro computer system bus) compatible. This allows them to access the bus equally well (except for priority which must be arbitrated), and therefore makes i t possible to share common resources like memory and i/o attached to the bus in additional printed circuit boards. At the time we started at the laboratory, the bus sharing mechanism was not used and was undone by removing a bus arbiter (to be mentioned) from one of the iSBC80/20-4 boards. As more knowledge of definition and power of the Multibus was achieved, the arbiter was reinstaled, and a auxilarry printed circuit board was purchased which includes memory (read write as well as read only) and i/o (both serial and parallel). These resources could then forth be accessed by both single board computers sharing cabinet, and more important, bus. Additionally a custom printed circuit board was designed and built to interface the computer system to the spark erosion machine. The subsequent paragraphs will describe these items to more detail.
6.1 Motivations for multiple microprocessor computer systems.
LSI circuit technology has reduced the cost of central processors to such a low level that the previously avoided concept of applying multiple processors to meet system performance requirements has now become an attractive and viable alternative. Several benefits accrue from such an approach. In addition to increased system performance and improve realtime response, modular system expansion capabilities may be realized.
computer system page 20
Discussions of the benefits of multiple system applications
motivation for this in system design.
multiple processor approach through in the A primary approaches is processor structures understanding of an provide will addressed objective
enhanced system performance and throughput. Enhanced performance is achieved through the partitioning of overal system functions
into tas~s that each of the multiple processors can handle
individually.
In general as the number of individual tasks any given processor must handle is reduced, that processors response time to new service requests will be reduced. A well planned multiple processor bus structure will allow new processors to be added to the system in modular fashion. When a new system function is added, more processing power can be applied to handle them without impacting existing processor task partitioning.
A master in our definition is any element on the system bus that may take control of the system bus (that is assert the address and control lines.). Among them are processor boards and DMA controllers. Slave elements include passive function on the bus, such as memory or non DMA interfaces to the outside world. (Note in this respect that slaves are not excluded from
power or 'intellegence'. Slaves cannot drive
any processing the address and control lines of the multimaster bus.)
6.2 Dual bus architecture.
One option for designers to implement multiple system is the use of a multiple master/single such a design every master uses the same bus to or read and write data to and fro memory or i/o.
processors in a bus structure. In fetch instructions Then the common bus rapidly becomes the bottleneck in the system, because the bus bandwidth· (or memory and i/o access time) will soon be saturated, so that masters may have to wait, idling, for the bus to become
available. This might severly limit the overal system
Computer system page 21
Use of the system bus can be minimized through the implementation of a dual bus architecture, existing of a global or multimaster and a local or private bus for each master. Local operations (like fetching instructions and internal data handling) will occur totaly without any use of the system bus and therefore greatly reduce the (system)bus access request by each master. Such a dual bus structure can readily be implemented with the 80/20-4 single board computer and the Multibus system bus.
Access to the system bus is only required when a global memory or i/o location is referenced during any data transfer. (Global means: accessible for bus masters.) The distinction between global and local residence of any location is defined through the physical address used in the reference. An address within the range of the on board resources will not require any multi master bus request. Only references in global i/o or memory space will nead the initiation and completion of a system bus request. If the system bus is currently idle, the requesting master will immediately be granted the bus. If the bus is not idle, the requestor will have to wait for both the current user to complete its cycle, and the arbitrition to grant the bus to the requestor. This arbitrition must also decide between priorities in access.
Several software operations such as mutual exclusion,
communication and synchronisation are essential in proper multi
processor usage on single problem solution. Resources
(predominantly i/o) that are shared between masters may preclude asynchronous or simultaneous use. (imagin the data written to a terminal through a serial port simultaneously used by two or more masters to send data.) A form of mutual exclusion must be provided to enable one processor to lock access of a shared resource by an other processor when i t is in a critical section of software. Such a critical section of software must complete execution before another master may start identical execution to gain access to the same resource. Semaphores (or communication flags) are often used to allow for software arbitrition of multimaster usage of resources. These semaphores (one for each
Computer system page 22
commonly ~sed resource) will be true if the device is available,
and false if not. Any master wishing to use such a device must
wait for its semaphore to become false, and set i t true upon
starting of the use. However the time between finding the
semaphore to flag 'resource available' and the setting of the
semaphore to 'resource in use' may be used for another master to
also find the resource available and attempting to use the
resource simultaniously. The 80/20-4 bus lock function can
provide for this, since the bus can not be granted to another
master while i t is locked. The master first finding the resource
to become available may lock the bus, retest the semaphore to be
sure no change has occured between the previous test and the lock,
and then set the semaphore to 'in use' before releasing the bus
for reuse by other masters.
In our first attempt to get things running, no i/o resources are
shared in such a way that the semaphore mechanism is necessary.
6.3 The iSBC 80/20-4.
The Intel 8080A CPU is central processor for the iSBC80/20-4.
~S2J2C
COMPA TtBlE
DEvICE
8INTERRUI'T
.ADDRESS BUS"r::)QUESTlINH sec so
Oil TA BuS SySTEM
• BUS
' - - - ' COI\lTROl BUS
2
PROGAAMMA8lE
TIMERS
Fig 12. iSBC80/20and ISBe80f20.4Block Diagram Showing Functional Components
Computer system page 23
under 2 microseconds. The 8080A has a 16 bit program counter which allows direct addressing of 64k (65,536 bytes) bytes of memory. An external stack (external to the processor chip) also addressed through a 16 bit address register (known as the stack pointer) ~llows data and program counter to be temporarily stored in a last in first out fashion. The size of this storage is only bounded by read write memory constrains. This stack size allows virtually unlimited subroutine nesting.
The iSBC80/20-4 contains 4k bytes of static read/write memory using 2114 RAMs. Sockets for up to 8k bytes of nonvolatile read only memory are provided on board. Read only memory may be added in 2k increments up to the full 8k by using 2716 EPROMs. All on boardmemcry references are performed at full processor speed.
Parallel i/o is available as 48 programmable i/o lines implemented with the 8255 programmable peripheral interface. . The system software must isue a configuration mode word to select the desired combination of i/o and or bidirectional ports. The flexibility of the i/o interface is further increased by the capability of selecting the appropiate combination of line drivers and terminators to provide the required sink current, polarity and drive/termination characteristics for each application. The 48 programmable i/o lines and signal ground lines are available as two 50 pin edge connectors which mate with flat cable.
A programmable communications interface using the Intel 8251 Universal synchronous/asynchronous receiver/transmitter is available as an on board resource. A software selectable baud rate generator provides the USART with all standard or non standard communication bit frequencies. The USART can be programmed by the system software to select the desired data transmission technique. The mode of operation, data format, parity and baud rate are all under this program control. Parity, overrun and framing errors are all detectable by the 8251. The interface on board provides a direct compatibility with a RS 232C compatible terminal or data set. The RS 232C command lines as
Computer ~ystem page 24
well as the data and signal ground line are available on a 26 pin edge connector.
For applications requiring additional processing capacity and the benefits of multiprocessing, the 80/20-4 provides full Multibus arbitrition logic. This control logic allows up to 16 masters to share the system bus with the addition of an external priority encoding/decoding network.
The bus arbiter/controller independent from the CPU
provides its clock. This own allows clock which is different speed masters to share resources on the same bus, and transfers via the bus proceed asynchronously. Thus, transfer speed is dependent on transmitting and receiving devices only. This design prevents slow masters from being handicapped in their attempts to gain control of the bus, but does not restrict the speed at which faster modules can transfer data via the same bus .- Once a bus request is granted, single or multibyte read/write transfers can proceed at a rate of 5 mega words per second. The iSBC80/20-4 also provides three programmable interval timers or event counters in the 8253 form factor. One of these timers is hard wired as baud rate generator for the serial i/o interface, and the other two are fully available for user application. These counters may be used to generate interrupts to achieve real time clocks and alike. A provision has been made by means of wire wrap pins to route the counter in and output signals to the outside world using the parallel i/o configuration drivers. The contents of each counter may be read after issueing the appropiate command.
An Intel 8259 programmable interrupt controller provides for eight interrupt levels. Four priority processing modes are available to the programmer, so that the manner in which requests are processed may be configured to match the application requirements. However, the nested mode of operation is most commonly used, as is in our system. The interrupt controller can accept requests from the various i/o modules, including the interval timers, as well as from slave boards residing under the system bus. The 8259
Computer system page 25
determines priority between requests and asserts the processor interrupt line to initiate the invocation of an interrupt service routine. Any interrupt source may be masked of by a single byte written to the interrupt mask register. The interrupt acknowledge cycle of the Intel MCS80/85 processors causes the interrupt controller to drive the data bus with a call instruction to a table containing eight interrupt routine vectors. The request may originate from 26 sources. Among them are two jumper selectable requests originating from the USART indicating respectivily receiver full or transmitter empty.
6.4 The iSBC108A.
The iSBC108A combination memory and i/o expansion board contains 8
CONTROL Sus
uSER DESIGNATED PERIPHE"Al.S
~
1.TE~.""T
D...
RoaR_'"UREOUEST 1'0LINES
LINlS
1.,..,T(RRynSOAICl""ATING FROM TME ""OGRAM«rIlABt,( COMMUNICATIONS INTERFACE
AflIDPROGRAM,..AILE PUUPHEIIlAllNTERFACIE ARE JU..flER SEL£CTAII,.I
Fig 13. ISBC 108AJ116A Combination Memory and I/O Expansion Board Block Diagram
k of read write memory implemented with dynamic RAM components and a 8202A dynamic RAM controller and 8, 16 or 32k of read only memory using 2716,2732 or 2764 programmable read only memories. The memory is accessable as two contiguous blocks of memory (one block for RAM and one for EPROM) The starting address of the blocks is hardware selectable by means of dip switches and wire wrap pins.
Computer system page 26
The i/o qn the extension board is almost identical to the i/o on
the iSBCSO/20-4 boards. The difference lies in the fact that no
interrupt controller nor an interval timer is available. The baud
rate gen~ration is semi hard wired, alterable with the USART
baudratebits and wire wrapping. The baud rate generation logic
also provides a 1 millisecond signal which can be used as a system
bus inte~rupt request for timing purposes. An on board register
contains the status of the eight available interrupt request
lines, and may be interrogated by the CPU. Each interrupt request
line is maskable under software control. Addressing of i/o and
Computer-Process Interface page 27
7 Design of a busextension in a microcomputer controlled E.D.M Machine.
The current Experimental E.D.M. Machine of THE WPTFYB J.S a
microcomputer controlled system. This chapter presents the definition of a straightforward bussystem, which can provide for the interconnection of several peripherals in the system.
7.1 Definition of the problem.
The experimental E.D.M. Machine is built using several separate modules or peripherals. All of these are custom built. All modules should be controlled by the microcomputer in one or another way. The modules can be seen as front-ends towards the actual sparkerosion process.
FYBBUS INTERF4CE
Fig 14. Logical information flow in Fybbus.'
Several functions such as power amplification, digital to analog conversions and vice versa, as well as specialized control are built into the peripheral modules. The modules can, from the micro-computers point of view, be seen as binary i/o gates. This
Computer~Process Interface page 28
fact imp~ies the possibility of a bus structure throughout the
system.
7.2 The status QUo.
The available computer system consisted of two Intel iSBC 80/20-4 industrial or OEM single board computers, and a iSBC 556 optically isolated i/o board.
First of all we must explain in shorthand the usage of the two microcomputers: One of the computers is fully occupied controlling the high speed Hydraulic Servo motor, using data retrieved from some of the measurement modules. This micro is called the Servo - micro processor. The other microcomputer ~s
intended to do an overall system supervising as well as to run an optimization program. This micro is called the Main micro processor. The servo computer used its own i/o to do all its work, the main computer was the only master in the available busstructure, and accessed its peripherals through the optically isolated i/o board. Because the main micro had to pass parameters to the servo micro, simple, not well evaluated hardware was used, emploing two 8255 parallel i/o ports. The original idea as background of this solution was that the main micro had to pass occasionally a few bytes of data to the servo micro computer, that is once per 0.1 microsecond. This could easily be implemented without the use of the relativilly expensive memory board. This way of communicating allowed only a few types of commands to be exchanged.
As the necessaty arrived to pass more commands and data, i t was decided to implement a so called common memory. This common memory should be equally accessible (exept for priority) to both busmasters (servo and main processor). A preliminary design for such a memory was made, but i t was decided to buy an off the shelf printed circuit assembly, to reduce development time and to save costs. The memory board chosen to solve the problem was the Intel iSBC 108A combination memory and i/o expansion board. The use of
Computer-Process Interface page 29
this common memory and i/o board featured two important advantages:
1. Parameter passing I/O procedures from main to servo computer could be eliminated.
2. Communication protocols can be defined in a proper, unrestricted way.
The use of this mentioned optically isolated i/o board necesitated a two level peripheral address selection, because only 48 i/o lines were available to implement communication between computer ~nd process. The number of necesarry lines was 16 times 8 bits is 128 lines. This means, that, if both computers were to use a bus with two level selection, a mutual exclusion scheme would have to be implemented, to prevent that different masters could access the bus during an address to data setup sequence. Such a scheme would yield several disadvantages, such as synchronisation problems, reducing throughput, and possible priority violation. (Main micro is system master, but- servo micro has higher access priority to the bus, since it works harder.) As we foresaw these problems, we decided to extend the power of a
well defined multimaster bus structure throughout the
computer/E.D.M. system.
7.3 Bus definition.
The bus between system and computer must feature input, output, and address part. A high noise immunity should be built in, and the bus should be optically isolated from the micro-computer system for two reasons:
1. Disabling ground loops.
2. Isolate the computer from the noisy spare erosion process.
These functions were implemented in the following way: A separate 8 bit input, an 8 bit output and a 6 bit address bus as well as a two bit control bus should fit into a ribbon type 50 lead cable. The input part is called DATI-bus. The output is called DATa-bus, and the control and address part is called the CHIP bus. The six address lines yield 64 seperatebut adjacent addresses, wherein
Computer-Process Interface page 30
each address can support both input an output, which means that 64 eight bit wide input ports and 64 eight bit wide output ports are addressable. (Currently 12 output and 8 input addresses are used.) The control bus consists of two lines which" are both active low. These lines are called EDATI/ and EDATO/ (for Enable DATa In and Enable DATa Out) . The lines are directly comparable to the read and write lines, common in many computer systems. Only 6 bits are used for the add:resses for two reasons:
1. Cable width. The whole bus including DATI, DATa, CHIP and control should fit into a 50 lead cable with alternate ground lines for shield function. This leaves 25 effective lines in the cable.
2. 64 addresses sUffice, and reduce the high speed (high price) optical isolation package number, a significant cost factor in the printed circuit assembly.
The lines are spread over the flat cable as follows: All even lines are ground.
3
-
EDATI/ 27- DATa 3 5-
EDATO/ 29- DATa 2 7 - CHIP5 31- DATa 9-
CHIP4 33- DATa 0 11- CHIP3 35- DATI 7 13- CHIP2 37- DATI 6 15- CHIP1 39- DATI 5 17- CHIPO 41- DATI 4 19- DATa 7 43- DATI 3 21- DATa 6 45- DATI 2 23- DATa 5 47- DATI 1 25- DATa 4 49- DATI 0Line 1 is not connected.
The addre$s bus AO through AS are called CHIP at the system level. Al bus signals are Locmos HEF4000 (signetics) family compatible signals, with a Vcc of 15 Volts.
Computer-Rrocess Interface page 31
We shall Jail the microcomputersystem the bus master, since i t is the only device that can assert the address and control bus. To connect this bus to the microcomputer, an interface was designed, which is the subject of the rest of this paper. (chapter)
7.4 Functional characteristics.
The 15 vqlt logic level bus is seperated into output, input and
6
8
EDIIT.l/[:>
CHIP8
IJATAs
<J
DilTZ8
Fig 15. Address decoding for Fybbus.
address and control bus. The in- and output buses are directly derived from the 8 bit low byte data bus of Multibus. The addressbus is logically the same as the 6 low order bits of the 20 address lines of the computer system definition. The control lines however are derived from memory read and write lines as well as an addressbase selection, EDATA/ (low active). The optically
Computer-Process Interface page 32
isolated ~us, called Fybbus can control addresses in range from OH to 3FH. the offset or base added to these addresses yields the logical address range, as seen by the two micro microcomputers. The base 9ffset is OFFCOH, which means, that the Fybbus logical
addresses~ from the computers point of view range from OFFCOH to
OFFFFH.
7.5 Universality
To make a design effort that would be fully flexible in its base selection would imply the need of unnecessary additional logic, since i t is very likely that this design will be used only once. However, the printed wire assembly as designed will respond correctly to a busmaster driving 20 adress lines, instead of 16 as the 80/20 boards do. The fixed address range of OFFCOH to OFFFFH has been chosen such, that no conflict would arise, if the printed wire assembly were to be used with a 8086 type bus master. (this type of CPU uses the addresses from OFFFFOH to OFFFFFH for initialisation vectors.) Since only a 8 bit wide data path is defined in fybbus, no swap registers to allow for both byte and 16 bit word transfers are implemented.
7.6 Additional features.
Since a new P.C.A. design had to be made, several additional new functions could be built into the remaining board space.
First of all a 8259A Programmable Interrupt Controller was added. This Controller cann substantially simplify the programing of routines servicing asynchronous signals. The interrupt controller will generate a multibus type INT/, and must be polled upon interrupt reception to determine the interrupt source.
an i8253 timer/event counter is implemented, to reduce counting and timing logic in the Machine control This counter can ammong other things, support a time the EDM system, and can generate interrupts on 'clock base for
Secondly auxilary interface.
Computer-frocess Interface
ticks' .
page 33
Thirdly an i8231A Arithmetic Processing Unit is used to upgrade the computational performance of the computer part of the system. Since thi$ unit resides under the multi master bus, it can be accessed ~nd used by both busmasters. The APU supports fixed and floating point instructions, on words up to 32 bits, as well as transcede*tal and trigoniometric functions.
To implem¢nt several control lines, a second, auxilary, bus is defined, the extra bus. This bus supports four incoming and four outgoing timing/control signals, as well as power supply ( 5 and 15 volts) and ground lines for auxilary logic.
Also, this bus will supply printed circuit assemblYr the computer system.
the power to the 'out'-side of the i.e. at the side to be isolated from
7.7 Principals of operation.
Readers of this part are assumed to be familiar with the busstructure of computer systems, in particular Intels Multibus. All logic used on the inside of the PCA consists of either Low power Schottky TTL (74LS... series), Schottky logic where neccesarry (mainly address decoding to meet Multibus and peripheral timing specs) or Intel interface and peripheral chips. The 'outside' uses HEF 4000 series LOCMOS The border between inside and outside consists of 16 2630 Hewlett and Packard dual Optical Isolators.
Computer-Process Interface
7.7.1 Address decoding.
page 34
All Multibus address lines ar inverted regarding the CPU's outputs. This means that the bus signals must be logically 0 to be high (true) at system logic level.
The Base address select, low active is contructed using a 74LS27 triple 3 input positive NOR gate and a 74S30 8-input positive NAND gate.
BASE/ = A13.A12.A11 .A10.AF/.AE/.AD/.AC/.AB/.AA/.A9/.A8/.A/7 This
11/ ; 12-U /I 10 ~ F '-.
I
U\ 6'"
l>-
f q: c-'"\..
q
•
..
Q A '::I e;tS
..
---=.
'"
1
..
-
J 8A3EiElEcr
A6Fig 16. Base selection and Data enable.
base signal is used to select the board as current active slave. BASE/ = OiF80H. From this BASE/ select both Fybbus enable C.q.
control lines are derived. BASE/.A6/ = EDATA/
EDATA/
=
Fybbus select.The control lines for Fybbus EDATO/ and EDATI/ are functions of memory write and read. EDATO/= EDATA/.MWTC/
EDATI/=EDATA/.MRDC/
Computer-Process Interface page 35
inhibit signals (RAM inh and ROM inh) must be generated. The inhibit signals are equal to the BASEl signal, but must be buffered with open collector gates to comply with the Multibus definition. To prevent bus overload on the low 8 bits of the
5V
BASEl
fI'lHJ./
.I
IYH 2/Fig 17. Inhibbit and acknowledge signals.
addresses, these lines are buffered with an 8287 bus transceiver, always used in one direction only. The chip select lines for the peripheral controllers and slave processor are generated by means of a 745138 3 to 8 line decoder. The CSI will arrive latest at 22+39 = 61 ns after address stable. Earliest CSI will arrive 5+6.5 ns after address valid.
Transfer acknowledge signals are generated separately for either Fybbus or peripheral chips (8259A, 8253, 8231A). However the output control of the tri-stated XACKI (transfer acknowledge) , is controlled by: BASEl. (MWTCI+MRDC/). Transfer acknowledge for Fybbus transfers ~s generated equally for read or write. The falling edge of the EDATA/ signal is delayed by means of a 74LS164 8-bit parallel output serial shift register, which can delay the edge by a maximum of eigth clocks. The input clock signal is provided through a 74LS93 4 bit binary counter, which is wired as a by 2, by 4, by 8, and by 16 divider. This arrangement and the constant bus clock of approximately 100 ns allows signal delays from 100 ns up to 12.8 lls. This delay will cover all possible propagation delay in the address and command lines, measured from the bus to the addressed IIO gate, as will be shown later. The
Computer~Process Interface c ~....- o page 36
)('.a.II~....-4X~~E:=
X;tICIUfilllERIITION FOA F YSSUJ rNrrltFIfCE.Fig 18. Transfer acknowledge.
XACK/ signal for the 8259A and the 8253 are made in a similar way,
but they use sepperate clock and shift registers, since their
response to transfer commands will be faster. The third XACK/
82'11f:..J=~~
R.EAD
-Q
Fig 19. i8231A Ready signal to Xack conversion.
generation is derived from the 8231A ready or pause signal. The
8231A will pull its ready line low to force the requesting
busmaster into wait states, which will ensure command to be stable
during the incomplete transfer. The APU will pull its ready line
low for each transfer, which means that the trailing edge of the
active low ready signal can be used to generate the required XACK/
at the end of the transfer in progress. The logic to create the
XACK/ pulse is designed such, that there will be a low going pulse
out of the triple NOR from the positive going trailing edge of
Computer-Process Interface
7. 7 .2 The' Interrupt and Interrupt Acknowledge.
page 37
The printed circuit assembly is a slave board, which implies that the incorporated PIC 8259A should be able to function as a slave interrupt controller using the slave mode. The slave interrupt controller will drive one of the multibus interrupt lines upon reception of a valid unmasked interrupt. The Master interrupt controller (normally an interrupt controller on a CPU board)) then will, if its asociated input is not masked by either hard- or software, drive the CPU's interrupt line. Upon reception of the INTA/ signal from the CPU the Master PIC will decide that a slave PIC is requesting service. The master interrupt controller either will drive the data bus with a CALL instruction (for MCS 80/85) or will not do a transfer in the iAPX-86 mode. After this setup, the
AAI_... AlJl_... 1181_... 8DArAI 818
i
8259//
8 DIITAFig 20. Data bus enable for slave interrupt controller.
Master PIC has derived the slaves Cascade address and will drive this onto the address bus (address lines 8 to A are used for this purpose.) from which the slave PIC will respond as soon as the INTA/ line goes low for the second ( or third time). The slave PIC must have been programmed in the Buffered Slave mode, which will instruct i t to drive its EN/ line true, to both enable the
Computer-Process Interface page 38
slave board's bus tranceiver into the towards Multibus driving direction, and to start the generation of the XACK/ signal. In this way the slave board's interrupt logic will fully comply with the Multibus specs. The older type CPU boards however, like the 80/20 board will not drive the interrupt cascade lines (cas lines) lines, nor the INTA/ line, which means, that both the SP/EN line and the INTA/ line must be tied to Vee, and the software must poll the slave' PIC.
7.8 Timing Analysis
The correct functioning of the printed circuit board interface assembly is mainly a function of timing parameters. The interface should respond correctly to Multibus commands/requests and should request for wait states (delayed XACK/) if the rest of the system (peripheral chips or Fybbus) require these. The timing specs of Multibus are listed in the Multibus definition Intel" publication nr 9800683 or in application note AP 28A. The timing requirements of the Fybbus interface can be calculated using the information retrieved from various data books concerning LOCMOS, TTL and Opto-electronics. The Timing specs of the MSI and SSI used is listed in table 1. (Appendix)
The Fybbus interface control and address logic will guarantee that EDATI/ or EDATO/ wil not be valid before addresses are stable. This is accomplished by the fact that the base selection EDATA/ is derived by means of two additional gates (one 74LSOO in address line 6 and one 74LS32 to add together the lines BASE/ and A6/.) This EDATA/ line in its turn is then gated with the WR/ an RD/
lines to produces the control lines EDATO/ and EDATI/
respectivily. The prop delay of the gates will ensured that these control signals will not arrive before stable address. In addition to this builtin delay, the multibus specs guarantee that the MRDC/ and MWTC commands are not active before 50 ns after valid address. The Intel 8253 requires that RD/ or WR/ are not driven before 30 ns after address and chip select are stable, and the RD/ and WR/ signals are removed at least 30 ns before address
Computer-Process Interface page 39
I
and C5/ ~o inactive. This is accomplished by the usage of the 74530 and the 745138 in the address decoding. Violation of the timing specs could theoretically occur when both the 74L527 and 745138 have maximum delay and the 74L508 in the RD/ and WR/ lines have minimum delay. RD/ and WR/ inactive too late will not occur since eveh the maximum delay in the RD/ and WR/ lines will leave at least 30 ns before the address on the bus deactivates. (5ee 8253-5 specs.) The trailing edge will be off quick enough because of the less gated RD/ and WR/ signals going inactive 50 ns before address (at MULTIBU5), so the chip select will not go inactive too soon. The same goes for the 8259A and 8231A, although these devices are less critical in this respect.
The timing nomenclature For Read command:
tAR Address to Read setup
ROOR.
ROt
OATA/
XACK/
/lEAD r/M.lIVG- FOA OI9TI 0,", i825919 OR /82S3
Fig 21. Read timing
tAE Address to Enable
tAX Address to Acknowledge
tRX Read command to Acknowledge tDX read Data valid to Acknowledge
tRNAN Address hold time after Read command tEA Enable inactive from Address inact. tANXN Address invalid to Acknowledge inactive tRNDN Data hold time after inactivation Read. For Write command:
Computer-Process Interface page 40 e",,/fAN c,/V £DArl'l/ I:-iNXN tEA VAJ.ID r----'rl---~----XACX/ /fDDA. """AI' DATA
Fig 22. Write timing
tAW tAE tDW
twx
tWNAN tANXN tWNDN tAWAddress setup to write command. Address to Enable
Data setup to Write command. Write command to Acknowledge. Address hold time
Address inactive to Acknowledge off. Data hold time
Address to Write command Setup For i8231A:
tRRYN Ready inactive from Read command. tWRYN Ready inactive from Write command. tRDRY Read Data valid to Ready.
tRNDN Read Data Hold time. tWNDN Write Data Hold time.
tRDX Ready rising to XACK/ active.
tANXN Address inactive to acknowledge inactive.
If inhibit signals are to be used to disable a RAM or ROM slave Board, (we use memory mapped I/O, which might pierce a hole into the logical address space of a memory slave) the acknowledge signal XACK/ should not become active before 1.5 microseconds after address stable.
Monitor and Loader ADD/lESS VALID 'WR/ AD.
---+-...
+--+-+---AD/ XACK C5/---~---_---Ir
;82.3111 /fEIID "'ND W/fZT£TJI'1IN6-Fig 23. Timing for 8231A
8 The mon~tor and loader software.
page 41
In every computer application a certain amount of basic software must be available before a system can be used (partially) on its own. Many microcomputer systems are provided with a so called monitor, a program which allows the memory and register contents to be examined and altered. The program also allows user programs to be executed, either real time or single stepped, and some times a complete debugger is available.
For our system a Intel 80/20 monitor was available which included most of these functions, although the program loading was restricted to the use of a teletype. The procedures for i/o were completely fixed.
The basic functions of this monitor were left intact, but a number o£ useful system functions were added. These functions include data format conversion (e.g. integer to binary) but more importantly, the software was made almost fully i/o independent.
Monitor and Loader page 42
I
The standard character handlers like CI and CO were redefined. This allows the user to write his own i/o drivers, and attach them to the software kernel of the monitor. In this way character streams may be redirected to other then the standard serial i/o
channel. This enables the loading of data and code information from other sources then a teletype or terminal. For instance the complete software (both user and monitor) could be controlled remotely ~y another computer. The flexible (that is through a RAM resident vector) defined character handlers allow various i/o drivers, such as interrupt driven. Also handshake, including checksum, between the microcomputer system and a (as mass storage device abused) host computer system can be implemented very easily.
All subroutines of any general use are also included in the monitor program. The built in functions of the monitor however require a substantial amount of read only memory, which could have caused problems in a single board system. However since the main application of the program still is the loader and debugger function, it was not necessary to let i t reside on the CPU board. The program could instead be moved to the iSBC108A extension board, leaving almost 8k bytes of read only memory available on the CPU board. This is a great advantage, since the CPU board resident memory can be accessed without arbitrition and therefore without wait states, which might slow down the application program. Also a more substantial saving in memory space is achieved, since the monitor kernel can be accessed from both master CPU boards which means that the great majority of the subroutines does not have to be duplicated in CPU board ROM. The CPU board resident memory is therefor almost fully available for application software, allowing i t to be executed at full speed.
Monitor and Loader
8.1 The miajor functions.
The mayor functions of the monitor are:
page 43
DISPLAY The displaying of memory memory is displayed in
column numbers and ASCII
contents. The contents of a formatted way, including character decoding. SUBSTITUTE GO INSERT eXCHANGE READ WRITE NEXT FILL MOVE
Alteration of memory contents, either single byte or sequentially. Controls to enable forward and backward pointer movement are included. Also memory address is showed after each 8 entries.
User program execution is started with this command. The starting address may be specified, as well as up to two breakpoints.
The insertion of hexadecimal information in bytes is
enabled in this way. The program provides automatic formatting.
Display and alteration of the (user) CPU registers.
Reading a hexadecimal file (or papertape) to load memory with data or program.
Storing memory contents in paper tape or external file.
Execution of one instruction (the one pointed to by the user program counter)
Initialising memory with a constant.
Monitor and Loader page 44
EDIT-LIS'l1
CONNECT
Entering texts in ASCII characters.
Communication with a host computer.
HEXADECIMAL Some hexadecimal calculation)
arithmetic (e.g. address QUERY
ORIGIN
Represatation conversion (e.g. ASCII to binary)
Code transport within memory.
A user manual for a subset of this system program is available in appendix B. The monitor program described in that paper is currently in use as system monitor for the EWMC computer, a in house designed single board computer.
Fybbus software interface
9 Software for the fybbus interface.
page 45
In this paragraph we will compare the software necessary to control the data i/o through the new and the old computer system to process interface. The previous interface was implemented using an Intel iSBC556 optically isolated i/o board. Apart from the optical isolation this board used two 8255 programmable peripherial interface integrated circuits. The directly available number of i/o lines was insufficient to address all the interfaces used in the spark erosion control system. To be able to access all the interfaces like measurement and control units a two stage addressing technique was used, which substantially slowed the system down because of the overhead involved in fetching or storing a byte of data. The new interface is different in two respects. In the first place 64 input and 64 output addresses are available. (All are byte wide, i.e. there are 1024 i/o lines available.) Secondly the i/o addresses are memory "mapped which allows memory reference instructions to be used to address i/o gates. Among these instructions are those which access 16 bit values in one indivisible (or not interruptable) operation.
To input a byte of measurement or control data the old system used the following program.
States
7 ~I A,ADR A:= LATCH ADDRESS
10 OUT CHIP APPLY TO ADDRESS BUS
7 MVI A,CHIOO ENABLE ADDRESS SELECTOR FOR
INPUT
10 OUT CHIPC WRITE TO CONTROL PORT
7 IN DATI GET THE DATUM
4 MOV C,A SAVE IT
7 MVI A,CHI01 DISABLE ADDRESS SELECTOR
10 OUT CHIPC APPLY CONTROL BYTE
4 MOV A,C RESTORE DATUM FOR
Fybbus software interface page 46
66
The timing in states assumes no wait states per cycle.
This has been reduced to a mere:
13 LDA DATUM GET THE DATA FROM ITS
MEMORY RESIDENT LOCATION.
Even if we allow for wait states ln the new situation the substantial speed improvement can easily be recognized. This is even more so if we use the 8080 memory addressing techniques to read sequential data. (This is used to gather data from several ports at once)
7 MOV A,M ; GET DATA FROM (H,L)
which executes in a minimum of only seven processor states. A two byte value can be read or written in one instruction taking 8 states per byte. More important feature is, that· this 16 bit parameter data is accessed without possible interruption.
servo EROSION DATA LATCH
ARC DATA LATCH
OPEN PULSE DATA LATCH
SHORT CIRCUIT PULSE COUNT LATCH ANORMAL PULSE COUNT
IGNITION DELAY.
and control values used by the
output addresses are in use and 8 input are to be found in the memory address space as:
TI AN TO OUTPUT PORTS
FOR GENERATOR PROGRAMMING (BCD) SPECIALLY CODED CURRENT
CONTROL WORD.
ANALYZER PROGRAMMING PORT EFFICIENCY DIAL ADDRESS SERVO DAC ADDRESS
At this moment 11 addresses. These FFCO TI: DS 2 FFC2 TO: DS 2 FFC4 STR: DS 2 FFC6 TI20: DS 2 FFC8 PHIE: DS 1 FFC9 SERVO:DS 1 At the input side: FFCO EROSIE: DS 1 FFC1 BOOG: DS 1 FFC2 OPEN: OS 1 FFC3 KORT: DS 1 FFC4 ANOR:MA: DS 1 FFC5 TO: OS 2 As we see the data
Fybbus software interface page 47
not so in the old interface, where the servo memory used its own (local) i/o addresses.
The programmable peripheral chips like the 8253, the 8259A and the 8231A are also located in this address space.
DS 1 DS 2 FFB8 APU: DS 1 OS 1 DS 2 FFBO P1]:T: DS OS OS OS FFB4 PIC: DS 1 1 1 1 1
PROGRAMMABLE INTERVAL TIMER COUNTER 0, 1
AND 2
CONTROL AND MODE ADDRESS PROGRAMMABLE INTERRUPT CONTROLLER
MODE AND COMMAND ADDRESS INTERRUPT MASK ADDRESS TWO DUMMYS
DATA ADDRESS OF ARITHMETIC UNIT
COMMAND AND CONTROL DUMMYS
9.1 Programming the process interfaces.
The pulse analyzer uses a 20 MHz time base for all its data acquisition. This value is used to classify the pulses and to 'count' the ignition delay value. To classify, the analyzer must known the length of the actual pulses. Therefore the control program must write the Ti value, multiplied by twenty, to the analyzer. The programmer must also be aware that the Td value as available is a value measured in 0.05 microsecond increments, and should be normalised at some stage in the program. ( detering the normalizing to a point later in the program may reduce bit loss and therefore increase the accuracy in the low count regions.)
The pulse generator is made with a binary coded decimal interface, and requires the Ti and To values to be converted from the internal binary format to BCD. In the old interface this was accomplished in hardware. This caused many troubles due to
