Implementation and evaluation of a combined test-error correction procedure for memories with defects

correction procedure for memories with defects

Citation for published version (APA):

Vinck, A. J., Pineda de Gyvez, J., & Post, K. A. (1987). Implementation and evaluation of a combined test-error correction procedure for memories with defects. (EUT report. E, Fac. of Electrical Engineering; Vol. 87-E-169). Technische Universiteit Eindhoven.

Document status and date: Published: 01/01/1987

Document Version:

Publisher’s PDF, also known as Version of Record (includes final page, issue and volume numbers)

Please check the document version of this publication:

• A submitted manuscript is the version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website.

• The final author version and the galley proof are versions of the publication after peer review.

• The final published version features the final layout of the paper including the volume, issue and page numbers.

Link to publication

General rights

Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. • Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain

• You may freely distribute the URL identifying the publication in the public portal.

If the publication is distributed under the terms of Article 25fa of the Dutch Copyright Act, indicated by the “Taverne” license above, please follow below link for the End User Agreement:

www.tue.nl/taverne Take down policy

If you believe that this document breaches copyright please contact us at: openaccess@tue.nl

providing details and we will investigate your claim.

Evaluation of a Combined

Test-Error Correction

Procedure for Memories

with Defects

by A.J. Vinck

J. Pineda de Gyvez K.A. Post

EUT Report 87 -E-169 ISBN 90-6144-169-2 ISSN 0167-9708 Fepruary 1987

Department of Electrical Engineering Eindhoven The Netherlands

IMPLEMENTATION AND EVALUATION OF A COMBINED

TEST-ERROR CORRECTION PROCEDURE FOR MEMORIES

WITH DEFECTS

by

A.J. Vinck

J. Pineda de Gyvez

K.A. Post

EUT Report 87-E-169

ISBN 90-6144-169-2

ISSN 0167-9708

Coden: TEUEDE

Eindhoven

February 1987

Department of Electrical Engineering and

Dr. K.A. Post,

Department of Mathematics and Computing Science of the

Eindhoven University of Technology,

P.O. Box 513,

5600 MB Eindhoven. The Netherlands

CIP-GEGEVEN5 KONINKLIJKE BIBLIOTHEEK, DEN HAAG

Vinck, A.J.

Implementation and evaluation of a combined test-error correction procedure for memories with defects / by A.J. Vinck, J. Pineda de Gyvez, K.A. Post. -Eindhoven: University of Technology. - Fig. - (Eindhoven University of Technology research reports / Department of Electrical Engineering, ISSN 0167-9708; 87-E-169)

ISBN 90-6144-169-2

5150664.2 UDC 681.327.66.08 NUGI 832

Introduction .•...•..••.•••••••...•....•.••••••••.•••••• 1 Notation. • • . . . . . . • • • • • • • • • • • • . . • • . • • • . . • • . • • • • • • • • • • • • • • • •. 2 Test procedures... 2 Mean time to f a i l u r e . . . 6 Extension to soft errors ..•••.•.•.••••...•.•..••.•..•• 9 Implementation ..•••••••••••....•.•.••••••••••••••••..••.... 11 Conclusion •••.•...•••••••••••...•••.••••••.••.•.••.••. 13 Appendix ••..•••.••••.••••••••.•.•••.•••••••••••.••••••••••• 14 Acknowledgement ••..•••••••••••••.•....••••.••••••••.••••••• 16 References •••••...•••.••••.••••••••••••••.•..••.••.•••••. 16 Figures ••••.•••..•.•.••••••••.•••••••...••.••.••..•••••••.• 17

INTRODUCfION

ABSTRACT

We discuss the application of simple parity check coding together with a test procedure to improve the Mean Time To Failure for memory systems with hard errors (defects). The memory is said to

be

in failure if more errors are detected than can be corrected. The test procedure combines the idea of additive coding with simple parity checking. The complexity is proportional to the frequency of parity errors. We extend the test procedure to include soft errors as well. We do calculations on the influence of coding on the Mean Time To Failure.

Vinck, A.J. and J. Pineda de GDvez, K.A. Post

TRPIrMENTATION AND

EVALUAf

IONF

A

COMBINro-TEST-ERROR CORRECTION PROCEDURE FOR MEMORIES WITH DEFECTS.

Department of Electrical Engineering, Eindhoven University of Technology (The Netherlands), 1987.

EUT Report 87-E-169

One of the important parts of a computing system is the memory. There is a tendency in producing large memory systems on one chip. This is possible due to improvements in process technology and clever circuit

design that leads to high packing densities. Obviously, packing density has its limits. A high packing density may cause defects in memory cells. We distinguish between Q-defects and I-defects, i.e. between defective cells

that always produce a "0" or a "1", respectively, when being read.

We analyze a computing system that reads each unit of time a word from

a specific memory location. The memory location is selected at random.

Write locations are again selected at random.

In the next sections we discuss a test method. in combination with an error detecting mechanism.

Then we discuss the Mean Time To Failure of the method. for the uncoded and coded situation.

NOTATION

N size of the memory

L

address or number of memory location

MEM(L)

content of memory location

L.

x word stored into the memory. y component wise complement of x. x·.y· words read from memory.

p probability tbat a memory cell is defective at time i. given that it was in order at time instant i-I.

q I-p

k length of a memory word.

a k+l

m message of k-bits. d distance of a code.

P

parity digit of a word.

P(i/i-l.i-2 •... 1) the probability tbat a selected word is in error given that previously the selected words were in order.

P the probability that there are no errors in a word of length k.

o

P.

the probability that a word is correct at time i.

1

MTTF Mean Time To Failure

TEST PROCEDURES

Before explaining the test procedures. we recall and extend the assumptions from the introduction.

- Each unit of time a specific word is selected from the memory with probability 1/N. where N is the number of words in the memory.

- Errors only occur as defects. The probability that a memory cell

at time instant i is defective given that it was in order at time (i-I) is p.

- A word consists out of k cells.

The test procedures we analyze assume that a word is possibly tested for errors only when it is read. Hence, memory words that are never used are consequently never tested. The test procedures are as follows:

a) Test every word read from memory.

In this case, directly after reading a word x'=M£M(L) from the memory location L, the complement y' to x' is restored at location L, while the word x' is normally processed. Subsequently we read the word y' from the same location. If there are no defects, then the components of x' and y' are each other complement.

The word x' is restored in the memory to recreate the original situation. If some components of x' and y' are the same, defective positions within a word x' are detected. Consequently processing must stop.

Assume for example there is a stuck at 1 defect at the third location of a word of length 4. Then, if 0101 is stored it is read as 0111. The

inverse 1000 is stored and read as y'=1010. The third component is the same, and thus one defect is detected.

If we use an error correcting code [1] with distance d, we are able to correct up to d-l defects. For, the codewords are different at as least d positions.

So, processing stops after more than (d-l) defects occured. Disadvantage of the above method is that every test costs a write/read/write cycle. If defects occur in the coded situation there is an additional coding-decoding

b) Test only those words for which the parity fails.

We assume that the (k+I)-th digit of a word contains the parity of the whole word. The parity is 0 if the number of ones is even. Else it is 1.

The parity of a word fails if the defect values are such that the number of errors in the codeword is odd.Note that defects that agree with

the codeword components are not counted as errors.

In case the defect pattern is such that there is an even number of errors, then the parity of the word is correct. This error event is not detected and thus leads to processing errors.

In case there is only one defect leading to an error, its location can be found by writing the complementary word into the memory and reading it again from the same location. This defect can be corrected. However,

processing has to stop because subsequent errors might be undetectable or uncorrectable.

The testing procedure avoids time consuming write/read/write cycles, but could lead to undetected errors.

As an example, read 0111 from the memory. The parity fails and 1000 is restored. We read y'=1010 and thus the third location is stuck-at-1. The original word stored in the memory was 0101. Again, extension to higher distance codes is possible.

c) Test only when parity fails but restore a modified version of x. This procedure assumes some precoding for x.

A message m, of even length k, is encoded as x=(O,m,P) or by the

complementary word y=(l,m,P). Hence, the length is extended to k+2. We initially only use x to store the messages.

The test procedure operates as follows:

- read x' from memory; if the parity is ok, go on, else store the complement to x' into the memory. read y

- if there is only one defect, that causes the error then the parity of y' must be ok, because y' is the complement of x' and thus the defect must agree with the component of y'.

We say that y' matches the defect, and therefore call our code a "I-defect matching code".

As a consequence of the precoding x and y have the same meaning and we do not restore x into the memory.

If the same location is read from the memory, and no additional defects occur, the parity checks and normal operation proceeds. If however one additional defect occurs it is detected because the parity of y' fails and proceSSing stops. The memory is thus in a failure mode when two or more defects occur.

The advantage of this method is that we can tolerate one defect in a word. The disadvantage is that the processor has to distinguish between x' and y'. This costs an operat~on equivalent to the inversion of a word.

Whether a word is to be complemented depends on the first digit of a word. Furthermore, undetected errors may occur.

As an example suppose that (0,10,1) is stored in memory. If a defect occurs in the third position, we read x'=(O,ll,l) and the parity fails. Then we store y=(l,OO,O) and read y'=(l,OI,O) which gives the correct message 01, in this case equivalent to 10, without a parity failure.

one additional defect occurs the parity fails and two defects are detected. These cannot be corrected by the decoder.

MEAN TIME TO FAILURE

We assume that each unit of time a specific memory location is selected at random and tested for errors. The system is said to be in failure if a selected word is found to be in error. Thus. the

Mean

Time To Failure (MTTF) can be defined as

MTTF = 1 Pl+2PlP2/1+3PlP2/1P3/2.1+ ...•

= _{1+P1+P1P2/1+P1P2/1P3/2.1+····} (1)

where P is the probability that a selected word is in i/(i-1.i-2 •...• 1)

error given that previously the selected words were in order.

The probability that a memory cell at time i is in error given that it was in order at time (i-I). is p.

For finite memories of size N»l. it is difficult to give a general expression for the

MTTF.

We therefore give an upper and a lower bound. The upper bound consists of two terms. The first term is given by the mean

time before there is at least one memory word in error.

As all words are selected with probability lIN. it takes on the average N units of time before a specific word. that is assumed to be in error. is selected. Hence. as an upperbound

MTTF(N)

<

l(l-P N)+2P N(l_P N)+3P 2N(l_P N)+ ... +N

o 0 0 0 0

= -"':'-oN"" +N. 1

1-P (2)

where P is the probability that there are no errors in a word of length k.

o

Thus P =(I_p)k. Note that the first term of (2) can also serve as a lower

o

bound to the MTTF{N).

If we define Pi to be the probability that a word is correct at time i, then for a memory with infinitely many words

P. _{l/i-l, i- , ... ,} 2 _{I=Pi ,} and

(3)

This can be approximated according to Appendix AS as

(4)

In Fig. 5, we plotted the approximation for MTTF{N) with k=4 as 1/4Np, N=4, 64 and 1024, respectively, together with (4).

The curves cross for p=I/{I.25N).

-40

For a 64k-4 bit chip the crosspoint is found at p=40 2 . Hence, using (2) and (4) and p, we are able to give an estimate of the MTTF of large memory

systems.

In the same figure are simulation results for memories of size 4, 64 and 1024, respectively.

The question arises whether the application of coding can improve the MTTF. Words of k digits long are extended to k+2 digits to be able to apply our test strategy c). Furthermore we assume that we always test the word

read from memory, irrespective the value of the parity.

Clearly, in this case a word read from memory is in order if it has less

The probability that a specific word has less than 2 errors at time i is

(5)

If we use the same approach that lead to (2). then the MTTF(N) can be upper bounded by the mean time before there is at least one word in the memory having 2 or more errors plus the mean time before we hit a specific word that is in error. thus

(6)

where Pi is given in (5).We can also substitute (5) in (3) to give MTTF(~).

As mentioned before. the MTTF(N) is also lower bounded by the Mean Time before there is at least one word. somewhere in the memory. in error. In the Appendix we derive lower bounds for MTTF(N) and MTTF(~). The result is that ~ MTTF(N)

>

!

~

i=O

I

II

>

"2a(a+1) '" _1:..:.:.:25:::.

kvffp

1 (A5)

This result is rather surprising. For a 1 defect matching code the gain in the MTTF(N) for small p is proportional to

vN.

Hence. the larger the

memory, the larger the gain.

For a memory with infinitely many words

3r-6

>

.;~) (A6)

2

h MTIF( } (p)-

3'

f

Hence, in the coded situation t e w increases as instead 0

1

-2'

(p) for the uncoded situation. The above results are summarized in Fig. 6, where we plotted simulation results together with A5 and A6. For large values of N, the initial behaviour of the real MTTF is according to A6. For very small values of p, the behaViour is according to A5.

In testprocedure c} we assumed that a word is tested iff the parity fails. Therefore, the expected mean time to failure in this situation is larger than in the situation where we always test for failures.

EXTENSION TO SOFT ERRORS

In order to be able to handle soft errors, we use an error-correcting code wi th

- division of the codewords into two complementary sets, each with minimum distance 4,

- all codewords have even weight.

We briefly discuss the consequences of the above requirements. Division of all codewords into two complementary sets of codewords with even weight enables us to use test strategy

c).

Thus we have a very low complexity error detecting mechanism.

Only in case there are errors, the decoder has to do additional work. As an example we use the following code with 2 equivalent sets of 4 codewords of length 6. 111111 010111 101000 101101 010010 111010 000101

x

y

The code can handle at least the following situations.

- One error caused by a defect in x is detected and the defect is matched by storing y' instead of x'.

- One soft error in x' is detected, because y' and x' are complementary if we use test procedure

c).

Correction is possible by storing the codeword at minimum distance from

, x .

- One additional defect in y can be detected and can be corrected by the decoder, using the distance property. After this event happened, the decoder has to check every word, for two additional defects may cause undetected errors, if we use procedure c).

- One soft error in y' is detected and corrected in the same way as before for x'.

The problem with using error correcting codes in general is that we normally have to use a complex error trapping circuit.

This may lead to an unacceptable delay. It can be avoided by using the even weight property of all codewords.

IMPLEMENTATION

We give a possible implementation of the test strategy. It is meant to give an insight of the hardware implications needed to have the scheme working in practice.

Fig. 1 shows the block diagram and Fig. 2 shows the hardware logiC for one bit. In order to have the complete correcting scheme working there must be as many implementations as bits per word. In the logic for the sign bit and

the parity bit buffers 17 and 18 can be omitted because it is not necessary to drive these bits out. Buffers 17 and 18 invert the bit in case it was complemented in memory. This function can also be acomplished

externally. Thus. these buffers are really optional to the hardware.

As the hardware is the same for every bit. the following explanation considers just one bit. For a correct operation the next conditions have to be met. The READ signal must remain high during the complete correcting phase. The signals READ-CONTROLLER. WRlTE-<X>NTROLLER and PARITY have to be initially low. The READ and the WRlTE-<X>NTROLLER signals are XORed through XOR 14. This allows the WRlTE-<X>NTROLLER signal to determine when to write or when to read again during the correcting phase.

Since initially READ-CONTROLLER is low, transistor Tl is on and the

information passes to the latch formed by inverters 11 and 12. At the same time the parity is calculated and checked against the parity bit of the word. If the calculated parity coincides with the parity bit then the

signal PARITY is high meaning that no errors are detected. Consequently transistor TS is turned on and the bit just read is driven to the output buffers 17 and 18. If the calculated parity differs from the one read then

the signal PARITY goes low and triggers the controller shown in Fig. 3. This controller generates Signals WRITE-coNTROLLER, READ-CONTROLLER and their complements WRITE-coNTROlllR' and READ-CONTROLLER'. All these signals depend on a clock for which the period equals the writing and reading cycle of the memory. Signal WRITE-ooNTROlllR is fired first to set the output of XOR 14 low. This causes transistors T3 be off and T4 to be on. These

transistors together with inverters 11 and 12 latch the incoming

information. At the same time pass transistor T2 is turned on in order to write the complemented bit in memory. Once the word is stored the

READ-CONTROLLER signal is fired to read the word just being written. While READ-CONTROLLER goes high WRITE-CONTROLLER goes low to avoid conflicts in writing or reading. The same applies for their complements. The function of signal READ-OONTROLLER' is to turn transistor 19 off to block any

information through that path, and the function of signal READ-OONTROLLER is to turn transistor T7 on to unblock its path to the output buffers 17 and 18.

XOR 13 "xors" the bit just read from memory with the one previously latched. If the output of this XOR is low then it means that this

particular bit is in error. Consequently only the complemented value,

selected through transistor 15, goes to the output buffer. On the contrary, if the output of the XOR is high then transistor T6 is turned on and the

original value is selected. If the word stored in memory is complemented. then by means of the sign bit the inverter tristate buffer 17 complements the bit again to obtain the correct output. Otherwise tristate buffer 18 is activated.

For each bit. the output of XOR 13 could also be used to check if two or more errors were detected. in which case a SYSTEM-FAIL signal could be

fired to acknowledge this fact.

Fig. 4 shows the simulation results for a stuck-at-o defect using a Switch Level Simulator [1]. The bits being read from memory are represented by M1. H2. M3. M4. MS. and MP. We assumed a six bit wide word. four bits for information. one bit for sign and one for parity. The output of the correcting scheme is represented by Otrn. OUT2. OUT3. 0UT4.

ours.

and OUTP. The information stored back into memory is represented by INM1. INM2. INM3.

INM4. INMS. and INMP. and finally the W2 and R2 signals are the WRlTE-cDNTROlLER and READ-CX>NTROlLER signals respectively.

CONCLUSION

We give a very simple implementation of a combined test-error correction procedure for memories with defects. The complexity is

proportional to the fraction of defects. We estimate the MTTF for the above test method. and compare the results with the uncoded situation. We also give simulation results. The improvement in the MTTF for a 1 defect matching test strategy is proportional to

vN

where N is the size of the memory in terms of the number of words. A hardware implementation is given at a gate level together with time delay simulation for a specific example.

APPENDIX

Let p,q,a and N be fixed real positive numbers, p+q=l. We define

and intend to find lower bounds for the expressions

00 00

L ~ and L i=O 1 h=O

The following lemma turns out to be useful:

-s 1 2

LEMMA. LET f(s): = en(a+l-ae )-as~(a+l)s (s~O)

Then f is an increasing function of s. -s ae Proof. f'(s) = -a+a(a+l)s = a+l-ae-s = a(a+l) {e-s-l+s(a+l-ae-s)} a+l-ae s

The first factor is positive. So we define

-s - 8

g(s): = e -l+s(a+l-ae ) Clearly g(O)=O and

-s - s - s g'(s)=-e +a+l-ae +ase

=(a+l)(l-e-s)+ase-s)O (s)O) . Therefore g(s)=g(O)+Js g'(u)du>O .

o

So f'(s»O and f(s) is increasing. Because f(O)=O we have the corollary

-s 1 2

en(a+l-ae »as~(a+l)s (s)O).

(Al)

[]

In order to find lower bounds for powers and products of Pi we define p:=-2nq (hence x>O) and evaluate lower bounds for

en

Pi (cf Al and A2):

2n P.=ai2n q +2n (a+1-aqi) =

1

-ix =-aix + 2n (a+l-ae )

>

. 1 ( 1) 2 2 1 ( ) 2 2

>

-alx + aix ~ a+ i x = ~ a+1 i x

pAs a consequence. we obtain

and

=

exp{ 1; a(a+I)12n ql2 h(h+l)(2h+I)}

>

so that finally and

..

..

!

~>

I

exp{

~

Na(a+1)12n ql2t2}dt = i=O 1 t=O

J

II ---!;1 _ _ - 2a(a+l) v'N12n ql

..

II

exp{-

~a(a+1)12nqI2t3}dt >

t -2 00

>

I

exp {

~

a(a+l)12n ql2t3}dt

-!

= t=O (A3)

(M)

(AS)

(A6)

For reasons of completeness we give upper and lower bounds for the series

CD h S(q,a): = ~

rr

h=O i=O ai q CD

=

~ h=O

~(h+l)

q -x

Again, we use the substitution q=e so that

ax Seq ,a)= exp(S)

CD

~ exp{~(h~)2}

.

h=O Hence

CD

exp(~)

II

e

-ke

2 dt<S(q,a)<exp(S) ax

so that, finally,

1 1

-a/8

ITi

1

12

1 -a/8

Ifi

1

2

1

q (v'~ en q 2)< S(q,a) <q (~en ql ~).

ACKNOWLEDGEMENT

The authors are indebted to Ir. J.J.A.M.Brands for his suggestions to analyse the probability functions effectively.

REFERENCES

[1] Clark, C.C. and J. Bibb Cain

troROR-CORRECTION CODING FOR DIGITAL COMMUNICATIONS.

New York: Plenum, 1981. Applications of communications theory.

(A7)

(AS)

[2] Genderen, A.J. van and A.C. de Graaf

SLS: A Switch-level Timing Simulator. In: The Integrated Circuit Design Book: Papers on VLSI design methodology from the ICD-NELSIS Project. Ed. by P. Dewilde.

~~-

_~~

_.(/'

PARITY PARITY PA~ITY f

-CDr1PARATOR "- _GENERATOR ~IORD LATCH

II'-'" .7 ""

7-INCOR~ECT PARITY --" WORD ( BIT )

I CORRECTION P AC KNOHL EDG E CORRECTION

CORRECT PARITY

SYSTEt1 FAIL

~7 ,lfCKNOWLEDf,E

7-

_II

I

OUTPUT STI\f,E

I

V

~rlte~ontrollar

15

T5

6

17

~rlte~ontroller' nd2.1.u n1 nv

....

'"

n2 jJarlty n1 IlV reaCl~ontroller' nd2.1.u read n2 read~ontroller clock' Ild2.1.u n2

SLS version: 2.0 SIMULATION RESULTS time _{1M M M M M M} 0 0 0 0 0 0 I I I I I I W R in le-09sec 1 I 2 3 4 S P U U U U U U N N N N N N 2 2 1 T T T T T T M M M M S p 1 I 2 3 4 5 6 I 2 3 4 5 6 10 0.00 0 0 0 0 I X X X X X X X X X X X X 0 0 30.00 10 0 0 0 0 I X X X X X X X X X X X X I 0 30.09 10 0 0 0 0 I X X X X X X I I I I I 0 I 0 45.00 1 I 0 I I I 0 X X X X X X I I I I I 0 I 0 50.00 1 I 0 I I I 0 X X X X X X I I I I I 0 0 I SO.63 I I 0 I I I 0 I I I I I I I I I I I 0 0 I S7.70 1 I 0 I I I 0 X I X X X X I I I I I 0 0 I S7.82 1 I 0 I I I 0 0 I 0 0 0 0 I I I I I 0 0 I 70.00

/1

0 I I I 0 0 I 0 0 0 0 I I I I 1 0 0 0 network: scheme nodes: 129

,

CODED .22

- - , PVN

100~----~~~~~--~~~---~---

__

~

1

u. >-::;:

,

10~---+---r~~~~---1 - P

Fig. 5. MTTF for strategy c). Simulation results together with bounds A5 and A6, for N=4, 64 and 1024.

,

...

iUNCOOEO

,

IOOr---~~~~---_+---~ ~ _4.4.P

"

,

, 10 SIMULAT ION ~G4 .DOOI .00 I .01 - p

Fig. 6. MTTF for uncoded memories using test strategy a) or b). Simulation; results. together with bounds 2 and 4,. for

N=4, 64 and 1024.

MII.l,IMETER-WAVE ANTENNA MEASUREMENTS WITH THE HP8510 NETWORK ANALYZER. EUT Report 85-E-149. 19R5. ISBN 90-6144-149-8

(150) Meer, A.C.P. van

EXAMENRESULTATEN IN CONTEXT MBA.

EUT Report 85-E-150. 1985. ISBN 90-6144-150-1

(151) Ramakrishnan, S. and W.M.C. van den Heuvel

SHORT CIRCUIT CURRENT INTERRUPTION I~W-VOLTAGE FUSE WITH ABLATING WALLS. EUT Report 65-E-151. 1985. ISBN 90-6144-151-X

(152) Stefanov, B. and L. Zarkova, A. Veefkind

DEVIATION FROM LOCAL THERMODYNAMIC EQUILIBRIUM IN A CESIUM-SEEDED ARGON PLASMA. EUT Report 85-E-152. 1985. ISBN 90-6144-152-8

(153) Hof, P.H.J. Van den and P.H.H. Janssen

SOME ASYMPTOTIC PROPERTIES OF M~IABLE MODELS IDENTIFIED BY EQUATION ERROR TECHNIQUES. EUT Report 85-E-153. 1985. ISBN 90-6144-153-6

(154) Geerlings, J.A.T.

LIMIT CYCLES IN DIGITAL FILTERS: A b1blioqraphy 1975-1984. EUT Report 85-E-154. 1985. ISBN 90-6144-154-4

(155) Groot, J.F.G. de

~NFLUENCE OF A HIGH-INDEX MICRO-LENS IN A LASER-TAPER COUPLING. EUT Report 85-E-155. 1985. ISBN 90-6144-155-2

(156) Amelsfort, A.M.J. van and Th. Scharten

A THEORETICAL STUDY OF THE ELECTROMAGNETIC FIELD IN A LIMB, EXCITED BY ARTIFICIAL SOURCES. EUT Report 86-E-156. 1986. ISBN 90-6144-156-0

(lS7) Ladder, A. and H.T. van Stiphout, J.T.J. van Eijndhoven ESCHER: Eindhoven SCHematic EditoR reference manual. EUT Report 86-E-157. 1986. ISBN 90-6144-157-9

(158) Arnbak, J.C.

DEVELOPMENT OF TRANSMISSION FACILITIES FOR ELECTRONIC MEDIA IN THE NETHERLANDS.

EUT Report 86-E-158. 1986. ISBN 90-6144-158-7

(159) Wang Jinqshan

HARMONIC AND RECTANGULAR PULSE REPRODUCTION THROUGH CURRENT TRANSFORMERS. EUT Report 86-E-159. 1986. ISBN 90-6144-159-5

(160) Wolzak, G.G. and A.M.F.J. van de Laar, E.F. Steennis (161)

PARTIAL DISCHARGES AND THE ELECTRICAL AGING OF XLPE CABLE INSULATION. EUT Report 86-E-160. 1986. ISBN 90-6144-160-9

TESTING: Theory and practice. The gains of fault modelling. EUT Report 86-E-161. 1986. ISBN 90-6144-161-7

(162) Meer, A.C.P. van

TMS32010 EVALUATION MODULE CONTROLLER. EUT Report 86-E-162. 1986. ISBN 90-6144-162-5

(163) Stok, L. and R. van den Born, G.L.J.M. Janssen

~HER LEVELS OF A SILICON"""'COMPILER. -EUT Report 86-E-163. 1986. ISBN 90-6144-163-3

(164) Enqe1shoven, R.J. van and J.F.M. Theeuwen

GENERATING LAYOUTS FOR RANDOM LOGIC: Cell generation schemes. EUT Report 86-£-164. 1986. ISBN 90-6144-164-1

(165) ~, P.E.R. and A.G.J. Slenter GAOL: A Gate Array Description Language. EUT Report 87-E-165. 1987. ISBN 90-6144-165-x

(166) Dielen, M. and J.F.M. Theeuwen

AN OPTIMAL CMOS STRUCTURE FOR THE DESIGN OF A CELL LIBRARY. EUT Report 87-E-166. 1987. ISBN 90-6144-166-8

(167) Oerlemans, C.A.M. and J.F.M. Theeuwen

ESKISS: A program for optimal state assignment. EUT Report 87-&-167. 1987. ISBN 90-6144-167-6

(168) Linnartz, J.P.M.G.

SPATIAL DISTRIBUTION OF TRAFFIC IN A CELLULAR MOBILE DATA NETWORK. EUT Report 87-E-168. 1987. ISBN 90-6144-168-4

(169) ~, A.J. and J. Pineda de Gyvez, X.A. Post

IMPLEMENTATION AND EVALUATION OF A COMBIN~EST-ERROR CORRECTION PROCEDURE FOR MEMORIES WITH DEFECTS. EUT Report 87-E-169. 1987. ISBN 90-6144-169-2