Low temperature thin films for next-generation microelectronics (invited)

Contents lists available atScienceDirect

Surface & Coatings Technology

Low temperature thin

films for next-generation microelectronics (invited)

Jurriaan Schmitz

MESA + Institute for Nanotechnology, University of Twente, P.O. Box 217, 7500 AE Enschede, The Netherlands

A R T I C L E I N F O

A B S T R A C T

In this article the current methodologies for low-temperature thinfilm deposition in microelectronics are re-viewed. The paper discusses the high temperature processes in microchip manufacturing and describes the thermal budgetfitting issue. The quest for low temperature deposition techniques is motivated in the perspective of contemporary trends in microchip technology such as 3D integration and the ending miniaturization. Reduced temperature depositions tend to deliver lower qualityfilms. This is illustrated with the relation between de-position temperature and thin dielectricfilm quality (dielectric strength). Existing and emerging technologies for low-temperature thinfilm deposition are reviewed with an emphasis on their applicability in microelectronic fabrication.

1. Introduction

Microchip (integrated-circuit) fabrication has developed very ra-pidly since its inception in the late 1950s[1–3]. Propelled by the Digital Revolution, the global semiconductor industry today reaches annual sales close to 400 billion USD. Given the typical 15% R&D expenditure level of semiconductor companies in combination with their overall size, is it only to be expected that developments go fast and will con-tinue to do so in the years to come.

While miniaturization long provided the heartbeat for innovation since the 1960s[4], the conventional lateral downsizing of components has today reached its limits [5]. Still, the demand for microchip in-novation is all but diminishing. This leads to a broad search for im-provements other than scaling [6]. The new paradigm for com-plementary metal-oxide-semiconductor (CMOS) and memory chips is called “equivalent scaling”: rather than physically miniaturizing the transistor, new materials and architectures are introduced to obtain the same performance benefits that lateral scaling used to bring[7]. This goes hand in hand with the renewed exploitation of the third dimen-sion. Both for memories and digital logic, three-dimensional circuitry is rapidly being developed and brought to the market[8–10].

These developments pose several challenges to the involved mate-rials scientists. First of all, the introduction of a new material into a microchip requires more than a successful thinfilm deposition. Good step coverage, in other words, conformal deposition is often a necessity, as high aspect ratio structures need to be coated; and thefilm needs to be patterned, requiring suitable etching processes. In addition, a thor-ough qualification must be carried out in order to safeguard the mi-crochip's functioning and reliability. Novel materials may introduce

new and unexpected reliability concerns that should be well understood and contained before mass production commences. In some cases, driven by commercial ambitions or changing legislation, market in-troductions appeared too early. For instance, the introduction of low-permittivity intermetal dielectrics and lead-free solder proved much more challenging than anticipated because of yield and reliability issues [11–13].

Another challenge can be described as“thermal budget fitting”. Each thin film has a typical deposition temperature and a certain thermal tolerance once deposited. The morefilms are stacked on top of each other, the more difficult it becomes to maintain the integrity of the already fabricated part, unless one gradually lowers the fabrication temperature. Indeed this is how microchips and many other planar-technology devices are made. Between the formation of the silicon substrate at 1414 °C and thefinal soldering of the chip onto a printed circuit board around 250 °C, the maximum temperature decreases as more and more layers are added to the substrate surface. This is illu-strated inFig. 1, and further discussed inSection 2.

The order of manufacturing steps, as well as the choice of materials, is often determined by thermal budgetfitting considerations. One ex-ample is the replacement of aluminum by polysilicon for MOS transistor gates around 1970, enabling high temperature source/drain annealing after the formation of the gate[14]. Only in the most advanced CMOS generations metal gates were reintroduced, at the expense of complex replacement-gate procedures. Another example is the formation of (high-temperature)field isolation before the creation of transistors and diodes[14].

Several trends in microchip fabrication, most prominently the 3D integration mentioned above, demand the deposition of high-quality

https://doi.org/10.1016/j.surfcoat.2017.11.013

Received 1 July 2017; Received in revised form 19 October 2017; Accepted 4 November 2017 E-mail address:j.schmitz@utwente.nl.

Available online 06 November 2017

0257-8972/ © 2017 The Author. Published by Elsevier B.V. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/BY-NC-ND/4.0/).

conformal thinfilms at reduced temperatures. This article reviews the technological options for lower-temperature depositions in microelec-tronics. Here, conventional (thermal) chemical vapor deposition is taken as the starting point, as this is the traditional technology of choice in this application.

Section 2of this article will further motivate the pursuit of low-temperature deposition techniques in the context of microfabrication. Section 3 treats six“cool” approaches for energy supply in order to control the formation of a good quality thinfilm.Section 4concludes this article.

2. Deposition temperature: high or low?

Integrated circuits make use of thinfilms with the highest quality in terms of chemical composition, uniformity, defect density and electrical performance. Besides these properties, a thinfilm must adhere well and should not affect its surrounding layers by process induced damage or mechanical stress. Relatively expensive fabrication processes such as chemical vapor deposition, atomic layer deposition (ALD),

deep-submicrometer lithography (including double patterning), plasma etching and chemical mechanical polishing are commonly applied in circuit fabrication. The economic value per unit mass of completed microchips exceeds that of pure gold and therefore, in comparison to most thin film applications, the priority is production yield before process cost.

High temperature process steps are common in integrated circuit manufacturing (cf.Fig. 1). These steps serve various purposes[15]: to activate impurities (dopants), repair lattice damage, deposit or densify materials; and to initiate reactions, mostly oxidation and silicidation. Impurity activation and lattice repair require temperatures of 900–1050 °C in silicon. Material depositions in integrated circuit pro-cesses typically take place at 600–850 °C (low-pressure chemical vapor deposition (CVD)), 300–400 °C (plasma-enhanced CVD) or close to room temperature (sputtering). A temperature between 700 and 1050 °C is used for oxidation of silicon. Silicidation is the reaction be-tween a metal and silicon, carried out to form the electrically con-ducting interface between the semiconductor and the interconnect at a typical temperature up to 700 °C.

Microchip fabrication comprises several hundred process steps di-vided into several phases (depicted inFig. 1). In every subsequent phase of this processing sequence, the maximum temperature goes down in order to maintain the chip's integrity. After the transistor fabrication phase, diffusion of impurities must be restricted. Once metallization is present on the chip, one should remain well below the metal melting temperature(s). After metallization and post-metal anneal, the hy-drogen passivation of the silicon surface should remain intact. And after thefinal phase of soldering, the solder melting temperature should not be exceeded. The stack of layers in a microchip therefore goes“from hot to cold”, as depicted inFig. 2. The use temperature range of integrated circuits spans from–40 °C to 150–175 °C. This also indicates a practical minimum temperature for the processing; there is no necessity to re-duce the chip manufacturing temperatures below the maximum use temperature of 150–175 °C from a functional point of view.

The above considerations already indicate that lower temperature processes are preferred for process integration. Thermal budgetfitting is easier if process steps are conducted at lower temperatures (and in shorter time spans). Tofit all process steps of an envisaged microchip within a given budget of thermal excursions becomes more difficult when more layers (hence more process steps) are involved. This is the case in V-NAND FLASH memories where 32 to 64 stories of memory Fig. 1. Temperature excursions over time during the manufacturing process of a

micro-chip and its functional life. First, wafers are manufactured at the silicon melting point; then followsfield isolation and transistor fabrication (a stage known as front-end-of-line, or FEOL) at ~ 1000 °C. Silicidation takes place at a typical temperature of 500–700 °C depending on the reacting metal. The formation of the interconnections (back-end-of-line, BEOL) occurs at ~ 400 °C maximum. The chip is then packaged and soldered, after which the functional life commences, with uncertain thermal excursions.

Fig. 2. Cross-section sketch of a silicon microchip, in-dicating the main production stages (as described in the caption ofFig. 1) and the related temperature limits.

cells are vertically stacked[10]and also for instance in 3D sequential integration[16]. Besides the thermal budgetfitting, additional benefits of low temperature processing include the following:

•

•

•

The latter point is of particular interest, because some planar technologies rely on materials with a low melting point or decom-position temperature, such as phase-change materials, InP andflexible substrates (polymer foils in particular). In such cases, all process steps are low-temperature. However, even at these lower temperatures, thermal budgetfitting is still part of the process integration puzzle.

Reducing the deposition temperature of thinfilms however tends to go at the expense of growth rate and film quality. Growth rate has progressively lost importance in integrated circuit manufacturing be-cause of miniaturization; deposition rates below 1 nm/min are nowa-days acceptable for some parts of the microchip. Film quality is how-ever a critical concern. Many studies in literature report the dependence offilm quality on the deposition temperature, see e.g.[17–26]; and for each case, an optimum temperature is found (as can be expected). In Fig. 3, this is illustrated by summarizing several studies of one aspect of film quality, the dielectric strength, of an insulating film as a function of the deposition temperature.

At the low end of the temperature range, deposition experiments are often limited by the low growth rate; or by the undesired formation of a different species or crystallinity. At the highest deposition tempera-tures, the used equipment often limits the temperature. It may also occur that precursors become unstable at high temperatures, leading to premature decomposition in the reactor. In spite of these experimental boundary conditions, several articles in literature describe the effect of the deposition temperature on a material's dielectric strength over quite a wide range of temperatures, as expressed inFig. 3.

Thefigure first of all illustrates that dielectric strength is normally dependent on the deposition temperature. The most common trend visible in thisfigure is that lower deposition temperatures yield lower dielectric strength. This is attributed to various root causes. The che-mical bonds in the material, its density and/or its stoichiometry may be affected by the deposition temperature, to name a few. One could create similar Figures for other material properties, such as hardness, density, hysteresis or optical absorption; however, this is beyond the scope of the present article.

As the same figure indicates, some studies show a maximum di-electric strength at a certain temperature within the studied range, while others conclude that either the lowest or the highest studied temperature yields the highest dielectric strength. Arguably, there must be an optimum temperature for maximum dielectric strength for each choice of deposition method and precursors.

These studies show that the optimum temperature depends not only on the deposited material but also on the chosen deposition technique and the used precursors. This deposition technique dependence moti-vates the systematic search for depositions that produce high-quality thinfilms at relatively low temperatures. The most investigated low-temperature approaches are described and reviewed in the next section. 3. Low-temperature deposition approaches

Deposition of a good-qualityfilm requires the correct ratio of ele-ments (stoichiometry), the formation of strong chemical bonds and a high packing density of atoms; the constituents should have reacted fully and formed the thermodynamically stable crystalline form. Further, the best layer thickness uniformity is obtained with layer-by-layer-growth [27]. To achieve this, typically one provides gaseous precursor molecules that physisorb to the substrate and diffuse over the surface, then to chemically react. High temperatures can be instru-mental in each stage. The transport of gaseous molecules towards the substrate surface (in case of diffusive transport in the gas phase), the diffusion over the surface and the chemical reaction all require thermal energy. The latter two steps determine the consistency of the thinfilm to a large extent.

Low-temperature deposition methods typically use other means than a high temperature to locally supply energy to enable surface diffusion and reaction. In the following, we will distinguish two types of approaches: one involves a local supply of energy at the substrate surface. The second approach provides highly reactive molecules or radicals instead of thermally stable precursors. These low-temperature approaches are further treated in the next two subsections.

3.1. Substrate surface heating approaches

In the sputtering deposition method, material is transported from a target to the substrate in a high vacuum. Depending on the process parameters, atoms, radicals and/or ions may reach the substrate with high kinetic energy. Given the supply of energy and the high deposition rate, the surface heating can be considerable. The released heat-of-condensation adds to that, yielding surface temperatures up to ~ 100° above the substrate temperature [15]. Sputtering ploughs into the upper few nanometers of the substrate surface. This leads to good ad-hesion on one hand, but a downside is that a damaged, mixed layer forms under the interface. As a consequence, this method can only be applied on top of non-critical layers.

Sputtering has found wide application in coating and micro-fabrication, in particular for metallicfilms. But as we miniaturize de-vices more and more, interfaces inside a device and their surrounding few nanometers become more and more significant for the device properties. Therefore more gentle deposition methods are favored. This is especially relevant at the interface between metal and insulator, e.g. for metal gates [28] and copper barriers in the microchip (see e.g. [29]).

The jet vapor deposition (or gas jet deposition) process[30,31]is another technique that supplies kinetic energy to precursor molecules before they reach the substrate. An ultrasonic jet is produced by a pressure difference over a nozzle and focused towards the substrate. Uniform coatings over larger areas are produced by mechanically scanning the nozzle over the surface. At impact, the kinetic energy may lead to decomposition of the precursor molecule and local heating, or at least the mobility of the surface atoms is enhanced by this bombard-ment. Compared to sputtering, jet vapor deposition delivers a lower Fig. 3. Dielectric strength of thin-film insulators as a function of their temperature of

deposition. Thefigure combines results obtained by chemical vapor deposition (Al2O3 [17]and BaxSr1−xTiO3[22]), defocused-laser CVD (Si3N4[18]), photo-CVD (SiO2[19]),

plasma enhanced chemical vapor deposition (Ta2O5[20], SiO2[21], SiNxwith three

different precursor combinations[23,26]and SiOC:H[24]) and rf sputtering (BCN, or perhaps BCxNy[25]). The shown dielectric strengths are not per se the highest reported in

literature; these data sets are chosen for the reported deposition temperature de-pendencies.

deposition rate at a higher pressure; the kinetic energy is orders of magnitude lower. Both physical and chemical vapor deposition results are published. Among others, excellent-quality thinfilms of SiO2and

Si3N4were deposited onflat substrates with this technique[30,31].

Illumination can also locally provide energy at the surface. In the laser CVD approach, a wavelength with low absorption in the gas is chosen to irradiate the substrate, either in a focused spot or unfocused [18,20]. By scanning a focused light beam, laser CVD can create pat-terned depositions without the need for lithography. Allen reports the successful deposition of Ni, TiO2and TiC[32]. In subsequent works,

authors commonly report the deposition of metals using this approach [33]. Given the focused laser beam, the deposit is severely non-uniform in thickness (see e.g.[33–35]). When a pulsed laser is used, the non-uniformity is further enhanced. This inherentfilm non-uniformity limits the application potential of laser CVD in microelectronic fabrication. It doesfind application in circuit edits and reticle repair[33]. Using un-focused laser light, layer thickness uniformities around 4% are reported [18].

Sputtering, jet vapor deposition and laser CVD are highly directional by nature. This directionality cannot be circumvented easily. Its detri-mental effects can only be partially overcome by wafer rotation and tilting. The step coverage is therefore poor; conformal growth cannot be achieved with these techniques.

3.2. Highly reactive molecules or radicals

Plasma-enhanced chemical vapor deposition (PECVD), with sput-tering, is the most employed low-temperature thin film deposition technique in integrated circuit manufacturing. It is commonly applied to deposit dielectric films in the back-end-of-line stage. The con-formality offilms deposited with PECVD is limited, as is the dielectric strength[15]. (Some implementations such as high density plasma CVD achieve reasonable conformality.) The density of PECVDfilms is com-monly low; sometimes layers are porous. Annealing leads to densifi-cation of the depositedfilm, but this requires an additional thermal step that may notfit within the thermal budget constraints. It should be noted that when the substrate is directly exposed to the PECVD plasma, bombardment of the surface can occur and surface heating phenomena as described in the previous subsection take place. Remote plasma processing avoids such circumstances.

Atomic layer deposition (ALD) is a special form of chemical vapor deposition. Alternating precursors form self-limiting “atomic layer” deposits on the wafer in this technique. In recent years, plasma-assisted atomic layer deposition (PAALD) has also successfully entered the in-tegrated circuit manufacturing arena. Whereas conventional (thermal) ALD is most commonly employed to form materials composed of two elements, such as metal oxides and metal nitrides, PAALD allows for the deposition of elemental materials, in particular noble metals, such as Pt, Ru and Pd[36]as well as Si, Ge[37]and Al[38].

As with PECVD versus CVD, the conformality of the deposition is normally compromised when plasma assisted processes are employed in atomic layer deposition[39]. Further, the plasma provides more than only the reactive radical wanted for the deposition process. Other molecules, radicals, ions as well as electrons and photons are also produced. Upon reaching the substrate surface these may influence the growth and material quality.

A clean supply composed only of the desired reactive molecule would lead to a better quality film. This motivates research on more gentle manners of precursor decomposition in the gas phase. The ap-proach can be generally termed as “radical-enhanced” CVD and ALD [37]. The mostly investigated techniques are photo-CVD (see e.g.[40] for a review) and hot-wire assisted CVD and ALD, as recently reviewed in [41,42]respectively. Photo-CVD makes use of an ultraviolet lamp that irradiates the precursor gases. Gases such as SiH4, O2and N2O will

decompose into neutral radicals upon photon absorption. More gen-erally, photochemical activation of a precursor molecule precedes its

encounter with the substrate surface. With this technique, thinfilms can be deposited close to room temperature[43,44]. Compared to PECVD, this goes at the expense of deposition rate. However both the film quality and the conformality of photo-CVD layers are better. Photo-CVD is commonly used for nanoparticle coating[40], an application where the deposition rate is not a critical concern.

For hot-wire assisted CVD and ALD a heatedfilament, in most cases a tungsten or tantalum wire heated by electrical current, is used to crack precursor molecules before their encounter with the substrate. The hot-wire CVD method draws interest for its capability to deposit good quality hydrogenated amorphous silicon thinfilms at a high de-position rate, attractive for the production of thin-film photovoltaic cells. It alsofinds application in other fields such as CVD-diamond and polymer deposition [41]. CVD with hot wires can reach appreciable deposition rates well over 10 nm/s, in particular when the wire is po-sitioned close (a few cm) to the substrate surface. This may come hand in hand with the unwanted effect of (local) substrate heating[45].

For atomic layer deposition with a hot wire, a distinctly different reactor geometry is needed. The hot wire must be remote from the substrate, as normally only one of the two ALD precursors should be exposed to the hot wire surface, whereas the other should not. Inherently, the deposition rates with such an approach will be a few nanometres per minute at best. Recent publications report the growth of pure, low-ohmic tungstenfilms with this technique[42].

3.3. Discussion

The techniques presented inSection 3.1that provide energy to the substrate surface yieldfilms of high quality at low substrate tempera-tures. They exhibit directionality, caused by the use of some kind of beam. Therefore conformal depositions are impossible in such ar-rangements. Sputtered metalfilms have excellent properties compar-able to bulk materials. Good uniformity and layer thickness control can be achieved. Jet vapor deposition yields good-quality dielectricfilms at temperatures lower than PECVD[46], as well as metal layers. In spite of the fact that the jet nozzle must scan the surface for a uniform de-position, high deposition rates over a micrometer per minute were re-ported on several hundred cm2_{substrates[31].}

To grow conformalfilms from the gas phase a different approach is however necessary, as the techniques ofSection 3.1are directional in nature. To facilitate conformal growth at low temperatures, the gas should contain highly reactive species with long lifetimes so as to avoid depletion and recombination effects. Several techniques are available for their formation. While plasmas provide high densities of reactive species, they cannot selectively provide the right radical needed for the deposition. Photo-CVD, especially with the use of specifically chosen wavelengths, and hot-wire CVD can provide a cleaner supply of re-actants. When such precursors are used in an atomic layer deposition system, the requirement of a long lifetime is complicating. As two precursors should remain separated in space or time, this implies that the source of the reactive species is better placed further away from the substrate. Both with remote plasmas and with a remotely placed hot wire, this approach has proven successful for various materials, in particular elemental metals[37,42].

Table 1provides a condensed overview of the deposition techniques treated in this article. The table lists the selection criteria most relevant to IC production. For completeness, spin coating is also mentioned al-though it was not treated earlier in this article. This technique is mainly used for photoresist and primer application. In older IC technologies (developed until the 1990s), SiO2and P- and B-doped silicon dioxide

were also spin-coated (termed spin-on-glass[15]). A curing step is used to remove the solvent after spin coating and to initiate chemical reac-tions. The curing is sometimes followed by a densification anneal. These treatments normally determine the thermal budget of spin coating. The step coverage is inherently poor; but spin coating does lead to planarization.

To illustrate the qualitative information in the table, typical de-position temperatures and growth rates are listed for the specific case of Si3N4. Other materials may be deposited at different temperatures

de-pending on the chemistry involved; yet, in relative terms the perfor-mance comparison between techniques remains similar.

4. Conclusions

Innovations in microchip manufacturing rely more and more on the development of new, high-quality thinfilms deposited at relatively low temperatures. As the layer thicknesses amount to only a few nan-ometers and the commercial value of the produced chips is high, the process cost and deposition rate can be traded in to benefit uniformity, defect density and electrical performance.

Developments in integrated circuit architecture, in particular 3D approaches, call for a reduction of the peak temperature of process steps. To maintain a good quality and to deposit conformally are the key challenges. Of the techniques discussed in this article, radical-en-hanced atomic layer deposition sticks out as the best performing along those criteria.

Acknowledgements

The author would like to express his gratitude to his former and current group members as well as Pierre Woerlee, formerly at Philips Research. They contributed in various ways to the development of the ideas and notions as presented in this article. Thanks to Dirk Gravesteijn, Ray Hueting, Alexey Kovalgin and Gertjan Koster (all at MESA+/the University of Twente) for their critical reading of this manuscript. The NWO Domain Applied and Engineering Sciences (NWO-TTW, formerly the Dutch Technology Foundation STW) is ac-knowledged for partial funding of the group's research program on low temperature thin film deposition under grant numbers 6358, 6630, 10017 and 12846.

References

[1] J.S. Kilby, Turning potential into reality: the invention of the integrated circuit, Nobel Lecture, 8 December 2000.

[2] M. Riordan, The silicon dioxide solution— how Jean Hoerni built the bridge from the transistor to the integrated circuit, IEEE Spectr. 44 (12) (2007) 51–56. [3] R.K. Bassett, To the Digital Age, John Hopkins University Press, Baltimore, 2002. [4] G.E. Moore, Cramming more components onto integrated circuits, Electronics, April

19, 1965, pp. 114–117.

[5] S. Thompson, Advanced CMOS device physics for 7nm and beyond, tutorial, IEEE-IEDM, 5 December 2015.

[6] International Technology Roadmap for Semiconductors, 2015 edition, available: public.itrs.net.

[7] K. Kim, Silicon technologies and solutions for the data-driven world, IEEE-ISSCC art. 1.1, 2015.

[8] S.J. Koester, A.M. Young, R.R. Yu, S. Purushothaman, K.-N. Chen, et al., Wafer-level 3D integration technology, IBM J. Res. Dev. 52 (6) (2008) 583–597.

[9] K.-T. Park, D.-S. Byeon, D.-H. Kim, A world'sfirst product of three-dimensional vertical NAND Flash memory and beyond, Proc. NVMTS, 2014.

[10] M. Joodaki, Uprising nano memories: latest advances in monolithic three dimen-sional (3D) integrated Flash memories, Microelectron. Eng. 164 (2016) 75–87. [11] K. Zeng, K.N. Tu, Six cases of reliability study of Pb-free solder joints in electronic

packaging technology, Mat. Sci. Eng. R 38 (2002) 55–105.

[12] H.R. Kotadia, P.D. Howes, S.H. Mannan, A review: on the development of low melting temperature Pb-free solders, Microelectron. Reliab. 54 (6–7) (2014) 1253–1273.

[13] G. Wang, C. Merrill, J.-H. Zhao, S.K. Groothuis, P.S. Ho, Packaging effects on re-liability of Cu/low-k interconnects, IEEE Trans. Dev. Mat. Reliab. 3 (4) (2003) 119–128.

[14] S. Wolf, Silicon Processing for the VLSI Era, Vol. 2— Process Integration, Lattice Press, Sunset Beach, 1990.

[15] S. Wolf, R.N. Tauber, Silicon Processing for the VLSI era, Vol. 1— Process Technology, 2nd edition, Lattice Press, Sunset Beach, 2000.

[16] C. Fenouillet-Beranger, P. Batude, L. Brunet, V. Mazzocchi, C.-M.V. Lu, F. Deprat, J. Micout, M.-P. Samson, B. Previtali, P. Besombes, N. Rambal, V. Lapras, F. Andrieu, O. Billoint, M. Brocard, S. Thuries, G. Cibrario, P. Acosta-Alba, B. Mathieu, S. Kerdilès, F. Nemouchi, C. Arvet, P. Besson, V. Loup, R. Gassilloud, X. Garros, C. Leroux, V. Beugin, C. Guerin, D. Benoit, L. Pasini, J.-M. Hartmann and M. Vinet, Recent advances in low temperature process in view of 3D VLSI integration, Proc. S3S 2016, art. no. 7804404.

[17] V.J. Silvestri, C.M. Osburn, D.W. Ormond, Properties of Al2O3films deposited from

the AlCl3, CO2, and H2system, J. Electrochem. Soc. 125 (6) (1978) 902–907. [18] J.M. Jasinski, B.S. Meyerson, T.N. Nguyen, Excimer laser-induced deposition of

silicon nitride thinfilms, J. Appl. Phys. 61 (1) (1987) 432–435.

[19] C.J. Huang, Y.K. Su, Effect of substrate temperature on the properties of SiO2/InP

structure prepared by photochemical vapor deposition, J. Appl. Phys. 67 (1990) 3350,http://dx.doi.org/10.1063/1.345372.

[20] I. Kim, J.-S. Kim, B.-W. Cho, S.-D. Ahn, J.S. Chun, W.-J. Lee, Effects of deposition temperature on the electrical properties of electron cyclotron resonance plasma-enhanced chemical vapor deposition Ta2O5film and the formation of interfacial

SiO2, J. Mater. Res. 10 (11) (1995) 2864–2869.

[21] K. Ishii, D. Isshiki, Y. Ohki, H. Nishikawa, M. Takiyama, Role of point defects in dielectric breakdown of SiO2formed by plasma-enhanced chemical vapor

deposi-tion of tetraethoxysilane, Jpn. J. Appl. Phys. 34 (1995) 205–211.

[22] G.T. Stauf, S. Bilodeau, R.K. Watts, BaSrTiO3thinfilms for integrated high

fre-quency capacitors, Proc. IEEE ISAF, 1996, pp. 103–106.

[23] M. Arps, A. Markwitz, Improved current–voltage characteristics of downstream plasma enhanced chemical vapor deposition SiN deposited at low temperature by using He as a dilution gas, J. Vac. Sci. Technol. A 15 (4) (1997) 1864–1873,http:// dx.doi.org/10.1116/1.580653.

[24] S.-K. JangJean, C.-P. Liu, Y.-L. Wang, W.-S. Hwang, W.-T. Tseng, S.-W. Chen, K.-Y. Lo, Fluorine-modified low-k a-SiOC:H composite films prepared by plasma en-hanced chemical vapor deposition, Thin Solid Films 447–448 (2004) 674–680, http://dx.doi.org/10.1016/j.tsf.2003.09.038.

[25] A. Prakash, K.B. Sundaram, Studies on electrical properties of RF sputtered de-posited boron carbon nitride thinfilms, ECS J. Sol. State Sci. Technol. 4 (5) (2015) N25–N29,http://dx.doi.org/10.1149/2.0071505jss.

[26] M. Maeda, Y. Arita, Electrical properties and their thermal stability for silicon ni-tridefilms prepared by plasma-enhanced deposition, J. Appl. Phys. 53 (10) (1982) Table 1

Key properties of thin-film deposition techniques. As Si3N4has been deposited by most techniques listed here, typical deposition conditions for this material are given as an example to

enable a more quantitative comparison of temperatures and deposition rates. For additional references, see the main text,Section 3. RT stands for room temperature. An ALD cycle may take 1 s to 1 min depending on the reactor geometry.

Technique Growth rate Conformality Uniformity Film quality

Temperature Si3N4typical conditions Remarks

Thermal low pressure CVD + ++ ++ ++ High 700–900 °C; 10 nm/min[15] Low cost of ownership; batch processing

Atmospheric pressure CVD ++ 0 0 + High 700–900 °C; 5–35 nm/min

[47,48]

Low cost of ownership; batch processing; particle risk

Laser CVD − − 0 0 Medium 200–500 °C; 2 nm/min[18] Not (yet) in IC production

Photo-CVD − ++ + − Medium (No data) Not (yet) in IC production

Plasma-enhanced CVD ++ + 0 − Low 200–350 °C; 20–50 nm/min

[15]

ECR/ICP CVD − ++ + + Low Near RT; 1 nm/min[49]

Jet vapor deposition − − − + Low RT; 2 nm/min Not (yet) in IC production

Thermal ALD − ++ ++ ++ Medium 400–600 °C; 0.2–0.3 nm/

cycle[50] Plasma- and radical-enhanced

ALD

− + ++ ++ Low (No data)

Sputtering ++ − − 0 Low RT–500 °C; 10–50 nm/min

[51,52]

Low cost of ownership; particle risk

6852–6856.

[27] S. Franssila, Introduction to Microfabrication, 2nd edition, Wiley, Chichester, 2010. [28] K. Nakajima, Y. Akasaka, T. Saito, K. Matsuo, A. Yagishita, K. Suguro, Damascene

metal gate technology, Proc. Advanced Metallization Conference, 2000, pp. 529–534.

[29] M. H. van der Veen, N. Jourdan, V. Vega Gonzalez, C. J. Wilson, N. Heylen, O. Varela Pedreira, H. Struyf, K. Croes, J. Bömmels and Zs. Tőkei, Barrier/liner stacks for scaling the Cu interconnect metallization, Proc. 2016 IEEE IITC/AMC, pp. 28–30.

[30] B. L. Halpern, J. J. Schmitt, J. W. Golz, Y. Di and D. L. Johnson,“Gas jet deposition of thinfilms,” Appl. Surf. Sci. 48/49 (1991) pp. 19–26.

[31] B.L. Halpern, J.J. Schmitt, Multiple jets and moving substrates: jet vapor deposition of multicomponent thinfilms, J. Vac. Sci. Technol. A 12 (4) (1994) 1623–1627. [32] S.D. Allen, Laser chemical vapor deposition: a technique for selective area

deposi-tion, J. Appl. Phys. 52 (1981) 6501–6505,http://dx.doi.org/10.1063/1.328600. [33] T.H. Baum, P.B. Comita, Laser-induced chemical vapor deposition of metals for

microelectronics technology, Thin Solid Films 218 (1992) 80–94.

[34] O. Conde, A. Kar, J. Mazumder, Laser chemical vapor deposition of TiN dots: a comparison of theoretical and experimental results, J. Appl. Phys. 72 (2) (1992) 754–761.

[35] C. Garrido, H. Van Den Bergh, Formation of Pt interconnection lines and periodic structures, Jpn. J. Appl. Phys. 32 (1993) 1312–1316.

[36] J. Hämäläinen, M. Ritala, M. Leskelä, Atomic layer deposition of noble metals and their oxides, Chem. Mater. 26 (2014) 786–801.

[37] S.M. George, Atomic layer deposition: an overview, Chem. Rev. 110 (2010) 111. [38] Y.J. Lee, S.-W. Kang, Atomic layer deposition of aluminum thinfilms using an

al-ternating supply of trimethylaluminum and a hydrogen plasma, Electrochem. Solid-State Lett. 5 (2002) C91.

[39] H.B. Profijt, S.E. Pott, M.C.M. van de Sanden, W.M.M. Kessels, Plasma-assisted atomic layer deposition: basics, opportunities, and challenges, J. Vac. Sci. Technol. A 29 (2011) 050801.

[40] C.A. Dorval Dion, J.R. Tavares, Photo-initiated chemical vapor deposition as a scalable particle functionalization technology (a practical review), Powder Technol.

239 (2013) 484–491.

[41] R.E.I. Schropp, Industrialization of hot wire chemical vapor deposition for thinfilm applications, Thin Solid Films 595 (2015) 272–283.

[42] A.Y. Kovalgin, M. Yang, S. Banerjee, R.O. Apaydin, A.A.I. Aarnink, S. Kinge, R.A.M. Wolters, Hot-wire assisted ALD: a study powered by in situ spectroscopic ellipsometry, Adv. Mater. Interfaces (2017) 1700058, ,http://dx.doi.org/10.1002/ admi.201700058.

[43] J.W. Peters, F.L. Gebhart, T.C. Hall, Low temperature photo-CVD silicon nitride: properties and applications, Solid State Technol. 23 (9) (1980) 121–126. [44] J.W. Peters, Low temperature photo-CVD oxide processing for semiconductor

de-vice applications, Technical Digest— IEEE IEDM, 1981, pp. 240–243.

[45] R.E.I. Schropp, Hot wire chemical vapor deposition: recent progress, present state of the art and competitive opportunities, ECS Trans. 25 (8) (2009) 3–14.

[46] D. Wang, T.P. Ma, J.W. Golz, B.L. Halpern, J.J. Schmitt, High-quality MNS capa-citors prepared by jet vapor deposition at room temperature, IEEE Electron Device Lett. 13 (9) (1992) 482–484.

[47] G. Beshkova, Shi Lei, V. Lazarova, N. Nedev, S.S. Georgiev, IR and Raman ab-sorption spectroscopic studies of APCVD, LPCVD and PECVD thin SiNfilms, Vacuum 69 (2003) 301–305.

[48] T. Otani, M. Hirata, High rate deposition of silicon nitridefilms by APCVD, Thin Solid Films 442 (2003) 44–47.

[49] G.I. Isai, J. Holleman, H. Wallinga, P.H. Woerlee, Low hydrogen content silicon nitridefilms deposited at room temperature with an ECR plasma source, J. Electrochem. Soc. 151 (10) (2004) C649–C654.

[50] K. Park, et al., Growth studies and characterization of silicon nitride thinfilms deposited by alternating exposures to Si2Cl6and NH3, Thin Solid Films 517 (2009)

3975–3978.

[51] S.M. Hu, L.V. Gregor, Silicon nitridefilms by reactive sputtering, J. Electrochem. Soc. 114 (8) (August 1967) 826–833.

[52] A. Oliveira, A. Cavaleiro, M.T. Vieira, Production and characterization of Si—N films obtained by r.f. magnetron sputtering, Surf. Coat. Technol. 60 (1993) 463–467.