MASH ADC
Analysis and design of an opamp-less VCO-based
Academic year 2019-2020
Master of Science in Electrical Engineering - main subject Electronic Circuits and Systems Master's dissertation submitted in order to obtain the academic degree of
Counsellor: Ir. Jonas Borgmans
Supervisor: Prof. dr. ir. Pieter Rombouts
Student number: 01408331Preface
Finishing a master’s thesis in times of a global pandemic is a bit odd. If it weren’t for the immensely interesting topic and if it weren’t for the great support and help I received, this work wouldn’t have been nearly as good as it is now. Maybe it wouldn’t have been finished at all. So special thanks goes out to everyone who helped to make it happen.
I would like to thank Professor Dr. Pieter Rombouts for increasing my interest in analog circuits. First by being great at teaching the interesting analog electronic courses and then by pointing me to this very interesting and challenging subject.
I would also like to thank Jonas Borgmans for the incredible amount of guidance he provided. The weekly meetings and honest, constructive feedback were a huge help.
My parents who were there for me and who provided moral support also deserve thanks. And I would also like to thank my fellow students Brendan and Edward for providing a fun, amicable work environment before the quarantine.
And to all other people who supported me throughout this year, or throughout my studies in general, I would like to say: “Thank you!”
Inigo Lowagie, june 2020
Admission to use
The author gives permission to make this master dissertation available for consultation and to copy parts of this master dissertation for personal use. In all cases of other use, the copyright terms have to be respected, in particular with regard to the obligation to state explicitly the source when quoting results from this master dissertation.
Inigo Lowagie, june 2020
iii
Analysis and Design of an Opamp-less
VCO-based MASH ADC
by Inigo Lowagie
Master’s dissertation submitted in order to obtain the academic degree of Master of Science in Electrical Engineering – main subject Electronic
Circuits and Systems Academic year 2019–2020
Supervisor: Prof. Dr. Ir. Pieter Rombouts Counsellor: Ir. Jonas Borgmans Faculty of Engineering and Architecture
Ghent University
Abstract
In this work, an open-loop 1-1 MASH VCO-based ADC architecture is analyzed and designed. First, the operation of the MASH is analyzed with system level models. This allows for estimates of the effect that certain expected non-idealities will have on the MASH’ perfor-mance. The models are also used to find the VCO parameters which would result in the best performance.
Once these parameters are found, the system can be designed and simulated on a circuit level using TSMC’s 28 nm technology node. The simulations of the design will result in more realistic specifications that can then by compared to current, similar ADCs.
Keywords
1
Analysis and Design of an Opamp-less
VCO-based MASH ADC
Inigo Lowagie
Supervisors: Pieter Rombouts, Jonas Borgmans
Abstract—In this work, open-loop MASH VCO-based ADCs are studied on a theoretical level, on a system-level and on a circuit- or transistor-level. A open-loop MASH VCO-based ADC that realizes second order noise-shaping is then designed and simulated in a 28nm technology. Index Terms—analog-to-digital conversion (ADC), VCO-based ADC, multistage noise shaping (MASH)
I. INTRODUCTION
W
ITH today’s advancement in wireless technology there is a demand for high-performance, low-power, mostly-digital ADCs. There is a trend towards more integration of wireless systems in more advanced technology nodes. As such, mostly digital ADCs are attractive in the sense that they benefit from technology scaling [1]–[4]. An important and well established ADC architecture that is mostly-digital is the SAR ADC [5], [6]. But VCO ADCs are recently becoming a promising architecture. VCO ADCs provide noise-shaping like Σ∆ modulators, but in a mostly-digital manner so that they scale better with technology than traditional Σ∆ modulators [7], [8].The focus of this work is an open-loop MASH VCO-based ADC. The open-loop structure is chosen to avoid the high power consumption that is to be expected from a feedback DAC. The closed-loop architectures for VCO ADCs were mostly designed to counter poor VCO linearity [9], but today, high linearity can be achieved with some improved voltage controlled ring oscillator designs [10], [11]. In an open-loop, however, higher order noise-shaping can not be directly implemented and tricks have to be used if higher order noise-shaping is needed [12]. One –but not the only– trick is to use multiple VCO-ADCs in a MASH structure.
This paper is organized in six sections. Section II quickly sums up how a MASH VCO ADC works in theory. In section III, an overview of system-level simulations, which were run to find out how certain parameters or non-idealities affect the performance, is given. Section IV handles the circuit-level design of the MASH. In section V, the performance of the system is compared with other, similar works and in section VI, a conclusion is drawn.
II. MASH VCO ADC
MASH, or multistage noise-shaping, is a technique from Σ∆ modulators [13]. In a MASH structure, the quantization error is extracted from a shaping ADC and fed into a similar noise-shaping ADC. Then, the two outputs are added together in a digital processing block, in a way that the first stage’s quantization noise is canceled out as much as possible, while the second stage’s quantization noise experiences higher order noise shaping. In a case of a 1-1 MASH, this operation boils down to equation 1.
Y1(z) = X(z) + 1− z−1Q1(z)
Y2(z) =−Q1(z) + 1− z−1Q2(z)
Ytotal= Y1(z) + 1− z−1Y2(z)
= X(z) + 1− z−12Q2(z)
(1)
In [12], it was proven that, if the fundamental PFM encoding error is kept minimal, this equation is also applicable to VCO ADCs. In this case, the quantization error is the aliasing error caused by the aliasing of PFM sidebands into the signal bandwidth.
III. SYSTEM-LEVELSIMULATIONS
A. Single Stage VCO ADC
First, a single stage, single phase VCO ADC was simulated in MATLAB Simulink. Using the equation from [12] for the funda-mental PFM encoding error, it was found that, when using only a single phase, this error is too close to the simulated SQNR of the system. As the noise-shaping, be it second- or first order, only applies to the aliasing error and not to the fundamental encoding error, using single phase VCO ADCs in a MASH would not provide the wanted performance benefit expected from second order noise shaping.
By means of a sweep over the number of used VCO output phases, it was found that using 30 phases would provide with a good performance of the single stage VCO ADC and a low enough fundamental PFM encoding error. A comparison of the system level simulation of the single stage, single phase VCO ADC and the single stage 30-phase VCO ADC is given in figure 1.
Figure 1. Single stage, single phase VCO ADC compared to the single stage, 30 phase VCO ADC. Over a bandwidth of fs/2, the single phase VCO ADC
has an SQNR of 54 dB, while the 30 phase has one of 75 dB.
This 30 phase single stage VCO ADC can now be expanded to a MASH. Each phase has its own 1-bit reset-counter which realizes the noise shaping. So each phase can be made to output an error bit as was also shown in [12]. The system-level 30-phase MASH is compared with the 30-phase single stage VCO ADC in figure 2. B. Effect of a MASH Gain Offset
Now that the performance benefits of the MASH are known, its reaction on different effects and parameters can be tested on a system-level. In [13], it was noted that a gain offset could affect the Σ∆ MASH. In MASH VCO ADCs, this gain error can result from a mismatch between the KV CO of the two stages as was noted in
[12].
The effect different VCO gain offsets have on the SQNR is plotted in figure 3. It can be observed that even with a certain gain offset, e.g.
2
Figure 2. Difference between the MASH and single stage VCO ADC output spectrum.
10%, the MASH still provides a significant benefit over the single stage VCO ADC.
The effect of a gain error can be described with equation 2, where α = KV CO,2/KV CO,1.
Y = X + (1− α) 1 − z−1Q1+ 1− z−1 2
Q2 (2)
Figure 3. Effect of VCO gain offset on the MASH performance
C. Effect of Delay in the MASH
The effect of a delay between two MASH stages is researched in figure 4. A delay between the two MASH stages has no significant effect on the performance of the MASH. Like a gain error, the delay will cause leakage of the first stage’s quantization noise into the total output spectrum. But unlike a gain error, where this noise will be first order noise shaped, the delay will result in extra shaping of this error. This causes the error to stay mostly under the second order noise shaped quantization error so that the SQNR is not affected.
The effect causes the output spectrum of equation 3, where τ would be the delay. [.]∗represents the sampling operation.
Y = X + 1− z−1 h1− e−jsτi∗Q1+ 1− z−1 2
Q2 (3)
D. Effect of slewing in the MASH
The effect of slowing down the rise or fall time of the error signal is presented in figure 5. The X-axis of this figure represents the maximum rate of change of the signal during a sample period.
Each error bit goes from 0 to 1. From figure 5, it can be concluded that the error signal needs to be able to rise (or fall) in a time of about .4Ts, so less than halve the sample period, to not affect the SQNR.
When the error bits can’t rise or fall during completely in a sample period or longer, the MASH starts to act like a single stage VCO
Figure 4. Effect of delay between stages on the MASH performance
ADC. That is why the SQNR goes back up again. It would be like cutting the connection between the two stages.
Between good MASH operation and single stage operation, the limiting of the error signal negatively affects the SQNR in a way that the MASH has worse performance than a single stage VCO ADC. The slow error signal adds unwanted signal components that severely affect the SQNR.
Figure 5. Effect of slewing of the error signal between stages on the MASH performance. SR represents the maximum rate of change of the error signal during a clock period.
E. Ideal VCO Parameters
Figure 6 shows how different VCO parameters affect the overall MASH SQNR. This can be used for sizing the VCO.
Figure 6. Effect of VCO parameters on the MASH performance
IV. CIRCUIT-LEVELDESIGN
The complete circuit will consist of two instances of the circuit presented in figure 7 in a differential configuration. These two will be driven by a differential signal.
A. VCO
One of the most important components is the VCO. The VCO that will be used is the VCO from [11]. It is a highly linear, pseudo-differential VCO, which is ideal for open-loop VCO ADCs.
3
Figure 7. MASH system without digital processing in a non-differential configuration
B. 1-bit Reset Counter
The 1-bit reset counter consists of two types of digital components as can be seen in figure 7. Per counter, two edge-triggered D flip-flops are needed. Both counters’ outputs are obtained with a XOR gate. The first stage also needs to output an error signal which requires another XOR gate.
The XOR gates are implemented as pass-transistor logic, based on [14] to limit power consumption and to improve the switching speed. Because these gates add to the load capacitance of the signals, the output stages of the circuits driving the signals that pass through the gates need to be sized strong enough.
The ring-oscillators’ outputs are not synchronous with the clock signal. This means that, if a dynamic flip-flop were to used to store the VCO output on every clock edge, problems with meta-stability can be encountered. While the fast, low-power flip-flops are preferred, meta-stability will have a serious impact on the system’s performance. Because of this, the first flip-flop is chosen to be a transmission-gate based static flip-flop as in [14], and the second one is a C2MOS
dynamic flip-flop as in [14]. C. DCO
In the DCO, the same ring oscillator as in the VCO will be used. The control of the DCO oscillation frequency, however, is done using switched current sources. Each of these current sources is switched with an error bit and provides the same addition to the current that can flow through the oscillator.
There is also a current source added that remains on, regardless of the error value. This is done to prevent the DCO’s oscillation to stop. When running oscillator simulations, it can be seen that starting the oscillation of ring-oscillators might take a while. To prevent the DCO’s oscillator to completely stop oscillating when the error signal becomes zero for a short period, this offset current path was added. For the DCO parameters, this extra path adds to the DCO’s f0,
but since the second stage’s output will be differentiated, this does not add to any form of VCO-DCO offset.
D. Complete System
Both the single stage as the MASH output spectra are presented in figure 8. The simulated systems are implemented and driven differentially. The bits are added together externally.
The designed MASH does not show second order noise shaping for the frequencies where it matters. Only for the high frequencies, where second order noise shaping results in more quantization noise than first order noise shaping, the MASH spectrum shows the desired shaping.
Figure 8. Comparison of the MASH output spectrum (red) to the single stage VCO ADC output spectrum (grey). Both have a SNDR of 57 dB. The input signal has an amplitude of 0.4 V and a frequency of 31.25 MHz.
This is mostly due to the limits of the DCO. Figure 9 shows time domain signals for one of the error bits. The clock is shown. As well as one error-bit and the current flowing through the current source that is switched by this bit. The sharp edges of the error signal show that the digital circuits generating it are fast enough to not miss small pulses.
The biggest problem here might result from the fact that in these switched sources, the current seems to start flowing immediately when they are turned on, but when they are turned off, the current does not turn off as quickly. This translates to a larger DCO output frequency for a significant amount of time, which results in erroneous DCO output pulses.
This uneven effect is different, and might be more destructive to the performance, than the effect researched in section III-D. The unwanted pulses generate a white noise floor that is added to the second stage’s output. This output is differentiated so that this white noise floor experiences first-order shaping that dominates the system’s second order shaping.
So a better DCO design is needed to allow the MASH to perform better than the single stage VCO ADC.
Figure 9. Time-domain analysis of the error signal and the response of the current source it drives.
V. COMPARISON WITHSIMILARWORKS
Table I provides a comparison with similar, mostly digital, ADCs. [16] is a time-interleaved VCO ADC, [17] is a MASH VCO-based ADC and [6] is a SAR ADC. The Schreier figure-of-merit [15] is used for the comparisons.
Since the MASH does not yet provide the full benefits of second order noise shaping, the performance of this system does not differ
4
much from using a single-stage, first order noise shaping VCO ADC, but with the power consumption of a MASH. The figure-of-merit still seems decent despite this. This shows that, if extra care is taken to either improve the DCO design this 1-1 MASH architecture could yield a well performing, low-power ADC.
This work [16] [17] [6]
technology (nm) 28 28 65 28
supply voltage (V) 0.9 1/0.85 1 0.9
architecture 1-1 MASH TI 1-1 MASH SAR
power (mW) 9.64* 22.7 0.75 0.35 fs(GHz) 8 5 0.056 0.1 number of bits 5 12 5 12 BW (MHz) 125 2500 1 50 SNDR (dB) 57 45.2 81.6 65.67 FoM (Schreier) (dB) 158* 155.6 172 177.2 Table I
COMPARISON WITH SIMILARADCS. *THE POWER CONSUMPTION DOES NOT INCLUDE THE DIGITAL PROCESSING NEEDED TO COMBINE THE BITS.
VI. CONCLUSION
While, in theory, open-loop MASH VCO-based ADCs, result in low-power, high-performance, higher order noise shaping ADCs, good care should be taken when designing the DCO for these systems in order to obtain this higher order noise shaping. But when this higher order noise shaping is obtained, very powerful ADCs for the wireless technologies of present and future can be constructed.
REFERENCES
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[2] G. Gielen and W. Dehaene, “Analog and digital circuit design in 65 nm cmos: End of the road?”, in Design, Automation and Test in Europe, vol. 1, Mar. 2005, pp. 37–42.
[3] P. R. Kinget, “Scaling analog circuits into deep nanoscale cmos: Obstacles and ways to overcome them”, in 2015 IEEE Custom Integrated Circuits Conference (CICC), Sep. 2015, pp. 1–8.
[4] L. L. Lewyn, T. Ytterdal, C. Wulff, and K. Martin, “Analog circuit design in nanoscale cmos technologies”, Proceedings of the IEEE, vol. 97, no. 10, pp. 1687–1714, Oct. 2009. [5] W. Kester, “Which adc architecture is right for your
applica-tion”, in EDA Tech Forum, vol. 2, 2005, pp. 22–25.
[6] C.-C. Liu, M.-C. Huang, and Y.-H. Tu, “A 12 bit 100 ms/s sar-assisted digital-slope adc”, IEEE Journal of Solid-State Circuits, vol. 51, no. 12, pp. 2941–2950, 2016.
[7] R. Naiknaware, Haiming Tang, and T. S. Fiez, “Time-referenced single-path multi-bit /spl delta//spl sigma/ adc using a vco-based quantizer”, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 7, pp. 596–602, Jul. 2000.
[8] J. Kim, T. Jang, Y. Yoon, and S. Cho, “Analysis and design of voltage-controlled oscillator based analog-to-digital converter”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 1, pp. 18–30, Jan. 2010.
[9] E. Sacco, J. Vergauwen, and G. Gielen, “From open-loop to closed-loop single-vco-based sensor-to-digital converter ar-chitectures: Theoretical analysis and comparison”, in 2019 IEEE 8th International Workshop on Advances in Sensors and Interfaces (IWASI), Jun. 2019, pp. 29–34.
[10] A. Babaie-Fishani and P. Rombouts, “Highly linear VCO for use in VCO-ADCs”, Electron. Lett., vol. 52, no. 4, 268–269, Feb. 2016.
[11] J. Borgmans and P. Rombouts, “Enhanced circuit for linear ring VCO-ADCs”, Electron. Lett., vol. 55, no. 10, 583–585, May 2019.
[12] E. Gutierrez, L. Hernandez, F. Cardes, and P. Rombouts, “A Pulse Frequency Modulation Interpretation of VCOs Enabling VCO-ADC Architectures With Extended Noise Shaping”, IEEE Trans. Circuits Syst.-I: Regular Papers, vol. 65, no. 2, 444–457, Feb. 2018.
[13] Y. Matsuya, K. Uchimura, A. Iwata, T. Kobayashi, M. Ishikawa, and T. Yoshitome, “A 16-bit oversampling a-to-d conversion technology using triple-integration noise shaping”, IEEE Journal of Solid-State Circuits, vol. 22, no. 6, pp. 921– 929, Dec. 1987.
[14] J. Rabaey, A. Chandrakasan, and B. Nikolic, “Digital inte-grated circuit-a design perspective”, Jan. 2003.
[15] R. Schreier, G. C. Temes, et al., Understanding delta-sigma data converters. IEEE press Piscataway, NJ, 2005, vol. 74. [16] M. Baert and W. Dehaene, “A 5-gs/s 7.2-enob time-interleaved
vco-based adc achieving 30.5 fj/cs”, IEEE Journal of Solid-State Circuits, 2019.
[17] H. Maghami, P. Payandehnia, H. Mirzaie, R. Zanbaghi, S. Dey, K. Mayaram, and T. S. Fiez, “A highly linear ota-free vco-based 1-1 mash delta sigma adc”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 7, pp. 2440–2453, 2019.
Contents
Preface i Admission to use ii Abstract iii Extended abstract iv Contents viii Used abbreviations x 1 Introduction 1 2 Theoretical basis 3 2.1 Oversampling ADCs . . . 3 2.2 The PFM spectrum . . . 6 2.3 First-order VCO-ADCs . . . 9 2.4 MASH structures . . . 12 3 System-level modeling 15 3.1 First-order VCO-ADCs . . . 153.1.1 Effect of the amount of VCO phases . . . 18
3.2 VCO-ADC MASH . . . 20
3.2.1 Effect of a VCO gain offset . . . 22
3.2.2 Effect of delay between stages . . . 24
3.2.3 Effect of limited rise and fall time between stages . . . 26
3.2.4 Ideal VCO parameters . . . 28
4 Circuit-level design 30 4.1 The VCRO . . . 30
4.1.1 Sizing and simulation results . . . 34
4.1.2 VCO conclusion . . . 46
4.2 The error generating 1-bit reset counter . . . 47
4.2.1 Flip-flops . . . 47
CONTENTS ix
4.2.2 XOR-gates . . . 51
4.2.3 Total 1-bit reset counter design . . . 52
4.3 The single stage VCO ADC . . . 54
4.4 The DCO . . . 54
4.4.1 DCO circuit design . . . 56
4.4.2 Simulation results . . . 58
4.4.3 DCO conclusion . . . 59
4.5 The complete MASH . . . 59
5 Results 63
6 Conclusion 65
Appendices 69
Used abbreviations
ADC Analog-to-Digital Converter BW Bandwidth
C2MOS Clocked CMOS
DAC Digital-to-Analog Converter DCO Digitally controlled Oscillator FF Flip-flop
FoM Figure-of-Merit
MASH Multistage Noise Shaping NCF Noise Cancellation Filter NTF Noise Transfer Function OSR Oversampling Rate/Ratio
PFM Pulse Frequency Modulation/Modulator PN Phase Noise
SAR Successive Approximation Register SNDR Signal to Noise and Distortion Ratio SNR Signal to Noise Ratio
SQNR Signal to Quantization Noise Ratio STF Signal Transfer Function
THD Total Harmonic Distortion
VC(R)O Voltage Controlled (Ring) Oscillator XOR Exclusive Or
ZOH Zero Order Hold
Chapter 1
Introduction
An ever increasing demand for higher data rates and more bandwidth for wireless commu-nication leads to an increasing need for better wireless technologies. 5G is being developed to meet these demands. But, as with all things, trade-offs need to be made. For 5G, the higher bandwidth and lower latency is reached by significantly increasing the complexity of the hardware –and software– needed. A further complication is that this hardware also needs to be more mobile as most communication today is done through smartphones.
The hardware to support the networks of the future needs to work at higher frequencies and lower power than the hardware of previous generations. This results in an increasing demand for highly integrated, low-cost mixed-signal systems with demanding specifications. As this hardware becomes more complex while also being miniaturized, the integration of these systems is evolving towards deep submicron and nanometer scale CMOS. Smaller feature sizes generally result in reduced area. The lower supply voltage and thinner gate oxides that come with these technologies generally results in faster switching of digital circuits. However, for analog circuits, the reduced supply voltage and increased effect of non-idealities that generally come with these technologies result in serious design challenges [1]–[3].
This thesis will focus on one of the most important building blocks for wireless technolo-gies, the analog-to-digital converter or ADC. Because these ADCs sit at the border between the analog and digital domain, they are made with a combination of analog and digital build-ing blocks.
Today, when low quantization noise is required, Σ∆ modulators are used to realize high-performance ADCs. Σ∆ modulators realize noise shaping. Together with oversampling, this can limit quantization noise inside the signal bandwidth. The noise shaping is realized with integrators, which are analog.
SAR ADCs are often used when working in deep sub micron, as this architecture is mostly digital and scales well with technology. These ADCs can operate over higher bandwidths, because of the lack of oversampling, but SAR ADCs generally have a lower resolution than Σ∆ ADCs [4].
2
VCO-based ADCs are like Σ∆ modulators, but the integration is done by using a voltage controlled oscillator [5], [6]. This VCO can be made with inverters. Further signal processing is then done using only digital building blocks. This way, a mostly-digital oversampling noise shaping ADC can be designed. It can be expected that the design scales better with CMOS technologies than traditional Σ∆ modulators while still keeping the advantage that Σ∆ ADCs have over SAR ADCs.
The VCO ADC will be realized as an open loop system. Thus power and area can be saved by not needing a feedback DAC. A problem with some VCOs – especially voltage controlled ring-oscillators – is that they have very poor linearity. Closed-loop architectures are sometimes used to counter this poor VCO linearity [7], but VCO architectures with high linearity do exist [8], [9].
Open-loop VCO ADCs that realize first order noise shaping have already been made, but higher order noise shaping is often required. The problem with the open-loop VCO ADC architecture is that this higher order noise shaping is not directly obtainable [10]. The goal of this thesis is to design a second order open loop noise shaping VCO ADC where the second order is achieved by using a technique borrowed from Σ∆ modulators, namely MASH (Multi-stAge noise-SHaping) [11]. MASH is a trick to obtain higher order noise shaping using multiple first order ADCs.
Chapter 2
Theoretical basis
In this chapter, a theoretical foundation for understanding VCO ADCs in general, and MASH VCO ADCs specifically will be elaborated. This theory is mainly based on the findings of [10] and [12]. First, a short overview of how oversampling ADCs work and how a VCO-based ADC accomplishes this behaviour is given in section 2.1. In section 2.2, the equivalence of the VCO spectrum and pulse frequency modulators is summarized. Then, in section 2.3, this theory will be used to better describe a generic first-order noise shaping VCO ADC. Section 2.4 will then describe how a VCO ADC MASH would work in theory based on [11] and [10].
2.1
Oversampling ADCs
An ADC converts an analog input signal to a digital output signal. A digital signal is discrete in both time and amplitude. An analog signal is continuous in both. To convert an analog signal to a digital signal, the signal needs to be discretized in both time and amplitude. Sampling is the discretization in time Quantizing is the discretization in amplitude.
A finite, band-limited analog signal can be represented in a finite number of bits. A simple Nyquist-rate ADC works by sampling and quantizing an analog input voltage. The sampling happens at a rate fs which is twice the bandwidth of the input signal, also known as the
Nyquist-rate.
These two operations have side-effects that make it so that the original analog signal can’t be perfectly recovered.
Sampling can cause aliasing. In the frequency domain, when an analog signal is sampled, copies of the original spectrum are repeated over multiples of the sampling frequency, fs.
This is drawn in figure 2.1.
This can result in overlap of the original spectrum with a copy of the spectrum. Then the signal is distorted and can’t be perfectly recovered. To avoid this distortion, the bandwidth of the input signal can be limited to fs/2. This can be forced by placing a low-pass filter in
front of the ADC. Figure 2.2 shows what happens if the Nyquist-rule is not followed.
2.1. OVERSAMPLING ADCS 4
(a) analog spectrum (b) sampled spectrum
Figure 2.1: Visualization of the effect sampling has on a signal’s spectrum
Figure 2.2: Frequency-domain plot of a signal that violates the Nyquist rule and experiences aliasing. The blue spectrum is the original analog spectrum. The red would be the distorted output spectrum after sampling with aliasing.
Quantization causes quantization noise. This noise is the error that is made by rounding of the signal amplitude to the nearest value that can be represented with the chosen number of bits. Quantization is often modeled as an addition of the signal with Q, the quantization noise, which is modeled as white noise with a variance as in equation 2.1, where q is the quantization step [13].
σ2Q= q
2
12 (2.1)
Oversampling ADCs are designed to decrease the effect of this quantization noise on the digital output signal [14]. The sampling frequency fs is chosen a factor bigger than the
bandwidth; fs
2BW = OSR is called the oversampling rate. Because the quantization noise is
added in a specific place in the system, namely when quantization happens, a system can be designed for which the transfer function of the noise Q to the output Y is different than the transfer function of the input X to the output Y . As such, the noise can be shaped so that it is attenuated over the actual bandwidth and pushed to the higher frequencies in the range [BW,fs
2.1. OVERSAMPLING ADCS 5
Figure 2.3 shows how oversampling and noise shaping can improve performance. In real systems, the area under the red curve is more or less the same so it’s not that noise can be removed out of the system without removing information. But in the right figure, the quantization noise is a lot smaller close to the signal bandwidth than without shaping. After noise-shaping, the signal can be downsampled to only include the frequencies in the chosen bandwidth, fs/12 in this case. So the information in higher frequencies is thrown away, but
as this is above the agreed bandwidth, this is only noise.
In a sense, noise-shaping is a way to push the noise away from the signal to a place in the frequency domain where it can be easily removed without affecting the signal.
(a) output spectrum without noise-shaping (b) output spectrum with noise-shaping
Figure 2.3: Output spectra of an oversampling ADC
Figure 2.4: Simple model for oversampling ADCs
A generic oversampling ADC can be modeled as in figure 2.4. The output of a generic oversampling ADC can be described as in equation 2.2. H is the loop-filter of the system. To get this filter to push the noise away from the signal without affecting the signal too much, H needs to have high gain for low frequencies and high attenuation at high frequencies. This can be done by using integrators.
Integrators have infinite DC gain. So for f going to 0, H goes to infinity and Y = 1·X+0·Q. For f going to infinity, Y = 0 · X + 1 · Q. The rate at which the transition between these two extremes happens depends on the order of H.
2.2. THE PFM SPECTRUM 6 Y = ST F · X + N T F · Q ST F = H 1 + H N T F = 1 1 + H (2.2)
The crux of the VCO-based ADC is that the analog input voltage is converted to the phase domain and integrated by means of a VCO. This way, the integration part of H is already obtained. Now, sampling and quantization can be realized with a reset counter, a block that counts the output edges of the VCO during a certain time interval, e.g. f1
s. This
reset counter can be implemented with digital building blocks.
Quantization in the phase domain is different than quantization in the voltage domain. Quantizing the phase on specific levels (say multiples of a certain time interval Ts) is the
same as sampling. So the quantization noise in VCO ADCs is a bit different than that in Σ∆ ADCs. Understanding this noise is key to designing good VCO ADCs.
2.2
The PFM spectrum
By relating the VCO operation inside a VCO ADC to Pulse-Frequency Modulation (PFM), the quantization noise in VCO ADCs can be better understood. A generic VCO ADC can be modeled better by the equivalent model drawn in figure 2.5 than by the traditional model drawn in figure 2.4, in which the sampling quantizer is modeled as a block that simply adds (approximately) white noise. The basic principles of oversampling and noise shaping of the previous chapter will still apply, but in a slightly different manner.
Figure 2.5: Model for a generic VCO ADC
The PFM block modulates the analog input. If the analog input is a simple sinusoidal signal (x(t) from equation 2.3), the spectrum of the modulated output, D(f ), can be described by equation 2.4.
2.2. THE PFM SPECTRUM 7 D(f ) = f0δ(f ) + AKV CO 2 (δ(f + fx) + δ(f − fx)) + M (f ) M (f ) = f0 ∞ X q=0 ∞ X r=−∞ Jr qAKV CO fx 1 +rfx qf0 (δ(f + (qf0+ rfx)) + δ(f − (qf0+ rfx))) (2.4) Equation 2.4 might look rather unwieldy. However, after plotting out the spectrum for different parameters, the spectrum can be understood more intuitively.
In figure 2.6, the PFM spectrum was plotted with different parameters. It is clear from the equation that the spectrum consists of a DC bias, a base tone at fx and some higher
frequency components. In the figure, one can see that these high-frequency components are modulation sidebands around harmonics of f0, each consisting of a main lobe and a tail. The
width of the main lobe at the qth harmonic can be approximated by equation 2.5. The speed at which the tails decay decreases when fx approaches f0.
(a) fx= f0/1024, AKV CO= f0/32 (b) fx= f0/1024, AKV CO= f0/4
(c) fx= f0/32, AKV CO= f0/32 (d) fx= f0/32, AKV CO = f0/4
Figure 2.6: Approximated PFM spectrum with different values for fx and AKV CO.
2.2. THE PFM SPECTRUM 8
Eventually, these sidebands will deteriorate the VCO ADC output in two ways: Firstly, the tails of the first sidebands could leak into the ADC bandwidth. This error can be reduced by making sure the first sideband is far enough from any possible input frequency. This was called the fundamental PFM encoding error in [10]. The magnitude of this fundamental error can be calculated using equation 2.6. The equation can be derived from equation 2.4.
SQN Rf und= 10 log10 AKV CO 2f0 2 Prmax r=rmin Jr AKV CO fx 1 + rfx f0 2 rmin= −BW − f0 fx rmax= BW − f0 fx (2.6)
Secondly, the higher sidebands will alias into the used bandwidth when the signal will be sampled. This aliasing error can be reduced by attenuating the sidebands before sampling. It is also the “white” quantization noise of the ADC. For high frequencies, the modulation side-bands start overlapping so that it may look a bit like white noise, but it’s not. Regardless, it is this noise component that will be shaped.
The output of the PFM block is a series of Dirac deltas with varying distances. The chance that a pulse is present on the exact time the sampler samples is very low because a Dirac delta has an infinitely narrow width. If these Dirac pulses were to be sampled directly, all information would be lost in theory. So, in order to sample the PFM output, the pulses need to be shaped first. This is done with the pulse-shaping filter.
Ideally, this filter keeps the base tone in the PFM spectrum and attenuates the modulation sidebands as much as possible. One way to accomplish this is by realizing an n-th order sinc in the frequency domain, Hn. This sinc filter has zeros at multiples of fs to attenuate the
high-frequency modulation sidebands, and poles in zero to compensate the attenuation at 0fs where the base tone lives. The higher the order of the pulse-shaping filter, the more the
modulation sidebands will be attenuated. The first- and second-order pulse-shaping filter are plotted in figure 2.7 as an example.
Hn(s) = sincn=
1 − e−sTsn
(sTs)n
(2.7) So how does the actual output spectrum of the VCO ADC look after this pulse shaping and sampling? First, take X(s) to be the base tone present in the PFM spectrum, and M (s) as the high-frequency components added by the PFM. Then the PFM block can be seen as an addition of the useful signal, X(s), with M (s) (the DC tone is ignored since it can be easily filtered out). Then, M (s) can be split up as MLF(s) and MHF(s), where MLF(s) represents
the fundamental PFM encoding error and MHF(s) all the higher frequency components that
alias to the baseband after sampling. Both X(s) and MLF(s) will pass through the filter
2.3. FIRST-ORDER VCO-ADCS 9
Figure 2.7: Plot of the spectrum of the first and second order pulse-shaping filter.
For MHF(s), Hn can be split up; after sampling, 1 − e−sTs
n
becomes (1 − z−1)n. Lets call
MHF(s)
(sTs)n Mal(s), which becomes Ual(z) after sampling. The output, Y (z) can be described as
in equation 2.8 (The [.]∗indicates sampling). In figure 2.8, these signals are plotted in a more theoretical representation of the system.
Y (z) = [ST F X(s)]∗+ [ST F MLF(s)]∗+ Ual(z)(1 − z−1)n (2.8)
Figure 2.8: Theoretical model on which equation 2.8 is based
From equation 2.8, it can be concluded that an n-th order pulse-shaping filter will result in n-th order noise-shaping, where Mal(z) acts like the quantization noise. One important
conclusion is also that the noise from the fundamental PFM encoding error can’t be pushed down by realizing higher-order noise-shaping. Hence the adjective “fundamental”.
2.3
First-order VCO-ADCs
First order pulse shaping can be realized easily with just a zero-order hold filter that holds the signal for a sampling period, Ts, because H1(s) in equation 2.7 is a simple first-order sinc.
2.3. FIRST-ORDER VCO-ADCS 10
(a) generic first order VCO ADC
(b) PFM equivalence
Figure 2.9: equivalence of a VCO with a PFM in the context of a VCO ADC
If the edges of w(t) are far enough from each other to be detected after sampling, it is sufficient to proof that pa(t) from figure 2.9a equals pb(t) from figure 2.9b. Then ysa[n] will
equal ysb[n]. pa(t) is defined as w(t) ⊗ w(t − Ts). It is composed of square pulses that start at
times tk where there is an edge in the VCO output w(t). So if the δ(t) block outputs a pulse
on the rising and falling edge, then pa(t) is indeed equal to pb(t).
The equivalence can also be found by analyzing the expected output waveforms. Eventu-aly, the output should look like in figure 2.10.
Figure 2.10: Expected output for the 1-bit reset counter that realizes the PF modulation and pulse-shaping together with the VCO when triggering on both rising and falling edges.
In order for the edges of the VCO output to be far enough from each other to be detected after sampling, the minimum oscillation period of the VCO is limited. It is limited to twice the sampling period in this case, since the edge-detector triggers twice during a period of w(t). Or rather, the minimum sampling frequency is limited to twice the maximum VCO frequency.
2.3. FIRST-ORDER VCO-ADCS 11
However, if the XOR gate were to be replaced with, for example, an AND gate where the delayed VCO output is inverted, then the edge detector in the equivalent PFM model only triggers on positive edges. For this system, the minimum sampling period now sim-ply becomes the maximum oscillation frequency of the VCO. Therefore, the term effective oscillation frequency was introduced in [10]. Assuming that the input signal is limited to values between -1 and 1, the sampling frequency of the ADC needs to satisfy the condition in equation 2.9.
fs,min= 2fmax,osc = (fmax,osc)ef f = (f0+ KV CO)ef f (2.9)
Notice that the VCO ADC output from figure 2.9a will be limited to one bit if implemented directly. A way to increase the depth of the VCO ADC output, one can use multiple VCO output phases. If the VCO is realized as a voltage-controlled ring oscillator, this can be easily done by tapping after multiple equidistant delay cells, implementing the pulse-shaping for each of these phases, sampling and then adding the output bits together. This is illustrated in figure 2.11.
Figure 2.11: Same VCO ADC as figure 2.9a, but with multiple VCO phases used The usage of multiple VCO phases also has a positive effect on the output spectrum of the VCO ADC. In [15] this effect is analyzed. It was found that using multiple phases would push the modulation sidebands from the harmonics of f0 in equation 2.4 to harmonics of
M f0 where M is the amount of phases used. And because the pulse-shaping is done for each
phase individually, this increase in effective oscillation frequency doesn’t result in harsher constraints on the sampling frequency.
This is a useful property. It reduces the effect of fundamental error that is caused by the tail of the first modulation sideband as this sideband is pushed further away from the signal bandwidth. Eventually it also reduces the effect of the modulation sidebands that are aliased
2.4. MASH STRUCTURES 12
on the signal bandwidth after sampling, because the pulse-shaping filter will attenuate more at higher frequencies.
Constructing a first-order VCO ADC is quite straight-forward because the first-order pulse-shaping filter can be easily implemented directly with digital blocks. But often, first-order noise shaping is not enough. But how does one implement Hn(s) with n > 1 using only
digital blocks? A direct digital implementation of this higher order is not possible, so tricks are needed to realize higher order noise shaping.
In [10], two tricks are given. One trick is to approximate the second-order pulse-shaping with a weighted sum of delayed samples. An other trick is to cascade two or more single stage VCO ADCs. This work will focus on the latter.
2.4
MASH structures
In [11], a solution was found to create higher order stable Σ∆ modulators by cascading stable first-order Σ∆ modulators. They called this structure a MASH. Today, stable third-order Σ∆ modulators have already been implemented directly, but this technique could be useful for open-loop VCO ADCs, because first-order VCO ADCs can be made, but implementing a higher order directly seems impossible.
The key to MASH is to extract the error or added noise generated by sampling but without noise-shaping. In equation 2.8, this error would be Mal(z).
2.4. MASH STRUCTURES 13
A theoretical model of a 1-1 MASH VCO ADC is presented in figure 2.12. The extracted error signal E can be described by equation 2.10 with U1,LF = X+MsT1,LFs and U1,HF = MsT s1,HF.
At low frequencies, HZOH will be approximately 1 and the error signal can be simplified.
E = U1,LF + U1,HF − [U1,LF]∗HZOH− U1,alHZOH
⇒ELF ≈ −U1,al (2.10)
Now, ELF can be the input of the second first-order VCO ADC. The high-frequency
component can be ignored. Its effect can be added in the already unknown M2,HF. The two
MASH outputs are put in equation 2.11.
Y1(z) = [ST F X(s)]∗+ [ST F M1,LF(s)]∗+ 1 − z−1 U1,al(z)
Y2(z) = [ST F (−U1,al)]∗+ [ST F M2,LF(s)]∗+ 1 − z−1 U2,al(z)
(2.11)
By analyzing equation 2.11, the ideal way to combine both MASH outputs is to take the first output, Y1 and sum it with 1 − z−1 Y2(z), so that the U1,al component in the two
equations cancels out. 1 − z−1 is called the noise cancellation filter, NCF.
In the signal band, ST F ≈ 1 so that the total output can be simplified as in equation 2.12. Note that the second stage adds its own fundamental PFM encoding error. But lets assume that VCO ADC stages with a very small MLF were chosen, so that this error can be
neglected for a moment.
Y (z) = Y1(z) + 1 − z−1 Y2(z)
≈ [X(s)]∗+ [M1,LF]∗+ 1 − z−1 [M2,LF(s)]∗+ 1 − z−1
2
U2,al(z)
(2.12)
Starting from the signals in a first-order VCO ADC as in figure 2.10, the wanted outputs of the first MASH stage can be constructed. A time-domain plot of the outputs of the first stage in the MASH is presented in figure 2.13.
2.4. MASH STRUCTURES 14
Figure 2.13: Example of the wanted output waves of the 1-bit reset counter in the first VCO ADC stages in a MASH when triggering on both rising and falling edges.
By using VCO ADCs in a MASH structure, higher order noise shaping can be realized. Now that the theoretical basis is out of the way, the first-order VCO ADC and MASH VCO ADC can be modeled on a system level to get a better view of possible non-idealities and to find VCO parameters that will result in good performance.
Chapter 3
System-level modeling
To get a better understanding of the VCO ADC, a system-level model for the device can be designed and simulated. This model will be made using MATLAB Simulink. It is based on the theory of the previous section and is first made as an ideal system. Once this ideal model is simulated, non-idealities that are expected to come up when implementing the system in practice can be added and their effect can be analyzed.
The system-level models can also be used to find the best parameters for the VCO ADC components. These will be normalized with respect to fs, as fs is a technology-dependent
parameter.
3.1
First-order VCO-ADCs
The basis of a good VCO ADC MASH is a good first order VCO ADC that is fit for cascading. So the first step for making a good MASH model is to make a good first-order VCO ADC.
First, a VCO ADC that uses only a single VCO phase is designed. The top-level model is drawn in figure 3.1. It consists of a VCO (figure 3.2) that is made to output four phases. This amount was chosen arbitrarily. It shows how the VCO model can output more phases.
It also contains a 1-bit reset-counter (figure 3.3). This reset-counter is the block that realizes the edge-detection and first-order pulse-shaping simultaneously. The output of this circuit is the same as in figure 2.10.
3.1. FIRST-ORDER VCO-ADCS 16
Figure 3.1: Simulink model for the full single-phase first-order VCO ADC
Figure 3.2: Simulink model for the VCO
3.1. FIRST-ORDER VCO-ADCS 17
The output spectrum is presented in figure 3.4. How the spectrum was obtained is ex-plained in appendix A. DC was averaged out and the magnitude is presented in dBc to make it easier to estimate the SQNR over a certain bandwidth at first glance.
The VCO ADC does not seem to perform that well. The SQNR over the bandwidth of fs/64 is about 53 dBc. First-order noise-shaping is present, but not that pronounced. Since
only one phase was used, the tails of the first PFM sidelobes could be close to the desired signal bandwidth. In other words, for this model, the performance is probably mostly limited by the fundamental PFM encoding error. Evaluating equation 2.6 with the used parameters for different fx in the bandwidth results in figure 3.5.
When comparing figure 3.5 with figure 3.4, it is clear that a better VCO ADC is needed, because the performance of the single phase VCO ADC has about reached the fundamental SQNR. As such, using this VCO ADC in a MASH will result in a worse VCO ADC than using it on its own as the fundamental PFM encoding error of the second stage would be added and the fundamental encoding error will most likely overpower the second-order noise-shaped aliasing error.
Figure 3.4: Output spectrum for the single-phase first-order VCO ADC model with BW = 1/64fs, f0 = fs/4.01, KV CO = fs/4.01, fx = fs/128 and A = 0.4. The SQNR over the chosen
3.1. FIRST-ORDER VCO-ADCS 18
Figure 3.5: Fundamental PFM encoding error with the same paramters as in figure for different input frequencies. The red dot indicates fx = fs/128 for BW = fs/64.
Luckily, the VCO model was made to be easily expanded to output more phases. From now on, the VCO ADC models used will be generated by a script which allows to choose the amount of used phases.
3.1.1 Effect of the amount of VCO phases
In figure 3.6, the results of simulating the same VCO ADC structure but with different amount of phase taps is plotted.
3.1. FIRST-ORDER VCO-ADCS 19
This plot can be split up in two by visually looking for the average SQNR over some number of phases. In the first part (roughly from single-phase to 20 phases), the fundamental PFM encoding error is dominant and the SQNR increases significantly with the amount of phases used. After that, the aliasing error will become dominant. Increasing the amount of phases further will still have a positive effect on the performance on average, because the effective frequency will increase and the pulse-shaping filter attenuates more for higher frequencies.
The irregularity of the plot is a result of the modulation sidebands moving when changing the amount of phases used. If M phases are used, f0 in the PFM spectrum changes to M f0.
So, sometimes this “new” f0 will be closer to fsfor the first, dominant modulation sidebands,
and sometimes farther. As such, the attenuation (caused by notches in the pulse-shaping filter at multiples of fs, as can be seen on figure 2.7) of the modulation sidebands change
which affects the performance.
For figure 3.7, f0 was changed to fs/5.01. This different ratio between fs and f0 results
in a different pattern. The overall SQNR for this value of f0 is lower than for f0 = fs/4.01,
because the latter is bigger, so the latter is preferred for the next parts.
Figure 3.7: Same plot as in figure 3.6, but with f0 = fs/5.01 and KV CO = fs/5.01.
Due to the way that the VCO will be designed later, an even amount of phases is preferred. From figure 3.6, 30 phases seems a good amount. It has the highest SQNR for an even amount of phases in the sweep range. The output spectrum of a 30-phase single stage VCO ADC is plotted in figure 3.8.
3.2. VCO-ADC MASH 20
Figure 3.8: Output spectrum of the 30 phase single stage VCO ADC with the same param-eters as in figure 3.4. The SQNR over the bandwidth is 75 dBc.
3.2
VCO-ADC MASH
One of the most important parts of the VCO ADC MASH is the generation of the error signal. The pulse-shaping block used in the first-order VCO ADC of the previous section needs to be adjusted to also output an error signal. For this, an other way of realizing the sampling, quantizing and pulse-shaping was used. The model can be seen in figure 3.9. The outputs should look like the waves in figure 2.13.
The problem with this realization however is that the flip-flops in MATLAB Simulink have zero propagation delay, so that when the output of the first flip-flop changes, the output of the second one changes as well and simultaneously. To counteract this quirk of MATLAB Simulink a very small delay is added between the two flip-flops.
The combination of Y1 and Y2, where Y2 is differentiated first, is done in the wrapping
MATLAB script outside Simulink.
The output signal of the single stage multiphase VCO ADC is the addition of the bits from the different VCO phases. As a result, this signal is an integer with a minimum of 0 and a maximum equal to the amount of summed phases. In the theory, and in the model for the single stage, the input was assumed to go from −A to +A. So scaling of either the error signal, or f0 and KV CO of the second stage is needed to make the model work.
In figure 3.10, the output spectrum of an ideal VCO ADC MASH is plotted on top of the spectrum for one stage. The model of the MASH made with two 30 phase single-stage VCO ADCs of the previous section, where the rstCntr block is replaced with the model from figure 3.9. As expected, second order noise shaping can be observed.
3.2. VCO-ADC MASH 21
Figure 3.9: Simulink model for the quantization block with error generation.
Figure 3.10: Output spectrum of the VCO ADC MASH (in red) on top of the spectrum from figure 3.8. Again, the same parameters are used. The SQNR over the bandwidth is 96 dBc
3.2. VCO-ADC MASH 22
Now, the model can be adjusted to add some expected deviations from the ideal so that their effect can be analyzed. After that, a final sweep over f0 and KV CO values for the VCO
can be done to find which values result in acceptable or good performance.
3.2.1 Effect of a VCO gain offset
One of the non-idealities is the VCO gain offset. When the VCO parameters of the second VCO are not matched with those of the first, U1,al from equation 2.11 might reappear in the
output spectrum, resulting in a noise-spectrum that shows first-order noise-shaping for low frequencies. For high frequencies, the second-order noise-shaping becomes dominant. Figure 3.11 compares the output spectrum of the ideal VCO ADC MASH with a MASH with a 20% mismatch between the parameters of the two VCOs.
Figure 3.11: Comparison of an Ideal MASH (grey) with a MASH that has a VCO offset of 20% (red). The SQNR dropped 5 dB.
Because this offset results in first-order noise-shaping for the lower frequencies in the spectrum, it is most problematic when a high oversampling rate is used. In the earlier example, the effect does not degrade the performance that much because the part of the output noise spectrum that has second-order noise-shaping is already dominant for the frequencies close to the bandwidth.
A sweep over multiple gain offsets is done to visualize how the SQNR changes with the offset. For this, the bandwidth and input frequency were both halved to give a worse case sce-nario than for the previous parameters. Figure 3.11 is remade with these different parameters in figure 3.12. The result can be seen in figure 3.13.
3.2. VCO-ADC MASH 23
Figure 3.12: Simulation for the same offset as in figure 3.11 but for the values of fx and
BW that are used in the offset sweep from figure 3.13.
Figure 3.13: Plot of the MASH SQNR versus the VCO gain offset. The bandwidth and input frequency were both halved compared to the previous simulations to better visualize the effect.
3.2. VCO-ADC MASH 24
3.2.2 Effect of delay between stages
Since the VCO ADC MASH will operate at quite a high frequency, some kind of delay could appear between the two stages. Will this negatively effect the performance of the VCO ADC? This effect can quickly be added to the model by simply adding an extra delay block between the two stages.
When sweeping over different delay values, as presented in figure 3.14, it can be observed that the delay does not affect the performance nearly as much as the gain offset did.
Figure 3.14: Sweep over different delay times between the two MASH stages. The difference between this effect and the offset effect can be understood by looking at equations 2.11 and 2.12. The offset error makes it so that the first-order shaped quantization error of the first stage does not cancel out so that it is present in the output as first-order shaped noise, the delay effect, however, will shape this error. A delay of τ in the time domain is a multiplication with exp (−jωτ ). So where a simple offset would result in an extra term of the form (1−α)(1−z−1)U1,al(z) where α is a constant that represent the second VCO’s gain offset,
a delay between stages would result in a term of the form [1 − exp(−jsτ )]∗(1 − z−1)U1,al(z).
Plotting this effect on its own gives figure 3.15.
So the quantization noise of the first stage will become present in the output signal, but it is shaped in a way that makes it less problematic for the performance. This can be observed in figure 3.16, in which a delay of 0.55Ts is compared with a delay of 10Ts. The latter is a
value that is a bit extreme, but for this value, the effect of U1,al(z) can be seen as the spectrum
3.2. VCO-ADC MASH 25
Figure 3.15: Plot of the extra shaping caused by the delay effect
(a) Spectrum for τ = 0.55Ts (b) Spectrum for τ = 10Ts
Figure 3.16: Output spectra for different delays between the two MASH stages compared with the output spectrum of the ideal VCO ADC MASH.
3.2. VCO-ADC MASH 26
3.2.3 Effect of limited rise and fall time between stages
Since the output of the error-generation of the first MASH stage is digital, the second VCO is implemented as a DCO. When limiting the rise and fall time of the error signal pulses, some of the narrower pulses could disappear when they don’t reach the threshold to be registered by at this DCO’s input. This limited rise and fall time could be the result of parasitic capacitances at the input of this DCO. Or it could be present earlier, inside the pulse-shaping filter for example.
The model is adjusted as shown in figure 3.17 to simulate this effect. In the reset counter block, a Simulink slew-rate block is placed after the error generation. This block uses the parameter SR to represent the slewrate. It is the maximum change in signal during a sampling period. It is then checked whether the error signal is bigger than 0.5 to model the input threshold of the second stage.
Figure 3.17: Simulink model for the error generating reset counter adjusted to model slew-ing.
Figure 3.18 shows how the SQNR for a sweep of slew-rate values. For high values of SR, the SQNR flattens out which was to be expected. For lower values, the SQNR lowers with increasing rate-limit or decreasing SR untill it reaches a minimum in 1. After that, the SQNR seems to rise again.
To understand this strange trend, the spectra are analysed. When plotting the error signal in the frequency domain for SR = 20 (figure 3.19a) and SR = 1 (figure 3.19b), it can be seen that for SR = 1 harmonics seem to be added to the error signal.
3.2. VCO-ADC MASH 27
Figure 3.18: Sweep for different values of SR. The VCO ADC parameters are chosen the same as for figure 3.8.
(a) SR = 20 (b) SR = 1
3.2. VCO-ADC MASH 28
When looking at the output spectra and comparing SR = 20 (figure 3.20a), SR = 1 (figure 3.20b) and SR = 0.4 (figure 3.20c), figure 3.18 can be better understood: For SR decreasing towards 1, harmonics in the error signal negatively affect the SQNR. For lower SR, the error signal starts disappearing completely as more and more error pulses can’t reach the threshold untill none of the pulses can. As a consequence, the MASH output shows first-order noise-shaping without the harmonics that further deteriorate the performance.
(a) SR = 20 (b) SR = 1
(c) SR = 0.4
Figure 3.20: Output spectra for different values of SR.
3.2.4 Ideal VCO parameters
The findings from previous sections give an idea about how the performance of an implemented MASH might differ from the ideal MASH. But before transitioning to the circuit level, the system level models can be used to get an idea about the best VCO parameters for a VCO MASH. A good value for the number VCO of phases was already found in section 3.1.1. But what about f0 and KV CO?
3.2. VCO-ADC MASH 29
From section 2.2, it is clear that it is not that straight-forward to obtain the ideal VCO frequency gain (KV CO). When KV CO is increased, the peak at fx in the output spectrum
will be more present. The higher frequency swing results in a stronger base-tone. However, this higher swing will also increase the danger to violate the oscillation condition as presented in equation 2.9. A higher KV CO will also result in wider modulation sidebands in the PFM
spectrum which in turn results in a heavier aliasing error.
The condition of equation 2.9 needs to be taken into account for the choice of f0 as well. A
higher f0does result in a higher fundamental SQNR and sidebands that are more attenuated.
So it can’t be chosen too low when optimizing the performance.
The heatmap plot in figure 3.21 is used to represent the relation between these VCO parameters and the performance.
Figure 3.21: Sweep over f0 and KV CO values for both VCOs in the VCO ADC MASH
model. N (from appendix A) was chosen 212so the SQNR might deviate a bit from the SQNR values found earlier.
From the plot it can be seen that it is important to keep KV CO small. KV CO should best
be chosen smaller than 0.35fs. Depending on the choice for f0, the best KV CO can range
from 0.1fs to 0.3fs. As reasoned earlier, f0 can’t be chosen too small, Taking a f0 between
0.2fs and 0.3fs would be a good choice. The previous choice of f0 = 0.25fs would be a good
Chapter 4
Circuit-level design
To get a better idea of how the VCO ADC MASH will perform in reality, the system will be implemented and simulated in TSMC’s 28 nm technology.
The chapter is seperated in different sections each about a part of the circuit. Starting at the analog input, there is the VCO, which is a voltage-controlled ring oscillator or VCRO. After that, the output waveform of the VCRO is the input of the digital 1-bit reset counter which is built with XOR-gates and edge-triggered D flip-flops.
The VCRO and 1-bit reset counter together can form a single-stage VCO-based ADC. In chapter 3, it was concluded from system level simulations that using 30 VCO output phases is expected to generate good results. The same amount of phases will be used in the circuit level too. As such, the digital output of the reset counter is encoded in 30 bits with equal weight (a thermometer-like encoded signal, which can be represented with 5 binary encoded bits). It also outputs a digital error signal which is encoded in the same way.
The second stage does not start with a VCRO, but with a DCO with these bits as input. After the DCO of the second stage, the same 1-bit reset counter designed for the first stage can be used.
4.1
The VCRO
As mentioned in chapter 1, a highly-linear VCRO architecture will be used. The architecture used will be that of [9]. This is a pseudo-differential VCRO design in which a resistive network will be used to tune the VCO output frequency, which results in high linearity as found in [8]. The auxiliary inverters used in [8] to align the edges of the main inverters, are replaced with pre-charge inverters in [9], which accomplish the same thing but with less of a performance hit.
4.1. THE VCRO 31
Figure 4.1: Schematic for the VCRO
Figure 4.1 shows how the delay cells are connected and how each of them is constructed. Each delay cell consists of a total of four inverters; Two inverters are needed for the buffer, drawn on the top of the delay cell in figure 4.1 and separately in figure 4.3. One inverter acts as the pre-charge inverter, drawn in the middle in figure 4.1. The bottom inverter is the main ring inverter.
Figure 4.2: Schematic for the VCRO delay element
As found in [9], the pre-charge and main ring inverters can be sized with the same widths. The width of these inverters will affect the delay of the delay cell and hence the VCO free-running frequency (f0), and the VCO frequency gain (KV CO). The inverter is sized to be
symmetric, so the width of the PMOS is twice that of the NMOS to account for the mobility difference between holes and electrons. The width of the NMOS transistors in these inverters will be denoted with M when comparing different sizings further on. The length is sized to the minimum length.
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Figure 4.3: Schematic for the VCRO output buffer
Because the sources of the NMOS transistors in the ring are not at 0 V but at the control voltage, the block wave goes from Vctrl to 900 mV, where Vctrl changes with Vin. To act on
this, the first inverters of the buffers are asymmetrically sized and made with transistors with different threshold voltages in such a way that the switching voltage of the inverters is shifted higher than 450 mV. This way, the output will go full-swing between ground and supply, while the inverter switches at about half the swing of the internal block wave.
In figure 4.3, the buffer circuit is drawn. The width of the first inverter’s NMOS will be denoted with Mbuffer when comparing different sizings further on. Because this buffer is
connected at each of the VCO phases, it adds to the load capacitance of each delay cell and changes the propagation delay of the cells as a consequence. So this Mbuffer will also affect f0
and KV CO.
In figure 4.4, this difference between the voltage transfer characteristic of a symmetrically sized inverter and an inverter with the asymmetry of figure 4.3 is shown.
4.1. THE VCRO 33
Figure 4.4: Comparison between a symmetrically sized inverter and an asymmetrically sized inverter. Both have a minimally sized NMOS.
The delay of the delay-cells is manipulated with a combination of current and voltage steering which is realized with the resistor circuit drawn in figure 4.5. The sizing of R1 and
R2 will affect the noise-performance and linearity of the VCO as well as KV CO and to a
lesser degree f0. By adjusting the relation between R1 and R2, the swing of Vctrl can be
adjusted. Vctrl will not change linearly with Vin as in a normal voltage divider because the
VCO impedance changes with changing Vctrl. As such, it is not possible or feasible to find
an analytical expression for the change in control voltage depending on the input voltage and resistor sizings. This has to be done numerically.
Figure 4.5: Schematic for the VCRO steering
Higher resistance will result in more thermal noise at the input, which will be integrated by the VCO operation to phase-noise at the output. The sizing of the resistors will also affect the non-linearity of the VCO operation. So different resistor sizings can result in very different results.
4.1. THE VCRO 34
4.1.1 Sizing and simulation results
The transistor channel lengths were kept on the minimal size of 30 nm. These inverters need to be sized in such a way that f0 and KV CO are close enough to fs/4 for fs equal to 8 GHz.
When increasing the channel width, f0 and KV CO decrease more or less simultaneously.
The resistor sizing in the steering network also affect the VCO parameters. If R2 is sized
bigger than R1, the voltage range of Vctrl will be bigger than if R2 and R1 are sized more
equal. Changing this swing will change KV CO to a greater extend than f0. Adjusting the
resistors will change the current through the VCO so it doesn’t exclusively affect KV CO, but
it is a way to change the difference between f0 and KV CO ∗ 1V , though there is no clear
analytical relation between the resistor sizings and the VCO parameters.
Based on circuit level simulations for different steering networks, it was concluded that an f0more or less equal to KV COis reached when R1 is about twice as big as R2when f0 is close
to fs/8 for a sample frequency of 8 GHz. The value of this R2 can then be sized by finding a
balance between non-linearity and phase noise. Still, when changing R2, slight adjustments
of the resistor ratio might still be needed. VCO parameters
When choosing R2 equal to 600 Ω and R1to 1.5 kΩ, Vctrlwill show the characteristic presented
in figure 4.6. For these simulations, Mring was chosen to be 800 nm and Mbuffer 600 nm. The
output frequency will evolve very linear with respect to the input voltage as can be seen in figure 4.7. The middle point, where in this case Vin equals 450 mV, has a frequency of
2.383 GHz. This is f0. The slope of this curve is on average −1.775 GHz V−1. This is KV CO.
Note that the VCO is not simulated for an input voltage of 900 mV. This is because for input voltages close to the supply voltage, there is no oscillation visible at the output. As discussed earlier, the low voltage of the internal square wave is Vctrl. For the highest input
voltages, Vctrl will move above the switching threshold of the first buffer inverter. So even
though the square wave inside the ring oscillates, the signal remains above the switching threshold and no oscillation can be seen at the inverter output.
A decent swing is still obtainable. If full swing is needed, the asymmetry of the first inverter needs to be more extreme by mismatching the NMOS and PMOS width more or by choosing ulvt and uhvt MOSFETs. The latter might increase leakage currents however.
Another important parameter is the static power consumption. This is the average power drawn out of the sources and should be as minimal as possible. For this sizing it is 779.8µW.
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Figure 4.6: Vctrl in function of Vin for R1 = 1.5 kΩ and R2= 600 Ω
4.1. THE VCRO 36
The effect that the resistor values have on the output frequency characteristic for fixed inverter sizing can be seen by resizing and re-simulating this VCO for different values of R1
and R2. The results in figure 4.8 compare the VCO output characteristic for different resistor
values when Mring is 800 nm and Mbuffer is 600 nm. The VCO parameters are presented in
table 4.1. Figure 4.9 compares the output characteristic for different resistor values when Mring is 1000 nm and Mbuffer is 100 nm. The parameters can be compared in table 4.2.
Figure 4.8: Effect of resistor sizing on the VCO frequency output when Mring is 800 nm and
Mbuffer is 600 nm.
Figure 4.9: Effect of resistor sizing on the VCO frequency output when Mring is 1000 nm
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KVCO f0 Pstatic
R1 = 1.5 kΩ, R2 = 600 Ω −1.775 GHz V−1 2.383 GHz 779.8µW
R1 = 600 Ω, R2 = 600 Ω −2.832 GHz V−1 3.698 GHz 563.6µW
R1 = 3 kΩ, R2 = 1.2 kΩ −1.462 GHz V−1 2.061 GHz 894.3µW
Table 4.1: comparison of the VCO parameters for different resistor sizings when Mring is
800 nm and Mbuf f er is 600 nm. KVCO f0 Pstatic R1 = 1.5 kΩ, R2 = 600 Ω −1.9042 GHz V−1 2.69 GHz 727.6µW R1 = 750 Ω, R2 = 300 Ω −2.8793 GHz V−1 3.86 GHz 1095µW R1 = 1.5 kΩ, R2 = 400 Ω −1.6861 GHz V−1 3.453 GHz 962.5µW R1 = 2 kΩ, R2 = 800 Ω −1.5746 GHz V−1 2.273 GHz 607.1µW R1 = 2 kΩ, R2 = 1 kΩ −1.6573 GHz V−1 1.962 GHz 521.5µW
Table 4.2: comparison of the VCO parameters for different resistor sizings when Mring is
1000 nm and Mbuf f er is 100 nm.
When keeping the resistor values fixed on R1 = 1.5 kΩ and R2 = 600 Ω, the effect of
inverter sizings on the output frequencies can be investigated. The output characteristics for different transistor sizings are compared in figure 4.10. Numerical values for power consump-tion and VCO parameters are compared in table 4.3.
From these results it can be concluded that f0 and KV CO will decrease for increasing
widths because of the increasing load capacitance for each inverter, which results in a bigger propagation delay per cell.
Increasing the width of the transistors in the first buffer stage has a greater effect on this. By making the ring inverters bigger, their drive strength increases too, which lowers the propagation delay, but in total, increased inverter width inside the ring will still result in lower output frequencies. But if the buffer sizes are increased, only the load capacitance is increased resulting in a bigger net increase of propagation delay.
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Figure 4.10: Effect of transistor sizing in buffer or ring inverters on output frequencies
KVCO f0 Pstatic Mring = 800 nm, Mbuffer = 600 nm −1.775 GHz V−1 2.383 GHz 779.8µW Mring = 400 nm, Mbuffer = 200 nm −2.832 GHz V−1 3.698 GHz 563.6µW Mring = 1000 nm, Mbuffer = 800 nm −1.462 GHz V−1 2.061 GHz 894.3µW Mring = 1000 nm, Mbuffer = 200 nm −1.897 GHz V−1 2.719 GHz 679.3µW Mring = 800 nm, Mbuffer = 100 nm −2.1544 GHz V−1 2.979 GHz 717.6µW Mring = 1000 nm, Mbuffer = 100 nm −1.9062 GHz V−1 2.69 GHz 727.6µW Mring = 900 nm, Mbuffer = 100 nm −2.0159 GHz V−1 2.818 GHz 722.2µW
