Cryogenic Low Noise Ampliﬁer for Noise Spectroscopy in Scanning Tunnelling Microscopy

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Cryogenic Low Noise Amplifier

for Noise Spectroscopy in Scanning

Tunnelling Microscopy

THESIS

submitted in partial fulfillment of the requirements for the degree of

MASTER OF SCIENCE

in

PHYSICS

Author : Corn´e Koks

Student ID : 2071541

Supervisor : Dr. Milan P. Allan

2ndcorrector : Prof. Dr. Jan M. van Ruitenbeek Leiden, The Netherlands, January 23, 2019

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Cryogenic Low Noise Amplifier

for Noise Spectroscopy in Scanning

Tunnelling Microscopy

Corn´e Koks

Huygens-Kamerlingh Onnes Laboratorium, Universiteit Leiden P.O. Box 9500, 2300 RA Leiden, The Netherlands

January 23, 2019

Abstract

The low noise amplifier from Bastiaans et al. [1] is improved by increasing the bandwidth, such that measurement time is reduced. Instead of a single common-source transistor, a cascode setup is used. A

common-source is followed by a common-gate which is followed by a common-drain. The gain (V/V) of the amplifier is estimated to be 22. The

cascoding reduces the miller capacitance from 22pF to approximately 2pF. The input noise current is estimated to be 19fA/√Hz and the voltage noise 0.2nV/√Hz. The power dissipation is estimated at 2mW.

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Chapter

1

Introduction

1.1 Shot noise

Usual Scanning Tunneling Microscopy (STM) measurements are used for example to measure the pair breaking gap in supercondutors. This is done by measuring the current as a function of the bias voltage, where is lat-ter is varied. The conductance as a function of bias voltage is related to the density of states. This technique is called Spectrospopic Imaging STM (SI-STM). High frequency fluctuations in the current are averaged out. However, these fluctuations contain information. For example, shot noise measurements contain information about the charge of the charge carriers. This technique is called Local-Noise Spectroscopy (LNS).

Using LNS, one can measure the charge of quasi-particles. If electrons tunnel randomly, the noise is called poissonian. In some exotic mesoscopic systems, the noise can be superpoissonian, which for instance Andreev re-flections in superconductivity where two or more electrons are clustered [2]. Suppossionian noise means that charge carriers of less than one elec-tron can tunnel [3][4]. With the first generation of cryogenic Low Noise Amplifier (cryo-LNA), charge trapping in the c-axis of BSSCO is measured [5]. Fano factors more than 30 are measured, which indicates that the c-axis is truly insulating, despite its zero resistivity below the critical tem-perature.

1.2 Cryogenic amplifier

In the past, cryogenic Low Noise Amplifiers (cryo-LNAs) have been pro-posed for STM measurements [6] or measuring Shot Noise [7] in

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meso-scopic systems. The noise power is given by SSN = 2qI. In typical STM measurements, shot noise is in the order of 1fA/√Hz. Measuring this is a challenge, because the other noise sources need to be suppressed as much as possible.

To reduce the effect of the 1/f noise, a LC resonator has been proposed by DiCarlo et al. [8], on which the circuits of Bastiaans et al. [1] and Massee et al. [9] are based. The noise from the transistor is also of im-portance. Most commonly, commercial Avago Technology High Electron Mobility Transistors (HEMTs) are used because they are cheap and work at low temperatures [8][10][11][12]. Other transistors are also available which have much better noise characteristics [13].

Another point of interest for amplifiers is increasing the Gain Band-Width product (GBW). As described by Analui et al. [14], the largest GBW for transimpedance amplifiers is achieved by reducing the capacitance. This reduction of capacitance can be done using bootstrapping with posi-tive feedback [15][16] or using cascoded design. Cascoding is an old and common technique, first proposed for in vacuum tubes by Hunt and Hick-man [17] in 1939. It is often used in all types of circuits, for instance in cryo-LNAs [11][12][18]. This report focussus mainly on these two concepts.

A technique commonly used for on-chip transport measurements (quan-tum dots, break junctions) is impedance matching [19] [20], where the impedance of a junction is transformed to the 50Ω impedance of the coax cable. For STM, the junction impedance (100MΩ) is much larger than for quantum dots (<1MΩ) which makes it a challenge. An attempt for impedance matching in STM have been done by Kamiktarak et al. [21]. Impedance matching is most useful for reflectance measurements, such that junction impedance can be measured rapidly. However, for shot noise measurements, it is less useful. This is therefore not covered in this report.

1.3 Outline

In the theory section, the noise sources are described in more detail. Then, the key concept of this report, the LC resonator is described extensively. Finally some basics concepts in electronics are given, among which tran-sistor setups and impedance matching.

The third chapter describes the ideas stated above in more detail, to-gether with analytic derivations and simulations to show their expected performance. Cascoding and bootstrapping are covered in most detail, since those are the most extensively tested concepts. The use of a switch is described in less detail.

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1.3 Outline 3

The fourth chapter is devoted to describe the details of the circuit which is used eventually, together with some drawings of the implementation of the circuit in the STM.

The fifth chapter describes the results of the tests on cascoding and bootstrapping. The sixth chapter would show the results of the cryogenic tests of the final amplifier. Unfortunatly, the amplifier is still under con-struction, so only estimations of the performance are given.

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Chapter

2

Theory

This chapter first describes various noise sources. Then, the LC resonator is described. Then, some concepts in electronics are described, among which that transistor setups, impedance matching and the Barkhausen sta-bility criterion.

Figure 2.1:The approximate current noise power is given below. The 1/f noise is a rough estimate, based on mechanical vibrations and voltage noise in the tran-sistor. The cut-off of the 1/f noise is where the transistor voltage noise becomes predominantly white. The shot noise is based on a current of 100mA and poisso-nian noise. The thermal noise is based on a real impedance of 500kΩ. The HEMT current noise is 2.2fA/√Hz.

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2.1 Noise

The shot noise, thermal noise, 1/f noise and transistor noise sources are described.

Figure 2.1 gives an approximate noise power for each noise source. The 1/f noise is a rough estimate of the mechanical and transistor noise. The figure shows that from about 100kHz, the 1/f becomes small. This is thus the preferred region of doing the measurements. Note that the thermal noise is the dominant noise source in the setup.

2.1.1 Shot noise

The equation for shot noise is given by

S=2|q|hIiF, (2.1)

where q indicates the effective charge and F indicates the Fano factor. For transport measurements, this Fano factor is given by

F= ∑nTn(1−Tn)

∑nTn . (2.2)

The full derivation is given in appendix A.1. Here, the Landauer approach is used, where single charge carriers have a finite probability for transmit-ting or reflectransmit-ting through the barrier. For STM measurements, Tn →0 and thus F≈1.

An increase in shot noise, compared to normal metals can still be ob-served in STM. This because of an increase in effective charge. Cooper pairs have|q| = 2e so that noise would double. Andreev reflections for STS junctions can give even high order of noise increment, i.e. |q| = ne for some positive integer n.

2.1.2 Thermal noise

Thermal noise originates from the thermal equilibrium of two element, derived by Johnson and Nyquist [22]. Important is that only dissipative elements produce thermal noise, i.e.

S=4kbTRe[Z]. (2.3)

Imaginary parts do no contribute. This is important, because if the abso-lute value is considered, the sides bands of a LC-resonator would give an overestimation of the thermal noise.

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2.2 LC resonator 7

Massee et al. [9], who have developed a circuit similar to Bastiaans et al. [1], report a thermal noise value of S = 4kbT|Z|max. For the LC res-onator used in their circuit, this suggests a noise of S = 4kbTω

2 resL2+R2

R .

When the real value is considered, the thermal noise is given by S = 4kbT_ω2 ωR

resL2+R2|Z(ω)|

2_{. The therm in the fraction does not change munch} around the resonance frequency, but the impedance, |Z(ω)|does change

significantly. Away from the resonance frequency it is thus important to consider the real part instead of the maximum impedance. More details are described in section 2.2 and appendix A.2.

2.1.3 1/f noise

Flicker noise is a general concept which is also applied to for instance earthquakes of the stock exchange. Key is that large events happen rarely and smalls event occur more frequently. For instance, in a semiconductor device there are many small traps, but a few large ones. The 1/f noise of the transistor is not of much relevance at 3MHz, since it is dominated by the white noise sources of the transistor, as shown in figure 2.1.

2.1.4 Transistor noise

The transistor noise is modelled as a voltage and current noise at the gate. Dong et al. [13] have fabricated a HEMT with much better noise character-istics than commercial HEMTs. One major noise factor is due to inelastic scattering, given by Strv =

F2eIds

g2m . From this one can see that reduction of impurities (Tn → 1) reduce the noise of the transistor. This is dong by using Molecular Beam Epitaxy (MBE) growth.

Typical values for the transistor from Dong et al. [13] are a current noise of 2.2fA/√Hz and a volage noise of 0.2nV/√Hz. These values are reported in appendix C. From Zavjalov [11] et al. the current noise for a commercial transistor (ATF33143) is 11.8fA/√Hz and voltage noise of 1.3nV/√Hz.

2.2 LC resonator

The key concept of the amplifier is the LC resonator. Its characteristics are over covered in this section. The equivalent circuit is given by figure 2.2.

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Figure 2.2:Equivalent model of LC resonator.

The impedance of this circuit is given by ZLC = (jωC− jωL

ω2L2+R2 +

R

ω2L2+R2)

−1_. _(2.4)

With inductance L, capacitance C and resistance R. For large enough Q-factors, ω2L2 R2, and equation 2.4 can be simplified. Furthermore, one can define the Q-factor as Q= ωL

R . Using this, equation 2.4 becomes ZLC = (jωC− j ωL+ 1 ωLQ) −1_. _(2.5)

2.2.1 Impedance and bandwidth

The Q-factor is defined as

Q = f0

∆ f, (2.6)

which thus contains a definition of bandwidth. The bandwidth∆ f is the Full Width Half Maximum (FWHM) bandwidth. To get more insight into equation 2.4, it is best to normalised it to form

YLC = r C L( jω ω0 − jω0 ω + ω0 ωQ) = q (C L)( jω ω0 − jω0 ω + ∆ω ω ). (2.7)

For ω = ω0+ 1₂∆ω, the admittance becomes YLC = p

(C_L)(j∆ω_ω 0 −

∆ω

ω ).

Here, the real and imaginary part are equal, which indeed corresponds to the−3dB point.

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2.2 LC resonator 9

Thus equation also shows that the maximum impedance is ZLC =

r L

CQ =Qω0L. (2.8)

However the FWHM (∆ω) bandwidth is not useful for our purposes. More useful for a bandwidth is equating this to a certain impedance smaller than Qω0L. A certain impedance ˜Z now defines the bandwidth. This re-quires solving (1 ˜ Z r L C) 2 _{= (} ω ω0 −ω0 ω ) 2_{+ (}∆ω ω ) 2_. _(2.9)

The derivation is given in appendix A.3. The bandwidth is BW =

s 1

(ZC)˜ 2 −∆ω

2 _(2.10)

around the frequency

˜f0= 1 2π s 1 LC + 1 (ZC)˜ 2. (2.11)

The minus sign in 2.10 in front of∆ω2seems counter intuitive. However, a finite Q-factor reduces the impedance of the resonator and thus decreases the bandwidth.

For the amplifier, the SNR is of the form SNR = Si|ZLC|2

Si|ZLC|2+Sv, where Siis the current noise and Sv is the voltage noise. If the impedance, ˜Z2 = S_Sv_v, is defined as the ratio of noises and the maximum impedance, Qω0L is much larger than ˜Z, then the bandwidth, BW, defines the FWHM of the SNR. This is the main figure of merit which needs to be maximised.

2.2.2 Mechanical analog

To get a more intuitive idea, it is useful to convert the electrical circuit to a mechanical analogue. The LC resonator can easily be mapped to a pendulum. By writing the Kirchhof Current Law (KCL), one arrives at

(jwC+ 1 jwL +

R

w2_L2)v=iext (2.12)

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Figure 2.3: Model of some part of transmission line. L0 and C0 denote the induc-tance and capaciinduc-tance per length. vnis the voltages at some each node.

C¨q+ q L +

Z _R

L2qdt= ¨qext. (2.13)

The last equation already looks like a harmonic oscillator with strange damping therm. With the equation of motion for a mass spring system

m¨x+kx+γ ˙x =Fext, (2.14) the capacitance can be mapped to the mass, the inductance to 1_k.

Another interesting point is that the KCL for a transmission line like structure, shown by figure 2.3, is in the mechanical analogue given by

C0q¨i+ 1

L0(2qi−qi−1−qi+1) = 0, (2.15)

where L0and C0are the inductance and capacitance per unit length. Equa-tion 2.15 is equivalent to the of phonons for a 1D piece of material. The characteristic impedance for acoustic waves is given by z =ρvs. The den-sity ρ = Ami

Ab , where b is a lattice vector, mi is the mass of a single atom and A is the perpendicular surface. The velocity of sound is vs = b

q k m. The acoustic impedance is thus z = √km and the electrical analogue is Y =

q C0

L0. This is not the electrical impedance, but the admittance. As described later in 2.4, the reflectance is given byΓ = ZL−Z0

ZL+Z0. In therms of admittance, it is equal apart from a sign change: Γ = −YL−Y0

YL+Y0

∗_{. A typical} coaxial cable has

q L0

C0 =Z0=50Ω as a characteristic impedance.

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2.3 Transistor setups 11

2.3 Transistor setups

A transistor can be considered as a three port device; gate, drain and source. In practise, two ports act as in- and output for the signal, while the third is grounded for AC signal. The part which is AC grounded is called common X (it is not necessarily grounded, but in practise this is most commonly done). In the following subsections, their simplistic mod-els are given, together with key equations. Important to keep in mind is that the gate is not completely disconnected from the drain and source. There is a gate-source and gate-drain capacitance of typically a few pico-farad, which influences the input impedance. † In the following figures and equations, vg,vs and vd indicate the gate, source and drain voltage (AC). CGDand CGSare the gate-drain and gate-source capacitance respec-tively. gm is the transconductance, which determines alternating current in the modelled current source as i =gm(vg−vs).

Figure 2.4: Equivalent circuit of CD transistor. Vg is the input voltage, Vsis the

output voltage.

When mapping to a different system, switching from admittance to impedance of v.v. does not matter for waveguides.

†_{From the key equation for MOSFET transistors: I}

DS = 12µCoxWL(VGS−Vthr)2and

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2.3.1 Common drain

The common drain (CD or source follower) amplifies signals from the gate towards the source. Its equivivalent circuit is given in figure 2.4. This amplification is given by

A= vs vg

= Rs

rm+Rs, (2.16)

where rm = _g1_m. The AC current through the transistor is determined by the difference between gate and source voltage. The source voltage is thus vs =Rsgm(vg−vs)which solves to equation 2.16. The input impedance is given by

Z =Zin||

1

jωCgd+jωCgs(1−_r_mR₊s_R_s)

. (2.17)

Where ||indicates a parallel configuration, i.e. a||b = _aab₊_b. Note that the gate-source capacitance is effectively reduced, because the voltage at the gate and the source are proportional and in phase with each other. The drain is grounded, so there is no change there.

Figure 2.5: Equivalent circuit of CS transistor. Vg is the input voltage, VD is the

output voltage. Technically, ro should be connected between vd and vs, but for

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2.3 Transistor setups 13

2.3.2 Common source

The common source (CS) transistor is similar to the CD, except the drain is the output. The output is thus at the other side of the current source resulting into a opposite phase. Solving the equations vs =Rsgm(vg−vs) and vd = (ro||RL)gm(vg−vs)gives the gain equation

A = vd vg

= − ro||rD

rm+Rs. (2.18)

Commonly, the source is grounded which gives a gain of A= −gm(ro||RL). The input impedance is now given by

Z =Zin|| 1

jωCgd(1+_rr_mo||+rRDs) +jωCgs(1−

Rs

rm+Rs)

. (2.19)

The gate-source capacitance is corrected for, like in the CG. The gate-drain capacitance now also has a correction factor, but with an opposite sign. Due to the π-phase difference, the capacitance is effectively enlarged. This is known as the miller effect. This effect can be reduced, as will be de-scribed in section 2.3.4.

Figure 2.6: Equivalent circuit of CG transistor. vsis the input voltage, vd is the

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2.3.3 Common gate

The third type is the common gate. Here the source is the input and the drain is the output. Figure 2.6 shows that the total current through the transistor is given by iDS = gmvs−vd_r−_ovs = _Rvd_L so that the gain is given by

A= vd vs

= (gm+ 1 ro

)RL||ro ≈gm(RL||ro). (2.20) The input impedance can be determined using vs = ro(iDS −gmvs) + iDSRL which is the voltage drop over the load and the internal resistance of the transistor. Together with the capacitors, the input impedance is

Z= Rs|| 1 jωCGS ||(RL|| 1 jωCGD +ro 1+gmro ). (2.21)

The input impedance is approximately Z=rmRL_r+₀r0.

2.3.4 Cascoding

Figure 2.7:The gate voltage is amplified by the first HEMT in the CS setup, which is then amplified by the CG stage. The first stage is assumed to have a small, in this can unity gain. The second stage provides the desired large gain.

Cascoding is an old concept invented in 1939 by Frederick Vinton Hunt and Roger Wayne Hickman [17]. A cascode amplifier has a CD or CS with

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2.4 Impedance matching 15

a CG stacked on it. The CS with CG cascode setup is used to have a re-duced miller effect.

From equation 2.19, the capacitance is effectively enlarged by the gain. The input capacitance is approximately given by

Ctot=CGS+ (A+1)CGD. (2.22)

For large gains, the input capacitance is substantially increased. For a gain of 30 and a gate-drain capacitance of 1pF, the additional capacitance, or miller capacitance, is 30pF. This effect can be reduced by the setup as schematically shown in figure 2.7.

This first stage has a gain of unity. The miller capacitance is thus only 1pF. The common-gate transistor then amplifies the signal. The amplifica-tion is thus ’delayed’ to the second stage.

One needs to take into account an additional noise source in the CG transistor. The gate is grounded, but still contain some noise. This can also be modelled to be a noise source at the source, because only the voltage difference between the source and the gate is of importance. If the gain of the first stage (the CS) is too small, the signal between the two transistors will be dominated by the aforementioned noise. Therefore, a gain of about unity should be chosen.

2.4 Impedance matching

Impedance matching is important when the signals are considered to be waves. The wavelength (in vacuum) is given by λ = c_f, where c, so for 3 MHz, the wavelength is 100m. Typically, for structures l < λ

20, the wave-like behaviour is important.

Key is to maximise the power over the load. If one considers a simple circuit from figure 2.8, the power is given by

P =I2ZL =V2 ZL

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Figure 2.8:Equivalent circuit of impedance matching. Z0indicates the impedance

of a transmission line. ZLis a load impedance.

Maximising this with respect to ZL gives the condition ZL = Z0∗. The impedance of the cable Z0is a constant, most commonly 50Ω.

To appreciate impedance matching better, lets first consider a one port device. In contrast to basic electronics, one has to consider forward and backward moving waves, given by v+ and v− respectively. This gives equations

v++v− =iZL v+−v− =iZ0

(2.24) which gives the reflection coefficient

Γ ≡ v + v− = ZL−Z0 ZL+Z0 . (2.25)

Equations 2.24 look strange, but can be understood by considering ZL to be infinitesimally small and Z0 to be infinitely long. For ideal lumped elements (zero length), the wavelike behaviour does not matter. Therefore, the voltage can be consider to be ”point-like”, i.e. v =v++v−. The coax cable is designed as a wave guide so the wavelike behaviour is crucial This means that the direction of voltage is proportional to the transmitted current, i.e. ˜v=v+−v−.

2.4.1 Finite length transmission line

If the transmission line length is comparable to the wavelength of the volt-age waves, so the equations become more complicated. From an ideal transmission line (no losses), its equations are given by

dv(z, t) = −dzωL0di

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2.5 Barkhausen stability criterion 17

resulting in the wave equations

v(z) =v+exp−jω √ L0_C0_z +v−expjω √ L0_C0_z i(z) =i+exp−jω √ L0_C0_z +i−expjω √ L0_C0_z = v + Z0 exp −jω√L0_C0_z −v − Z0 exp jω√L0_C0_z . (2.27)

The input impedance is given by

Zin(z) = v(z)

i(z) (2.28)

The forward and backward travelling waves are determined by the way the transmission line is terminated. The relation between v+ and v− is given by equation 2.25. The input then becomes

Zin =Z0 ZL−jZ0tan(ω √ L0C0d) Z0−jZLtan(ω √ L0C0d). (2.29)

Where d is the length of the transmission line, Z0 = q

L0

C0 and ZLare again the characteristic impedance of the cable and the load which terminates the cable. Obviously, if the transmission line is terminated with 50Ω, the input impedance is also 50Ω. Also note that for ω√L0_C0_d _{1, the length}

is irrelevant and the impedance is just Zin =ZL.

The unpredictable wavelike behaviour thus does not appear if the cable is much shorted than the wavelength, or if the cable is therminated by 50Ω.

2.5 Barkhausen stability criterion

The Barkhausen stability criterion is an obvious restriction on a feedfor-ward system. It is explained for the Wien bridge in Martinez-Garcia et al. [23] which explains where the Wien bridge forms an oscillator and when it is unstable. The theory holds more generally.

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Figure 2.9:Stability figure of feedforward systems. The input signal arriving from the left gets amplified and voltage divided, such that a signal multiplied with Aβ is added to the input.

Consider a feedforward system as given by figure 2.9, the voltage v0is amplified by a factor A and voltage divided with a factor β (note that both A and β can be functions of frequency. The Barkhausen criterion states that stable oscillations occur if the following two conditions are satisfied

|Aβ| =1

](Aβ) = 0. (2.30)

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Chapter

3

Simulations

In this chapter, first the circuit from Bastiaans et al. [1] is explained. Then, the main conditions for the simulations are explained, in which the last mentioned circuit is the standard which is improved. The improvement using cascoding and bootstrapping is explained. Last, the advantages and disadvantages of using a switch are discussed.

Figure 3.1: The basic idea of the amplifier. Two tank circuit are separated by a capacitor. The left tank and the capacitor act as a Bias Tee. The capacitance in the tank is a parasitic of the inductor, so not a mounted element. IN is the total input signal, i.e. the tunneling current. The DC OUT line goes to the feedback electronics of the STM. AC OUT is the signal for the noise measurements.

3.1 Amplifier as proposed by Bastiaans et al. [1]

The amplifier described in Bastiaans et al. is mostly based on DiCarlo et al. [8]. The high frequencies (2MHz) are measured using an LRC resonator, where the capacitance is mostly due to the coax cable. The proposed am-plifier by Bastiaans et al. does not have this parralel resistor, such that the

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impedance is larger. Part of the circuit is given by figure 3.1.

Two frequencies ranges are of importance. The main focus of this re-port is the high frequency range which is about 5MHz. At this high fre-quency range, the capacitor between the tanks is approximately a short. This gives an effective inductance of Le f f = L/2 and a capacitance of Ce f f =2C. The values for the tank inductance L and the tank capacitance C are 66µH and 15pF, respectively. The resonance frequency is therefore given by fres = _2π1 √1_LC, which is approximately 5MHz. The amplifier pro-posed by Bastiaans et al. also report a cable capacitance of 30pF. In the new amplifier this value is expected to be much smaller, to about 4pF. For simplicity, this is included in the tank capacitance.

The other frequency range is about 1kHz. This is the range where _dVdI measurements are performed. Current going through the left tank and thus to DC OUT goes to the feedback electronics of the STM. It is impor-tant that the current goes through the first tank such that STM feedback electronics receive the most signal. The ratio between the two currents is equal to the ratio of impedances, given by

Z1 Z2+Zc = −ω 2_LC c 1−ω2L(C+Cc) ≈ − ω 2 ω∗2. (3.1) where ω∗ = √1

LCc. So if Cc is too large, the ratio goes to one and only half the current will flow through the first tank. If the ratio is too large, the signal is well separated, but high frequency signals can’t pass through the second tank.

Note that this ratio also holds for signals at the input of the transistor, i.e. at the input of the right tank. So the input current noise of the transistor will not pass through the left tank and no additional noise source is added to DC OUT.

3.2 Rules for simulations

In all simulations given below, the following conditions are taken into ac-count. First of all, the temperature is 4.2K, the DC current which gives rise to shot noise is 100pA and charge carriers are taken to be single electrons, i.e.|q| =e. The schematic of the simulations is given by figure 3.2. In both tanks; the inductance is 66µH, the capacitance is 15pF, the Q-factor is 600 and the resistance is thus R = 2π f L_Q

f=3MHz

≈ 2.1Ω. The transistor is as-sumed to have noise values of 2.2fA/√Hz and 0.2nV/√Hz (appendix C).

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3.2 Rules for simulations 21

Figure 3.2: The equivalent circuit for the noise simulations is given here. The noise at the end of the drain of the transistor is due to the thermal noise of the drain resistor.

The capacitance of the coaxial cable from STM to circuit is assumed to be negligible, i.e. the total input capacitance if 15pF which is the capacitance of the first tank.

Figure 3.3: Two peaks are visible. The low frequency peak corresponds to the even mode, the high frequency peak to the odd mode. The high frequency peak is used.

Figure 3.3 shows the impedance of both tanks. That is, any current first arriving at the left tank, results in a voltage at the gate such that the vertical axis in figure 3.3 is defined as |Z| = |vgate

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due to the coupling capacitor. In practise, only the high frequency peak is used, because it has the largest impedance.

The total noise power arriving at the gate is shown in figure 3.4.

Figure 3.4:The total voltage noise which arrives at the gate of the transistor. The noise floor is due to the transistor noise, 0.2nV/√Hz.

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3.3 Cascoding 23

More useful is the signal to noise ratio. This is defined as

SNR(f) = |ZI|

2_S SN,i |ZI|2_S

tank1,i+ |ZI I|2(Stank,i+Str,i) +Str,v

, (3.2)

where ZI is the impedance for any current arriving at the left tank and ZI I is the impedance for any current arriving at the right tank, such that ZI = v_igate

le f t and ZI I =

vgate

i_right. At the gate of the transsitor, the SNR for each frequency is given by figure 3.5.

As was suggested in section 2.2.1, the bandwidth of the SNR is larger than the bandwidth of the impedance. In figure 3.6 both the impedance |ZI|and the SNR are normalised to their maximum.

Figure 3.6: Both SNR and impedance for currents arriving at left tank are nor-malised to one. One can see that the bandwidth is in fact larger for the SNR than for the impedance.

3.3 Cascoding

3.3.1 Improved SNR and bandwidth

Cascoding mostly affect the circuit after the transistor. The main idea is that using a larger gain, a larger bandwidth can be measured without los-ing good SNR. The SNR was already given in equation 3.2, however, effec-tively, the SNR is given by equation 3.3. Here, one can see that for a small

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gain, the SNR goes down. This is because the noise at the drain has less influence on the signal.

SNR(f) = A

2_|ZI|2_S SN,i A2_|ZI_|2_S

tank1,i+A2|ZI I|2(Stank,i+Str,i) +A2Str,v+Sdrain . (3.3) If the drain part of the transistor is 50Ω, the voltage noise is 0.1nV/√Hz. Even further, if gain is small, e.g. A=0.1, the noise is effectively 1nV/√Hz. Therefore, a large gain gives a better SNR.

A larger drain resistance implies a larger noise. However, this noise scale with Snoise ∼RD while the signal scales with Ssignal ∼ A2 ∼R2D. The SNR for different drain resistors is given by figure 3.7.

Figure 3.7:The SNR for different transistor transconductances and drain resistors is shown. The gain is given by A=gmRD.

The curve for gm = 2mS and RD = 50Ω is a rough approximation of the old situation. One can see that the bandwidth is relatively small. Increasing the transconductance increases the bandwidth. The bandwidth is limited by the 0.2nV/√Hz voltage noise of the transistor. Figure 3.7 shows that for gm = 40mS, a drain resistance of 50Ω and 750Ω shows no difference. The reason for using this larger than then necesary, is to eliminate other noise sources in the further amplification stages. These are

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given by Sextra. ∗, the SNR is

SNR(f) = |ZI|

2_S SN,i |ZI|2_S

tank1,i+ |ZI I|2(Stank,i+Str,i) +Str,v+Sdrain_A+2Sextra

. (3.4)

This shows that also these extra noise sources effectively go down by a factor A2.

Another noise source, which increases with frequency is the gate-drain capacitor. If this is about 1pF, the current noise is increased by S_drain,vω2C2.

In the cascode configuration, the input is more decoupled from the output, i.e. this noise source is expect to become less relevant. The voltage noise at the gate of the CG transistor is also added, which would include a noise of about 0.1nV/√Hz. For simplicity in the simulations, this is included in the transistor noise, such that the total transistor noise is still 0.2nV/√Hz.

3.4 Bootstrapping

Bootstrapping is the charging of discharging of any parasitic capacitance using an amplifier. When a capacitor is charged, the additional amplifier discharges the capacitor and v.v.. Effectively the capacitance is thus re-duced, which increases the bandwidth of the SNR, as shown in equation 2.10.

The key element for bootstrapping is a non-inverting amplifier with a gain A larger than one. Birk et al. [15] use an external amplifier. For prac-tical reasons, the amplifier is a PCB which also contains the feedback line, so there is no external amplifier. This has the advantage that the delay of the signal is smaller and thus the frequency of operation is larger. Birk et al. claim this is their major limitation in frequency range. As an exam-ple, if one would measure at frequencies of 30MHz, the wavelength is 10 meters. Therefore, to get a good signal, the amplification line needs to be much smaller than 10 meters. For a circuit on a chip, this should not give any problems. Figure 3.8 shows this setup, where the two CS transistor together form a non-inverting amplifier with gain A.

∗_{This thus effectively lowers the noise floor of the Lock-In amplifier, which is used to}

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Figure 3.8:A non-inverting amplifier, together with voltage divider(Ctop, Cbottom)

effectively reduce the capacitance C in the tank.

Using the KCL for the input, like in section 2.2.2, the idea becomes more intuitive. In fact, the principle is the opposite of the miller effect, where the input capacitance increases. The KCL is given by

(jωC+ 1 jωL + R ω2L2)v =pSSN,i+ q S_th,i+jωCbt((A−1)v+ q S_drain,v), (3.5) or more suggestively (jω(C− (A−1)Cbt) + 1 jωL+ R ω2L2)v =pSSN,i+ q S_th,i+jωCbt q S_drain,v. (3.6) One can see that the capacitance is effectively reduced for a gain A>1, to

Ce f f =C−Cbt(A−1). (3.7)

The complete noise equivalent circuit is given by figure 3.9. Where the noise of the drain comes from the drains of both amplification stages, where the first amplification stage causes the largest gain. † The noise at the drain is thus Sdrain = 8kbTRD1. There is an extra noise therm given by(ωCbt)2Sdrain. The extra noise therm scales linearly in gain (S ∼ RD ∼ A), but quadratically in Cbt. The effectively reduced capacitance scales

†_{The reason for choosing the first amplification stage to have the largest gate is the}

the total noise is given by S = 4kbTRD1(gmRD2)2+4kbTRD2. Together with A =

gmRD1gmRD2, the noise is S = 8kbTARD2. Minimising for R2 thus gives the lowest

noise. However, the second amplification stage is chosen to have unity gain and thus the thermal noise therm at the drain is given by S=8kbTRD1≡8kbTRdrain

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linearly in both capacitance and gain, so it is preferable to minimise the capacitance. Capacitors below 1pF are rare and therefore 1pF is chosen as the bootstrapping capacitance.

Figure 3.9: Noise equivalent circuit for bootstrapping. Here, β is a voltage dev-ider, which is for now assumed to be perfect. This means that only for the voltage dividing, Cbtis assumed to have an infinite impedance.

Figure 3.10:For larger effective gains (larger β) the resonance frequency shift and also the impedance increases. This gives an improved SNR. The gain is 30, such that the effective capacitance is approximately Ce f f =30pF−30·β·1pF+1pF.

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In order to get some fine tuning in the system, the output voltage divided, using a variable resistance or a varactor. In order to not add any noise, the voltage divider is constructed with two capacitors Ctopand Cbottomgiven rise to a voltage division ratio β =

Ctop

Ctop+Cbottom. One of these capacitors should thus be a varactor diode, such that some control is achieved. The total gain is thus Aβ. Thus SNR for different voltage division ratios is given in figure 3.10.

This figure shows the major improvement in SNR. This is because the impedance is given by ZLC =

q L

CQ, so for small capacitors the impedance increases much. At some gain, the capacitance becomes negative (see equation 3.7) and the LC resonator stops working, which is at Aβ = 1+

C

Cbt. Figure 3.10 seems to suggest the critical value for β is 1. This is not the case, A is 30 in this case, so also for β = 1 the effective capacitance is still positive.

3.4.1 Limitations on bootstrapping

It is of importance for the bootstrapping to have a flat gain. That is, for every frequency, the drain resistance has to be constant. This is a challenge, since there is a capacitor in series with an LC-resonator, which gives rise to a zero. This is expressed by

Zdrain =RD||( 1 jωCtop 1+Cbt+Ctop Cbottom −ω 2_L(C₊_C bt+_CCC_bottombt + Ctop Cbottom(C+Cbt)) 1+ Cbt Cbottom −ω 2_L(C₊_C bt+_CCC_bottombt ) ). (3.8) The drain thus has a zero at

ω2₀ = 1 LC(1+ Cbt C Cbottom+Ctop Cbottom+Ctop+Cbt )−1≈ 1 L(C+Cbt) . (3.9) Where the last approximation is for the voltage dividing capacitances to be larger then the tank capacitance. The appearance of the zero indicates that there is a frequency for which is the gain of the amplifier is zero. Note that the above two equations are approximations. The voltage at the gate is assumed to be independent of the input. For large gains, this approxi-mation is valid. If Cbottom and Ctop are large, this peculiarity should only appear at the lowest frequency and where gain is small and this equation is not valid i.e. the current would not flow over the resonator but over the

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3.5 Switch 29

resistor ‡. For larger gains, where it is valid, the frequency is well above this zero.

Another reason for a non-flat gain is low-pass filtering in the circuit. Typically, a flat gain can be created up too 100MHz (drain resistance of 500Ω and 3pF parralel capacitance). From frequencies higher than this, the bootstrapping would not work.

Birk et al. [15] claim the bootstrapping in their circuit breaks down be-cause the amplification line is too large w.r.t. the wavelength of the signal. For a circuit on a PCB, the amplification line is about 5cm. Therefore, the circuit only breaks down for frequencies above 100MHz (ratio length and wavelength is there 0.05₃ which should be sufficient for functioning boot-strapping).

3.5 Switch

In order to protect the transistor from static discharges or other effects, it could be usefull to implement a switch which disconnects the transistor circuit from the STM electronics.

A relais switch has been used by Robinson et al.[12], who created a very similar circuit for cryogenic environments. They reported a switching time of 1ms with a dissipation of less than 1 mJ. In their paper it was used to switch between an oscillator and external source.

In our case, the switch could be used to remove one inductor. Two inductors are necessary to make sure the noise from the transistor does not drop over the transimpedance amplifier. However, if we could fully separate the high frequency measurements and the regular measurements, the impedance could be doubled by using only one coil. The scheme is by figure 3.11.

For the regular measurements, the transistor has to be disconnected from the STM circuit, using ’S2’. A floating gate might harm the transis-tor, so the transistor has to be shorted to ground, using ’S1’. This is the configuration of figure 3.11.

‡_{The voltage at the input and output are approximately equal, so little current will}

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Figure 3.11:The schematic of a switch diagram is given. This current setup would be for low-frequency measurements. If both switches are in the other direction, the high frequency measurement setup is shown.

For the high frequency measurements, the coil has to be grounded to the same ground as the transistor, so ’S1’ is flipped. ’S2’ also has to be connected to the gate of course.

The downside of a switch is the additional capacitance towards the in-ternal electronics of the relais. This capacitance will be in the order of pF which could give additional current noise (see section 3.4). Furthermore, each time a switch is switched, this capacitance can be slightly different, yielding a change in this noises and resonance frequency. Last, it was re-ported by [12] that the switching voltage has to be increased when used more often.

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Chapter

4

Final circuit design

This chapter describes the exact design of the final circuit. First, the used components are described in some detail. Then, a schematic with all com-ponents is given, together with an explanation for the used comcom-ponents. Finally, some drawings shows the implementation of the circuit is the STM.

4.1 PCB components

The resistors and capacitors used are SMD 0805 or 0603 components. Ca-pacitors are labelled NP0 meaning they vary only 0.5% between -55 to +125 degrees centigrade.

The transistors are HEMTs developed by Dong et al. [13]. They show good noise characteristics of 2.2fA/√Hz at 1MHz and 0.26nV/√Hz at 100kHz (appendix figure C.5, transistor B2). For the MHz range, the volt-age noise is expected to be slightly smaller, to 0.2nV/√Hz, because of the 1/f behaviour. Details are described in appendix C.

In the first generation amplifier, the circuit board was make from Rogers TMM10i. This because of its low outgassing properties. The circuit board in the amplifier proposed by this report uses Rogers 4003. The Rogers 4003 has a dielectric constant of 3.38, while TMM10 has 9.20. Thermal conduc-tivity of 0.76 for TMM10i and 0.71 for 4003. Based on these specifications, no changes are expected between the amplifier from Bastiaan et al. [1] and the proposed one. ∗

The inductor consists of niobium wire. Important is that the wire has

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no normal metal coating, as this would reduce the Q-factor significantly [24]. The core is made out of Macor, as this also causes little dissipation of RF field induced by the coil. Last, the coil is shielded using niobium. The implemented coil is shown in appendix C and figure 4.4.

4.2 Circuit design

Figure 4.1: Schematic with all components as is shown in table 4.1. The right hand side faces the STM.

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4.2 Circuit design 33

A schematic of the physical circuit is given by figure 4.1. The circuit dia-gram is given in figure 4.2 with all elements denoted in table 4.1. Capac-itors C2−8 only have the purpose of blocking DC signal while acting as short for high frequency signal. Reistors R1 and R2 have no function in the circuit, they only dampen out high frequency (>100MHz) oscillations. Some elements require special attention.

Table 4.1:Circuit elements as shown in figures 4.1 and 4.2.

C1 100pF C2,C3,C4,C5,C6,C7,C8 220nF R1,R2 10Ω R3 130Ω R4 2kΩ R5 1MΩ R6 68kΩ R7 200Ω R8 68Ω R9 2.2kΩ R10 3kΩ

4.2.1 Common Source biasing; R

3

,R

4

First of all, the source resistor of the CS transistor, R3 (first stage). The resistance is set to be 130Ω. From figure C.6, transistor B2 in appendix C, the drain source current is IDS =0.5mA for a bias gate-source voltage of VGS = −78.7mV. This would correspond to a resistance of RS ≈ 160Ω. This resistance is chosen slightly smaller, such that the current is slightly larger and the transconductance is larger. The transconductance should be about 30-35 mS.

The drain resistance of the CG transistor, R4is set to 2kΩ. If this is too small, the gain is too small. However, if it is too large, the dissipation is too large.

The bias voltage is determined by the above mentioned parameters, according to VDS = IDS(R2+R3+R4) +VDS,CG+VDS,CS, where VDS,CG and VDS,CS are both 100mV for optimal noise performance.

4.2.2 Common Drain biasing; R

7

, R

9

, R

10

The source resistance of the third transistor, R7is set at 200Ω. From figure C.7, transistor A1, the drain-source current of transistor is set at IDS,CD=0.5mA.

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This required a gate-source voltage of about 100mV, hence the 200Ω resis-tor. Resistor R9 is determined by the bias voltage i.e. R9 = Vbias−_IVDS −R7. The total dissipation can be written as

P = I2_DS,CS(R2+R3+R4) +I_DS,CD2 (R7+R9) +IDS,CS(VDS,CS+VDS,CG) +IDS,CDVDC,CD. (4.1)

This is approximately equal to 2mW. The resistance R10set the gate voltage at 0V. This is chosen to be large, such that the gain of the CG is large.

4.2.3 Common Gate biasing; R

5

,R

6

This voltage divider determines gate voltage of the CG. If this value where too small, e.g. grounded, the gate-source voltage would be too small and thus the noise is too large. It is important to have the CG in saturation, which is why a voltage divider of β ≈ _68kΩ68kΩ₊_1000kΩ is chosen. The bias volt-age will be slightly larger than VBias=80mV+100mV+100mV+1000mV=1.28V. The voltage at the gate is thus slightly larger than 80mV. The gate-source voltage of the CG is thus sligthly smaller than 100mV. So the transistor is well in saturation.

4.2.4 Impedance matching; R

7

,R

8

The output should match the 50Ω of the coaxial cable. This thus requires R8to be 68Ω, such that the output is Rout= _RR₇7+RR88 ≈50Ω.

4.3 Implementation in STM

The limited space has determined the shape of the circuit as shown in figure 4.1. The implementation of this circuit is shown in figure 4.3. The circuit is attached to the side poles using four clamps. From figure 4.4 one can see that the clamps are not symmetrically spaced. This is due to the location of PCB components. Besides attachment, the clamps also have the purpose of thermalisation.

Three connectors are shown in figure 4.3, which correspond to ’DC OUT’, ’BIAS’ and ’AC OUT’ from figure 4.1. The ’In’ is visible in figure 4.5. This is directly connected to the STM, such that the input capacitance is small.

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4.3 Implementation in STM 35

Figure 4.3:Implementation of the PCB with attachment. The clamps to the poles have the function of both attachment and thermalisation.

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Figure 4.5: The back of the PCB. The connector perpendicular to the PCB is the input.

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Chapter

5

Results and discussion

This section shows all test circuits, i.e. the room temperature measure-ments. First, the results of cascoding are presented. The benefit of cas-coding as well as some points of concern are explained. Then, the results of bootstrapping are presented. This turned out to be unsuccessful and possible explanations are given.

5.1 Cascoding

The reduction of the miller capacitance is measured using a LC resonator at the input. All measurements have a 33µH input coil with an effective parralel capacitance of 1.6pF. The other parasitic capacitances (transistor, cable) are included in this effective capacitance. The Self Resonance Fre-quency (SRF) is then 22 MHz.

5.1.1 Not cascoding

To show the relevance of cascoding, first the shift in resonance frequency is given for a single CS transistor, as is shown in figure 5.2. In therms of voltages, S21 =20 log(_vv_outin). The units of this parameter are arbitrary, but they can be viewed as a measure of the impedance of the resonator. The increase of bias voltage corresponds to a larger gain and therefore with a larger miller capacitance. The equivalent circuit is shown in figure 5.1.

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Figure 5.1: Schematic of the used circuit. The capacitance between the gate and the drain is effectively enlarged, as visualised in figure 5.2.

Figure 5.2:If the first stage is not cascoded, the resonance frequency would shift due the increasing gain. The gain scales with bias voltage (legend) over the tran-sistor.

The vertical axis in figure 5.2 is the ratio between the out- and input voltage. This is proportional to the impedance of the resonator. The num-ber do not provide much information about the resonator, because the gain is also varied (the tails of the resonator also move up). Most important is

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5.1 Cascoding 39

that the frequency changes as a function of the bias voltage, or equiva-lently, the frequency changes as a function of the gain in the tails.

Using the relation ∆C_C = f02−f2

f2 , the miller capacitance ∆C can be cal-culated. The resonance frequency in figure 5.2 decreases from 22Mhz to 17Mhz and with a capacitance of the coil of about 1.6pF, the miller capaci-tance is 1.1pF. Together with the flat V/V gain of 10, the gate-drain capac-itance can be estimated to be 0.1pF. Note the for the low-noise HEMTs, the gate-drain capacitance is 1pF, and the miller effect becomes more substan-tial.

5.1.2 Cascoding applied

Now that the increase in effective capacitance is clear, the effect of cascod-ing can be shown. It is important to have the cascaded transistor (CG) to be in saturation. This can be controlled by two resistors which voltage divider VDD. Figure 5.3 shows this setup, where Rtop and Rbottom deter-mine the gate voltage using Vgate = VDD_R_bottomRbottom+Rtop. Figure 5.4 shows the cascoding effect for a voltage dividing ratio of 1/3.

Figure 5.3: The equivalent circuit of cascoding is given. The resistors Rtop and

R_bottom form a voltage divider, which determine the saturation point of the cas-caded CG transistor.

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Figure 5.4: Cascoding effect for a top resistor of 10kΩ and a bottom resistor of

20kΩ. The gate voltage is large, so the CG saturates only for high bias voltages, hence the resonance frequency shift back up. The legend indicates the bias volt-age.

Figure 5.5: An estimate of the miller capacitance is set against a rough estimate of the gain for voltage dividing ratio _10kΩ10kΩ₊_39kΩ. This plot is just qualitative. First, gain increases fast giving larger miller capacitance. The second transistor just acts as a resistor of about 1kΩ when not in saturation. At the downward slope, the cascaded transistor becomes saturated and thus the miller capacitance goes down.

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5.1 Cascoding 41

For larger bias voltages, i.e. larger gains, the resonance frequency first goes down, but goes up again at some point. Converting this resonance frequency to capacitances, one can more clearly see the effect of cascoding, as is shown in figure 5.5.

5.1.3 Optimal bias voltage

The ratio of voltage dividing is crucial since the gate voltage determines when the CG transistor is in saturation.

1MΩ. The gate voltage is small, so the CG saturates rapidly.

If the gate voltage is too small, as shown in figure 5.6, the miller effect is not visible, but drain source voltage of the CG stage (cascaded stage) is too large, which leads to a worse noise performance for the HEMTs. If the gate voltage is too large, the CG saturates for large bias voltages. For these large bias voltages, the CS (first transistor) has a too large drain-source voltage, which also gives a worse noise performance. The optimal form is the intermediate voltage divider as is given by figure 5.7. Here the shift in resonance frequency only happened at one bias voltage.

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100kΩ. This ratio is between those of figures 5.6 and 5.4. Only at 3.6V bias volt-age, the miller effect is apparent.

Figure 5.8: 33µH inductor, no additional capacitance. The resistance ratio is the voltage division ratio, i.e. the fraction of VDDat the gate fo the CG transistor. For

a too large voltage dividing ratio, the gate voltage is too large and the bootstrap-ping has no effect.

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Figure 5.8 shows this relation even more clearly. The ideal situation would be exactly the voltage dividing ratio of_10kΩ10kΩ₊_110kΩ, i.e. a top resistor of 10kΩ and a bottom resistor of 100kΩ. Actually, the voltage dividing ratio should be slightly more than 10/110 to achieve optimal performance.

5.2 Bootstrapping

In contrast to the idea of cascoding, bootstrapping does not show good results, and is therefore not implemented in the final amplifier. It is still interesting to review its functioning and instabilities.

5.2.1 Bootstrapping applied

Bootstrapping requires a non-inverting constant amplifier, which is a flat gain and a phase shift around zero. This is measured by disconnecting the bootstrapping capacitor Cbt, the setup is shown in 5.9. Figures 5.10 shows a flat gain and flat phase response, so that indeed a non-inverting amplifier is created.

Figure 5.9: Circuit for measuring flat gain. The input and output resistances are 50Ω. The output is voltage divided, such that the signal is attenuated by approx-imately 20 dB. This should be corrected for in figure 5.10.

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Figure 5.10:Gain of the amplifier. One should correct for the 20dB attenuation by adding 20dB. The amplitude gain goes up to 10V/V.

Figure 5.11:The phase of the transmitted signal. The phase shift is approximately zero.

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The effect of bootstrapping is the opposite of cascoding. A 33µH induc-tor is connected in parallel with a total capacitance of 63pF. When increas-ing the bias current, the gain increases and thus the effective capacitance decreases. Figure 5.12 shows the increase in resonance frequency with in-creasing gain.

Figure 5.12: Shift in resonance frequency after bootstrapping. The resonance fre-quency doubles due to the effect of bootstrapping.

Figure 5.13: Estimate of the effective parallel capacitance as a function of the estimated amplitude gain. Again, the gain is a rough estimate.

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The capacitance is effectively reduced to 16pF. Thus, the resonance fre-quency can effectively be doubled, which thus significantly extends the bandwidth. The effective capacitance as a function of gain is given in fig-ure 5.13.

5.2.2 Instability

Figure 5.12 shows a good functioning of the LC resonator. However, in practise, some instability occurs. First of all, when applying a too large VDD, i.e. the gain is too large some ’strange’ peaks occur. These peaks are given in figure 5.14. From a certain drain voltage, the peak becomes sharp and higher harmonics occur. This peak in unpredictable (shifts in resonance frequency) and should therefore not be used for measurements. The instability shows peaks at the higher harmonics of resonance fre-quency as figure 5.15 shows. Also, when the bootstrapping capacitance is increased, the instability occurs. Also the peak of the instability shifts down as is shown in figure 5.16.

Figure 5.14:If unstable, peaks become much sharper compared to usual LC res-onance impedance. Also for equal bias voltage (6.4V) and thus equal gain, the peak can be stable or unstable.

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Figure 5.15: The main frequency peaks are at f = f0n, n ∈ N. There are also

peaks at f = 5₄f0visible, which correspond to higher harmonics.

Figure 5.16: 33µH input inductance, 130 pF parallel capacitance. For too large capacitance, the LC resonance becomes unstable.

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5.2.3 Possible explanations

An explanation for the instability is that the input power on the transistor is too large. The transistor gives unpredictable behaviour and only trans-mits some signal around the frequency where the signal is maximal. How-ever,the input power has been attenuated significantly using a tunnelling resistor and RC filters. This did not influence the instability.

A second explanation is based on section 2.2.2. Reducing the capaci-tance is the same as reducing the mass. This is a difficult to visualise, but the equation could also be mapped to a pendulum with two masses at two different lengths

¨θ+gm1l1+m2l2 m1l2₁+m2l₂2

θ =0. (5.1)

Note that if one mass reaches above turning point, a negative contribution is added, i.e. the pendulum is bootstrapped. Having two masses above and below the turning point is intuitively unstable. However, mathemat-ically, only if m1l1+m2l2 < 0, the pendulum is unstable. This means that one would reach infinite frequency before becoming unstable. Although this does not explain the instability, it does give an intuitive idea. Any imperfections (e.g. gain or phase depend on input signal) would create an unstable system. However, from figures 5.10 and 5.11, the phase and gain both seem flat.

A third explanation is that the amplifier forms a oscillator. The transfer function from the output of the amplifier to the input of the amplifier is given by H(ω) = A −ω 2_LC bt 1−ω2L(C+Cbt) (5.2) where an infinite Q-factor is considered for simplicity. Note that the input voltage is ”unknown” in the above equation. If this is considered to be ”known”, as it should, the circuit is stable (see equation 3.6). Equation 5.2 suggests that the gain is largest at f = _2π1 √ 1

L(C+Cbt)

. Also there is no phase shift around this frequency (also required for oscillations, see section 2.5). This suggests that the resonance frequency goes down with increasing capacitance, which is consistent with figure 5.16. However, if this explanation was correct, the bootstrapping would not have worked at all. Besides, the Barkhausen theorem would have been satisfied long before.

This explanation can be tested by high pass filtering the lower fre-quency. However, using low order filters, only artefacts of this filter can be shown. If the filters frequency is too high, the full signal is attenuated

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such that the total gain is less than one and the bootstrapping is pointless. If the filter has a too low cut-off frequency, the instabilities still occur.

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Chapter

6

Cryogenic measurements

Unfortunately, the final transistor is still under construction, so no data can be displayed here.

6.1 Gain measurement

To measure the gain, the input and output are connected to 50Ω. The Vec-tor Network Analyser (VNA) measures the power amplification in those lines. The figure to be inserted would show a flat voltage gain of approxi-mately 22 up to about 20MHz.

6.2 LC resonator

To measure the LC-resonator, a 50Ω is again connected to the output, but the input consists of the two coils with their coupling capacitor, just as is indicated in figures 4.2. If the input also has a small capacitance con-nected to it, the resonance frequency and bandwidth can be measured, from which the inductance is measured.

The total input noise can be measured using a Lock-In at the output and no input signal. The signal at the resonance is predominantly caused by current noise. The noise floor is due to the voltage noise.

6.3 Noise estimations

Because of the lack of experimental data, some estimations are made. The estimated voltage noise is 0.2nV/√Hz, which is only due to the

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transis-tor voltage noise. The total current noise is the sum of the noise of the two coils and the transistor. This is estimated using S =

q 24kbT

Qω0L + (2.2·10

−15₎2_. For Q= 600, ω0 = 5MHz and L =66µH, the input current noise is about 19fA/√Hz.

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Chapter

7

Conclusion and outlook

In order to improve the bandwidth, one should measure the bandwidth of the SNR instead of the bandwidth of the impedance. The bandwidth of the SNR can be improved by increasing the gain, such that the white voltage noise sources after the resonator have a smaller influence. In the amplifier an amplitude gain of 22 is chosen. Because of the Miller effect, this would add a capacitance of 22pF, which reduces the bandwidth. This can be prohibited by using cascoding which is a CS transistor followed by a CG transistor. In order to match the 50Ω of the coax cable, the CG is followed by a CD with an output resistance of 50Ω and unity gain.

This setup would give an input current noise of 19fA/√Hz and a volt-age noise of 0.2nV/√Hz.

Reducing the capacitance with bootstrapping, i.e. a feedforward signal through a transistor, would improve the SNR even more. In the testing stage, this shows instabilities which are not fully understood. The best ex-planation is given by the Barkhausen oscillation theorem; for a gain larger than one and no phase shift oscillations will occur.

7.1 Outlook

This project has focused mainly of the transistor stages an less on the in-ductor. Improvements might be achieved by fabrication a coil with higher Q-factor as was reported in [18][24][25]. The challenge here is to fabricate coils and shielding for a small space and Ultra High Vacuum.

Also a SQUID might be used. For state of the art SQUID current sen-sors [26] the input current is about 0.08pA/√Hz, which is only one or-der of magnitude larger. Experimental data show this is possible up to

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100kHz. With proper shielding, this should work for higher frequencies as well, such that a good resolution for a large bandwidth can be achieved. Finally, bootstrapping can still be successful. Using a high order filter to filter out the parasitic oscillations, but leave the effective LC resonance frequency unchanged, the bootstrapping might work. However, there is a trade-off between the bootstrapping capacitor and the order of the filter. To get a small extra noise from the bootstrapping, the capacitance should be small and the order of the filter should be very large. It is unlikely that this would work in practise.

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Cryogenic Low Noise Ampliﬁer for Noise Spectroscopy in Scanning Tunnelling Microscopy

Cryogenic Low Noise Amplifier

for Noise Spectroscopy in Scanning

Tunnelling Microscopy

Cryogenic Low Noise Amplifier

for Noise Spectroscopy in Scanning

Tunnelling Microscopy

Corn´e Koks

Abstract

Contents

Chapter

1

Introduction

1.1

Shot noise

1.2

Cryogenic amplifier

1.3

Outline

Chapter

2

Theory

2.1

Noise

2.1.1

Shot noise

2.1.2

Thermal noise

2.1.3

1/f noise

2.1.4

Transistor noise

2.2

LC resonator

2.2.1

Impedance and bandwidth

2.2.2

Mechanical analog

2.3

Transistor setups

2.3.1

Common drain

2.3.2

Common source

2.3.3

Common gate

2.3.4

Cascoding

2.4

Impedance matching

2.4.1

Finite length transmission line

2.5

Barkhausen stability criterion

Chapter

3

Simulations

3.1

Amplifier as proposed by Bastiaans et al. [1]

3.2

Rules for simulations

3.3

Cascoding

3.3.1

Improved SNR and bandwidth

3.4

Bootstrapping

3.4.1

Limitations on bootstrapping

3.5

Switch

Chapter

4

Final circuit design

4.1

PCB components

4.2

Circuit design

4.2.1

Common Source biasing; R