A 0.28pJ/b 2Gb/s/ch transceiver in 90nm CMOS for 10mm on-chip interconnects

ISSCC 2007 / SESSION 22

/

DIGITAL CIRCUIT

INNOVATIONS

/

22.9

22.9

A

0.28pJ/b 2Gb/s/ch

Transceiver in 9Onm CMOS

The schematic of the receiver implementation is shown in Fig.

for

10mm

On-Chip interconnects

22.9.3. The left of the_{sense-amplifier-basedflip-flop}

diagram

_(SAFF),shows a clocked comparator, a_{which consists ofa}

differ-Eisse Mensink. Schinkel

EricKlumperinkEdvanTuiential

input

stage,

cross-coupled

inverters and anSR-latch. The

Fisse Mensink,

Daniel

Schinkel,

Eric

Kiumperink,

Ed van

Tuiji,

outputs of the SR-latch drive the low-pass feedback filter, in this

Brain N\lauta case an RCfilter, implementedwithpass-gates and anti-parallel

University ofTwente, Enschede, The Netherlands gate capacitances. The filter output is

coupled

back into the SAFF via a second differential input stage, as shown on the right of

Fig.

22.9.3.

IEQ

setsthe feedback

gain

A

(see

Fig.

22.9.2).

The The bandwidth ofglobalon-chipinterconnects inmodern CMOS total area of the receiver is 117 gm2

(324m2

for the DFE part) processes islimitedby theirhigh resistance and

capacitance

[1].

Repeaters thatareusedto

speed

uptheseinterconnectsconsume The chip micrograph is shown in Fig. 22.9.7. The 10mm-long aconsiderableamountofpower[2] andarea.

Recently

published

interconnects, placed in metal 4, have a total distributed resist-techniques [1-4] increasethe achievable datarate atthecostof ance of

2kQ

and a capacitanceof

2.8pF.

Theother metal layers highstatic powerconsumption,

leading

to

relatively

high

energy are filled with GND- and

V,,-connected

metal stripes. An exter-per bit for low data

activity.

On the other

hand,

low-swing

nal pattern generator/analyzer generates data and measures schemes [5] often sacrifice bandwidth for power

reduction,

or BER. The receiver clock is generated externally to adapt its make useofan extra low-voltage power

supply.

More

ideally,

a phase to the eyepositionand to be able to measure eyewidths.In transceiverwould combine low

dynamic

andstatic powerwith a an application, a simple skew circuit or a source-synchronous

high achievable datarate. approachcould be used to generate theproperclock phase.

Eye-diaglrams alremeasured via 50Qoutput

buffercs

that

alre

connect-The bandwidth and powerconsumption ofanRC-limited inter- edtotheoutput ofa

differenetial

intercontnaect.

connect depends onits source

(Zs)

and load

impedances

(ZL).

In

Fig. 22.9.1, aconventionalcase withaninverterusedasboth a Figure 22.9.4 shows a measuredeye diagram at a data rate of transmitter (Zs =

100Q)

and a receiver

(ZL

=

10fF)

has

only

lGb/s.

Themeasured BER at the edges of the eye is also shown. 62MRz bandwidth and

high

power

consumption.

Current-seas- TheBER drops rapidly below a clock skew of

-150ps

and above ingschemes(ZL=190Q inFig.

22.9.1)

increasethe bandwidthup

180ps,

giving aneye-openingof 670ps. Data rates up to

1.35Gb/s

to 3x [1,4], but with increased power atlow dataactivities. We are achieved without DFE (IEQ=O). The one-6 offset of the total propose using a

capacitive

transmitter

(Zs

= 255fF in

Fig.

transceiveris

llmV,

measuredover 20samples. Due to this

off-22.9.1), which has the samebandwidth

improvement

ascurrent set, not all samplesachieve

1.35Gb/s,

but all samples do achieve sensing, but with lowerpowerand without staticpower consump- aslightly lower data rate of

lGb/s.

Simulationsover process

cor-tion. ners alsoindicate that the circuit is robust to PVT variations at a

Trate

slightly lower than themaximumachievable datarate.Data Thispaperpresents atransceiverfor 10mm

long

inte9connects

in

rates up to 2Gb/s aremeasuredwith DFE. Fig. 22.9.5 shows that a 1.2V 90nm 6M

CMAOS

process, showntin Fig. 22.9.2. Acapaci- DFEimproves the eye opening for a wide range of

IER.

InL

an appli-tivepre-emphasistransmitterbothincreasesthe bandwidth and DFE can

thereye

be

fora

design

Ie.

decreases the

voltage

swing,without the need foran additional

cation, 'EQ

cantherefore be fixedat

design

time.

power supply. As

low-swing

signaling

is more

susceptible

to In Fig. 22.9.6, the measured energy per bit is plotted as a

func-crosstalk, we use differential interconnects with twists

[1],

of tion oftransition probabilityatdifferentdatarates.With random whichonlya

single-ended

halfis shown. Incontrast tothe wide data at2Gb/s,only

0.28pJ/b

isdissipated,which is 7x lower than interconnects used in [2,3], we use

relatively

small width earlierwork

[1,4].

The powerdissipationof

0.12pJ/b

at zero data (0.54,um) and

spacing

(0.32gm) [1,4]

andassume

high

metal-den- activityismainlydue to the powerdissipationinthe SAFF, which sity

surroundings.

Thereceiverusesdecision feedback

equaliza-

has largetransistorstoget a low offset(6s =

8mV).

Clock-gating tion (DFE) [6]tofurther increasethe achievable data rate. The canbe usedtoeliminatepower

consumption

during

inactive

pen-DFE,withacontinuous-time feedback

filter,

consumesalmostno ods. The DFE part of thecircuitrequires less than 7% of the total extrapower.The

bandwidth-increasing

pre-emphasis

effect of the transceiverpower, while it can increase theachievabledata rate transmitter is shown at the bottom

right

of

Fig.

22.9.2: every 1.5x.

transition is

emphasized

by

thetransmitter

by injecting

a

charge

viacapacitance

Cs.

With

the presented transceiver, the same high data rates over

small RC bandwidth limited

on-chip

interconnectsare

possible

as

With only a series capacitor(AC-coupling), the DC voltage on the with

plrevious

solutions, but with a

7x

lowerpower consumption. interconnect isnotwell definedasthere isnoDC

path

tooneof By

using both

acapacitive pre-emphasis

transmitter and

contin-the supplies. Tocontrol the DC

voltage,

aloadresistorRL and a

uous-time

DFE, a

data rate

of

2Gb/s

is

achieved over

a 10mm transconductance

G,,,

controlled

by

Vi.,

areadded

(see Fig.

22.9.2).

long

interconnect.

The

transceiver

consumes

only

0.28pJ/b.

Byhaving the timeconstantsC

/G,,

and

RLCwi,,

equal,

the

trans-fer function resembles the transtrans-fer function of the

capacitive

Acknowledgements:

transmitter in Fig. 22.9.1. Ifa small

G,,,

(5gS)

and a

large RL

We thank

Philips

Research for

chip fabrication,

the Dutch

Technology

(16kQ) arechosen, thestaticcurrentis

kept

small

(6gA)

and also Foundation (STW, project

TCS.5791)

forfundingand Gerard Wienk for the power consumption remains similar.

Gm

and

RL

are

imple-

assistance.

mented with MOStransistors asvisibleinthe bottompart of

Fig.

22.9.2. Folr

Cs,

the

gate

capacitanlce

ofan NMOS transistor is

[11

D.

Schinkel,

E. Mensink, E. A. M. Klumperink, etal., "A3-Gb/s/ch used. As the gateoxideismuch thinner than the oxide between Transceiver for 10-mm Uninterrupted

RC-limited

Global On-Chip interconnects, the area consumed

by

C,

is

relatively

small

Interconnects,"

IEEEJ.

Solid-State

Circuits,

vol. 41,no. 1,pp. 297-306,

(6x6gM2). The

signals,

witha

voltage swing

of

100mV,

arechosen Jan.,2006.

closeto

V,

of

1.2V,

because thecapacitance of the NMOStransis- [21A. P. Jose, G. Patounakis, and K. L. Shepard,

"Pulsed

Current-Mode

toris

highest

fora

high

gate-source

voltage.

The totalareaof the Signaling for NearlySpeed-of-Light Intrachip Communication," IEEEJ.

differential transmitteris 226 gM2

.Solid-State

Circuits,vol. 41,no. 4, pp. 772-780,

Apr.,

2006.

[31

A.

P.

Jose,

and

K. L.

Shepard,

"Distributed

Loss

Compensation

for Low-LatencyOn-ChipInterconnects,"ISSCCDig. Tech.Papers,pp.

516-Thereceiverconcept is also showninn Fig. 22.9.2.Aclocked colm- 517,

Feh.,

2006.

parator restores the low-swing line output to full swing. DFE fur-

[41

L. Zhang, J.

Witson,

R.

Bashiruttah,

et

at,,

"Driver

Pro-Emnphasis

ther

ilncreases

the achievable data rate. Instead of the

ofteln-used

Techniques for On-Chip

Glohal

Buses,"ISLPED, pp. 186-191, Aug., 2005. FIR

filters

[6], a

continuous-timne

filter

operates as the decision

[51

H.:

Zhang, V. George, and J. M.

Rahaey,

"Low-Swing On-Chip fedbc

fi1ltr

Thi flter

cacl mos of the ISI with a

1iml

Signaling Techniques: Effectiveness and Rohustness,"IEEE

Thanrs.

VLSI anpoe-fiin fis-re imlmnain whra_{an( owerettelentlst-ofe lmpemetatln, nLeeasan}n FI_q-4 Systems, vol. 5, pp. 264-272, Jun., 2000._{[61 V. Stojanovic, A.}

_HIo,

_B.

_Gartlepp,

_{et at,, "Adaptive Equatizationand}

f1iter

requires

many

taps.

Data Recovery in a

Duat-Mode

(PAM2/4) Seriat

Link

Transceiver,"

Symp.

VLSICircuits, pp. 348-351, Jun., 2004.

ISSCC 2007

1

February 14, 2007 /12:00 PM

Conventional: 3 .3 ^

lGbps

S 40

2R

1000

VL

'

BW=

$80

62MvHz

JaIou

V >ff|20H ti |cpctvpeepai troncalclcecmaarwit

vs

OlfFT

Q

-120_{10 1b}

Oan

bs

_{10 0 05 1}

frequency(Hz) transitionprobability

Gm*Vi

n

Current-sensing:

BW 1bp

Capacitive transmitter: '4 |~~~~1

Gbps

VoQ

Rl

CO

g

- I _ 8~~~~~~~-01 22MZ\{n1 5|o9

1000

VL

,

_W

r

120

0Mzcapacitive

pre-emphasis interconnect and clockedcomparatorwith

VST

> -120 w

~~~~~~~~~~~~~transmitter

biasing continuous-time

190flo,~1

10,

I0 0 0.5 1 feedback filter

frequency(Hz) transitionprobability circuitimplementation: V

DD1.4V .k

Capacitive

transmitter: 0 1Gbps 255fF

AU40

2V

LKK | ' t RC = ~~~L W °i|_n

_1

_ 1ns /O\ 1n

-8O

220MHz

L4

VV[.jjv

VL

. 1

OfFT

-120₁6 a 10 0

10

10

0.5 1

VLR1\

frequency (Hz) transitionprobabilityIVL2J

=~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11

>_t

Wf3-i

e

Figure

22.91: Bandwidth and energy per bitversustransition

probability

(=

data activ- tm

ity)

forthree different termination schemes. The resultsarefor 10mmdifferential inter-

Figure

22.9.2:

Concept

of transceiver and circuit

implementation

of the

capacitive

pre-connectswithadistributed resistance of 2kil andadistributed

capacitance

of

2.8pF.

emphasis

transmitter.

.~~1L,

HF;'

r/

.. .2 Seedbackfitense

ampliteer

RC~~~~

atheoedgesuoftte0In

Eye-opening Measurements |BitError RateMeasurements

IVfb+ Vfb- 1 ° 1-________IEQ _

w

U-Vini1

'in-

_Ha

,

11

I150

100 -50 0 50 150

.# .X.}....clock..25GI}I5

delay

(ps)

Figure

22.9.3:

Implementation

of the clocked

comparator

with continuous-time

Figure

22.9A4 Eye-diagram

atthe

input

of the receiver at

1Gb/s

and measured Bit Error

feedback filter. Rate at the

edges

of theeye.

Eye-opening

Measurements Power

Consumption

Measurements

600~~~~~~~~~~~~~~~~~05

...

0.25Gb/s,

I'EQ0=-t ----s---r

0.45

--e-0.50Gb/s,

E0

5200r

EQS11°2 .''.-#t---. 500 /-| >

rte-=1.OQGbI:i/°

data =0 0.40-EQ

-=.-1.25Gb-

.- s

E.0

0I35

; Sdt.../

1.5Gb/s,

IEQ75gA

O --El-- I-r

=.1.75Gb/s,

'E =1 g 1 20 40 60 BO 100 ° 0.1 0.2 O.3 0.5~~00.4 0 E

0-,~~~~~~~~~~~~~~~~~~~~~~~~0

~

2.00G/

EQ (U

20.25

'

-e-data

rate =1.25 Gb/s 00 0.1 -e- at at 13 G/

-2-data

rate =1.50

Gb/s

Figure

22.9.5:

Measured eye-opening for different data rates as a function of

lEo.

transition

probability

(=data

activlity).

Conztinued onz Patge

612

ISSCC 2007

PAPER

CONTINUATIONS

1mm

Figure

22.9.7:

Chip micrograph.