Every integrated circuit (IC) goes through two types of tests before it can be sold and used to build a product: wafer test and final test. The wafer test (or probing) is the test process that checks for fabrication mistakes at the front-end process. A probe card is used to connect the dies on the wafer with the tester. Small probes touch down on the dies and test the dies on fabrication mistakes. Figure 1.2 shows a schematic and a picture of a probe card.
(a) A schematic overview of a probe card (b) A picture of probes touching down on a wafer Figure 1.2: An example of a probe card
The second type of test will be the last test on the product before it is shipped to its customers.
This test is called final test. Final test takes place after the products are assembled. The purpose of final test is to ensure that no products have been damaged during wire-bonding and packaging.
The final products are loaded into a load board, this serves as a connection tool between the products and the tester. Figure 1.3 shows an example of a load board with space for eight products.
Figure 1.3: An example of a load board
Each time a product is inserted into the load board and tested is called a test insertion. Products are often tested multiple times, depending on the product type and purpose. Common tests are temperature tests, in which the product is tested at a very high temperature and a very low temperature. This study focuses on a test insertion policy analysis in the final test of the integrated circuit production. Testing accounts for approximately five percent of the total expenses at NXP, so it often is an area where improvement needs to be made in order to decrease the production costs and increase the total profits of NXP.
NXP Graduation thesis Problem definition and research questions
2 Problem definition and research questions
This section takes a closer look at the problem at hand within NXP and discusses the research questions that will tackle the problem. The section explains what the different insertion policies are and how the test parallelism is determent. Finally, the importance of different changeovers is discussed.
2.1 Problem Definition
During the final test of the integrated circuit (IC) production process, the products are tested on manufacturing mistakes that might occur at the assembly process. When products are being tested, a lot of products need to be inserted into the tester. A lot consists of 100-15000 IC products. A lot is inserted at the test handler and the products are tested in batches. The batch size is also called test parallelism. The current research will revolve around the test insertion policies in the final test. The easiest insertion policy is to insert the product once per test program and let the tester run the whole test program. However, engineers at NXP found out that splitting the test program into two insertions could decrease the total testing time a lot.
This could be achieved by increasing the test parallelism of the second insertion. The first thing that needs to be explained is how the maximum test parallelism is determined. Each integrated circuit has a certain number of connection pins. These are connection points on the back or the side of an integrated circuit. These connection pins need to be tested on manufacturing mistakes during the assembly process. Semiconductor testers have a limited number of connections to which the pins can be connected. Divide the total connections at the tester by the connection pins on the integrated circuit to determine the maximum test parallelism. Figure 2.1 shows how this works.
Figure 2.1: An example of how the maximum test parallelism is determined
At one point in a test program, all the connection pins need to be connected to the tester, but for a significant portion of the test program, this is not the case. For that part of the test program, only a subset of the pins has to be connected, so this part of the test program can be done with higher parallelism. This means that a single test can be split into two tests, where the second test is being done at higher parallelism. This results in a lower net test time. Figure 2.2 shows how a single insertion policy works, the lot is tested once per test program with low parallelism.
Full pin means that all the connection pins are connected to the tester, this results in a low test parallelism. The Chevron bar represents a single test. Figure 2.3 shows the same test program but split up into two separate tests. The second test is a min pin test, this means that the minimal number of connection pins are connected to the tester resulting in the highest possible test parallelism. The split insertion strategy results in a lower total net test time.
Full pin test on a low test parallelism
Figure 2.2: A single insertion test policy
Full pin test on a low test parallelism Min pin test on a high test parallelism
Figure 2.3: A split insertion test policy
The split insertion policy has also downsides. Splitting a test program into two means that the total number of tests is doubled. This means that if a product is temperature tested, which normally happens with a hot temperature test and a cold temperature test, the product now has to be inserted four times instead of two times. This means more changeovers, which could result in higher cycle times. Due to the higher number of changeovers, the testers have higher idle times which results in a decrease in machine efficiency. With a split insertion policy, the second test is being done at higher parallelism. In order to achieve this, extra load boards need to be developed due to the fact that the load boards are different than the full pin test load boards. More sockets need to be added to the load board due to the increase in parallelism.
This increases the complexity of the load boards. The development and production of these load boards result in the test costs going up.
The changeover times between the different test programs are important for insertion policy problem, because they cause the most downtime for the testers. The split insertion policy has four test programs: cold and hot min pin test and cold and hot full pin test. This means that on this policy there are 16 possible changeovers with 16 different changeover times. Within those 16 possibles, there are three types of changeovers. The first type is a changeover in which the next test program is the same as the current test program. This changeover takes the shortest amount of time, because nothing has to be changed on the tester. The second type is a temperature changeover on the same load board, for example, a cold min pin to hot min pin. This changeover takes longer due to the temperature change of the tester. Depending on the current test program and the next test program, the tester needs to cool-down or warm-up. The final type is a changeover in which the load board needs to be changed. This happens when a switch is being made from a min pin test to a full pin test or vice versa. This type of changeover has the longest duration of all the changeovers.
Table 2.1 summarizes the trade-off of using each of the insertion policies.
Table 2.1: The trade-off between the different insertion policies Performance parameter Single insertion policy Split insertion policy
Net test time Higher Lower
Number of tests per test program 1 test 2 tests
Changeovers Less More
Time consuming changeovers Limited hardware change
so short changeovers Changeovers more time consuming due more hardware change
Tester efficiency Higher Lower
Load board usage Minimal load boards required More and complexload boards needed
NXP Graduation thesis Problem definition and research questions