STWW project
KULSAT 1: Building blocks for future
LEO-satellite terminals
1.1 Introduction and overview...4
Workpackage 1000: electronic beam steering...5
Workpackage 2000: AD converter...6
1.2 WP1100: detailed study of literature...6
1.3 WP 1210: type of antenna (technology)...7
1.3.1 Choice of antenna topology...7
1.3.2 Simulation of the antenna element...7
1.4 WP 1220: passive or active elements...11
1.5 WP 1230: type of array...12
1.5.1 Minimising coupling...12
1.5.2 Exploiting Coupling...16
1.5.3 Modeling of the Array on a Finite Ground Plane...19
WP 1240: type of beam steering...24
1.5.4 General introduction...24
1.5.5 RF phasesteering...25
1.5.6 IF phase steering...27
1.5.7 Baseband techniques...28
1.6 WP 1250: type of phase shifters...31
1.6.1 Baseband processing...31
1.6.2 RF processing: QAM modulation of received signal with DBMs...31
1.7 WP1300: Selection of a candidate architecture...31
1.7.1 Prototype 1: Baseband downconverter + baseband beamforming...31
1.7.2 Prototype 2: RF-phase steering...36
1.7.3 Prototype 3: 8x1 Baseband downconverter + baseband beamforming...41
1.7.4 Final implementation: 8x8 patch array...45
1.8 Technical conclusions...57
1.9 Educational demonstration set-up...57
1.10 Future (necessary) work...57
1.10.1 Power consumption...57
1.10.2 Bandwidth...57
1.10.3 Use at higher frequencies...57
1.10.4 Use under space conditions...58
1.11 Diffusion action with respect to possible users of the new beam steering technology...58
1.11.1 Within Flanders...58
1.11.2 Within Europe...58
1.11.3 Globally...59
1.12 WP2100: Architecture and design of high-speed CMOS analog to digital converter...60
1.12.1 Introduction...60
1.12.6 Layout of Matching transistors...67
1.12.7 A layout example: Layout of the ROM encoder...68
1.12.8 Realization...69
1.12.9 Measurement setup...71
1.12.10 Measurement Results...72
Table 1: ADC performance summary...73
1.12.11 Conclusion...74
1.13 General conclusions...75
1.1 Introduction and overview
It is expected that in the near future, LEO-satellite applications will become increasingly popular. In this context the KULSAT project was initiated at the K.U.Leuven. KULSAT is intended to be an independent integrated project for developing specific technology for use within LEO satellites. Independent means that the KULSAT project did not target a specific satellite (e.g. SUNSAT of the University of Stellenbosch, or PROBA of Verhaert), but studied innovating enabling technology for mini- en micro-satellite communication in general.
Within the KULSAT project, more specific two topics have been addressed.
1. The analysis and proof of concept of a new electronic beam steering concept. To this goal, many structures have been built and tested. The final prototype structure is an 8 x 8 planar array.
2. The analysis and fabrication of fast A/D-converters.
The concept of electronic beam steering for integrated planar antennas, in our view, is a technology absolutely crucial for the future. In an electronically steerable antenna, the antenna is not moved mechanically but for example in receiving mode the signals hitting the different elements are combined in such a way that the receiving beam exactly points in the direction from where the waves are incident. This technology is preferable over non-steerable antennas due to the lower power consumption, the lower electromagnetic pollution of the environment (see further), without having to degrade the performance of the system. Compared to mechanical beam steering, the most important advantages of such a system are: a. the speed by which the beam can be steered, b. mechanical movements are avoided so that the life span of the system is larger, c. once such a system can be build on a large scale with standard technology, the price per unit will be much lower than for mechanical steering.
Up to now most wireless links worked with fixed omnidirectional antennas, with sectorial antennas, or with slow mechanical single beam steering. In a world of high-performance, wide-band communication, heavily concerned with EMC (ElectroMagnetic Compatibility) and biological aspects, this is just not possible any more. Radiated power has to be minimized, without giving in performance. This is possible by using electronic beam steering. Since the main interest is in higher volume, lower-budget applications the traditional architectures for electronic beam steering in many cases are too expensive to be used. However, in the case of planar antennas, the fact that the beam steering circuits may be integrated with the antenna in a single structure opens possibilities to reduce fabrication costs drastically. The concept of electronic beam steering implemented in an integrated way with planar antenna elements in our view is one of the big challenges in the antenna design community.
The proliferation of digital computing and signal processing in electronic systems is often described as “the world is becoming more digital every day”. Compared with their analog counterparts, digital circuits exhibit lower sensitivity to noise and more robustness to supply and process variations, allow easier design and test automation, and offer programmability that is more extensive. But, the primary factor that has made digital
circuits to attain higher speed, more functionality per chip, low power dissipation or lower cost. These trends have also been augmented by circuit and architecture innovations as well as improved analysis and computer-aided design tools.
While the above merits of digital circuits provide a strong incentive to make the world digital, two aspects of our physical environment impede such globalization: (1) naturally occurring signals are analog, and (2) human beings perceive and retain information in analog form. That’s why there is lots of research on e.g. high-speed analog-digital converters.
Below, the tasks that had to be performed, subdivided into WPs, are depicted. WP 1000 is the WP on electronic beam steering of antennas. WP2000 is the WP on AD converters.
YEAR Workpackage 1000: electronic beam steering
Year 1 WP1100: Literature study
WP1200: Evaluation of existing and new architectures for electronic beam steering WP1210: type of topological technology WP1220: passive or active antenna elements WP1230: type of array
WP1240: type of beam steering WP1250: type of phase shifters
Year 2 WP1300: Selection of a candidate architecture
Year 3 WP1400: Implementation of the candidate architecture
Year 4 WP1500: Testing and fine-tuning
WP3000: Implementation of steerable antenna into single prototype
Workpackage 2000: AD converter
Year 1 WP2100: Study of and choosing suitable architecture for high speed analog-digital converter
Year 2 WP2200: Layout of analog-digital converter Tape out (CMOS technology)
Year 1-2-3 WP2300: Research Dynamic aspects
Tape out (CMOS technology)
Year 4 WP2400: Testing
WP3000: Implementation of fast A/D converter into single prototype
1.2 WP1100: detailed study of literature
Lots of basic research is focused on the development of steering algorithms. Much less effort has gone to the development of technological know-how to really build the antennas, although there has been an improvement over the last few years.
In a steered array, the phase and amplitude of each antenna element must be individually tuned in some way (using software or hardware) to create the desired radiation pattern. This is not a simple task. Part of the current research is dealing with optimal array design (off-line) using novel techniques for optimising the excitation parameters of an array. Possible design goals are pre-defined beam shapes [i] or side lobe reduction [ii].
Another hot topic is adaptive steering algorithms of phased arrays to maximise the signal-to-interference-and noise ratio [iii]. Lots of algorithmic strategies have been developed
and investigated, like null-steering, optimal beam forming, beam-space processing and such, in which not only the main lobe of the antenna array is pointed towards the desired signal, but interfering signals are being cancelled out by steering nulls towards those interferers. Algorithms currently under investigation include genetic algorithms [iv], LMS
algorithms, MUSIC [v,vi] and others.
Recent experimental studies include work done in the TSUNAMI-project [vii] and various
Some research [ix] [x] focuses on the design of low-cost building blocks for use in
electronic beam steering. The use of active antenna elements makes it possible to reduce the component count by using the active element as a mixer. Mutual coupling between antenna elements can be used for injection-locking individual oscillators, eliminating the need for phase-shifters. Switched parasitic antenna arrays offer another possibility for phase-shifter-less beam steering [xi,xii].
1.3 WP 1210: type of antenna (technology)
1.3.1 Choice of antenna topology
Comparisons of several aperture antennas, aperture-coupled patch antennas and probe-fed patch antennas were made.
At first glance, aperture antennas look promising. They are easy to fabricate and very cheap. They have one major drawback: their front-to-back ratio is very bad. This can be solved by shielding the back of the apertures by a ground plane or a cavity. This increases the complexity and cost.
Patch antennas have a cleaner radiation pattern (better front-to-back ratio), and seem therefore better suited for satellite communications.
Figure 1: Patch antenna with air dielectric.
Several patch antenna configurations were considered. Using an air layer between ground plane and patch gives the lowest achievable losses (Figure 1). This type of antenna is very well suited for integration of antenna and RF electronics.
1.3.2 Simulation of the antenna element
The antenna element was also simulated in IE3D as this simulation tool is able to take into account the finiteness of the dielectric superstrate and metal ground plane. The radiation pattern of all three, i.e. infinite superstrate and ground plane, finite ground plane and infinite superstrate and finite ground plane and finite superstrate, as well as the input matching is given in Figure 3 to Figure 6. We conclude that the finiteness of the superstrate is indeed an issue as it shifts the resonant frequency up to 2.55 GHz. When
X1 55mm
Y1 55mm
X2 40mm
Y2 47mm
Probe offset (P) 10mm
Air layer thickness 5mm
Superstrate thickness 1.575mm
Ground plane dimensions 70x70mm
Dielectric constant Circa 4.5
Loss tangent Circa 0.0012
Figure 4: Gain for the patch with finite ground plane and infinite superstrate
Figure 6: S11 for the patch with and without finiteness.
1.4 WP 1220: passive or active elements
Because the techniques that look most promising so far each introduce quite some loss in the beam forming network, an active design seems unavoidable.
Pin diode switching and variable impedance steering cause signal loss due to the losses in the non-ideal components. Baseband beamforming starts with downconverting the received signal to baseband. This step has a typical conversion loss of 10dB. Variable attenuation with Double Balanced Mixers attenuates the signal by at least 10dB in the minimal attenuation setting.
Type of phase shifter Signal loss (dB)
Pin diode switch 1 – 5
Variable impedance 2 – 3
Baseband 10
Table 1: losses in the BFN
The use of baseband or DBM phasesteering rules out passive elements. The losses in those circuits are too high. Pre-amplification of the signal is absolutely necessary. This amplification should be done as close to the antenna-element as possible. Therefore we prefer an active element.
To overcome the losses in the baseband and DBM schemes, an amplification of 20 dB seems appropriate. For demonstration purposes, a noise figure of 3 dB is acceptable.
1.5 WP 1230: type of array
1.5.1 Minimising coupling
To evaluate the suitability of the selected antenna element, a small 4-element linear array was designed. The design was optimised for minimal mutual coupling between antenna elements (Figure 7).
Figure 7: outline sketch of the 4-element linear array and feeding network X1 57mm Y1 90mm X2 40mm Y2 47mm Probe offset (P) 10mm
Air layer thickness 5mm
Superstrate thickness 1.8mm
Figure 8: Layout and dimension of the patch used in the four elements array with Butler matrices.
Figure 9: Photograph of the antenna element
Figure 10: Calculated radiation patterns
This array was built and measured. The agreement between simulated and measured results is quite good. This confirms the validity of our modelling techniques. (Figure 11). More information about this antenna can be found in a master thesis [xiii]
Figure 11: Calculated vs. Measured radiation patterns
1.5.2 Exploiting Coupling
By varying the element spacing, it is possible to make use of element coupling to enhance the gain of an array in one direction.
Suppose that identical currents are applied to the N antenna elements of an array. The maximum electric field strength of this array will be N times the electric field strength of one antenna element. But the power that is consumed when applying these currents depends on the inter element spacing as varying the element spacing will vary the electric fields at the element locations and hence vary the power that is consumed by the array. [xiv]
In terms of a receiving antenna instead of a transmitting antenna we seek for the array that accepts as little total power (side lobes and main lobe) as possible for the same gain of power coming from a certain direction of interest (main lobe). When optimizing the
a rule of thumb satellite communication is started as soon as the elevation of the satellite is higher than 10°. One thus needs to select the array that gives the highest gain at a scan angle of 80°.
A detailed study [xv] revealed that to obtain this maximal gain, the inter element spacing
should be so that the first grating lobe lies just behind the edge of the visible interval. For several values of N, the distances were calculated and can be seen on Figure 12.
Figure 12: Optimal distances
Choosing the number of elements in the array is a trade-off between cost and performance. The performance is reflected through the gain of the array and is depicted in Figure 13.
Figure 13: Gain of array
By using the array that we designed, the worst case has become less bad so that the link budget became less stringent as seen on .
Other than uniform taperings are possible as well but seem to degrade the gain so that their use is only advisable if the side lobe level should be below some threshold lower than –13 dB.
Figure 15: Gain vs. side lobes
1.5.3 Modeling of the Array on a Finite Ground Plane
The design of the array was performed under the assumption that the ground plane has infinite dimensions. In reality the size of the ground plane is finite. It is well-known that the finiteness of the ground plane only slightly affects input parameters, and the far field above the ground plane around the direction of the array main beam. However, the finite size of the ground plane does lead to back radiation under the ground plane. This radiation is incident onto the electronic circuits steering the beam and thus has to be checked.
We have implemented a numerical technique [xvi] based on a 3 dimensional physical
optics method in order to be able to model this. When applying our model to the array, in order to assess qualitatively the effects of the finiteness, we have considered an array with 8 by 8 elements located on the finite ground plane of 56 cm x 56 cm. with inter-element distance of 7.5 cm in x and y direction. The array inter-element is a cell with the same configuration (patch, probe, etc…) as the cells considered in the previous sections. We are not able to model lateral discontinuities in the FR4 substrate. In order to avoid this problem we have made the substrate homogeneous in the horizontal plane. This step should not qualitatively affect the radiation parameters of the array because these
discontinuities are located outside the patch and they are small in comparison to the cell size.
We have considered two cases:
the phase shift between array elements is zero and the main beam is normal to the ground plane,
the phase shift between adjacent elements in the y direction is 100 degrees and the main beam is about 30 degrees off normal in the E plane.
Calculated radiation patterns in the E plane and in the H plane are plotted in Figure 16 and Figure 17 for the first case and in Figure 18 and Figure 19 for the second case, respectively. The radiation patterns over the infinite ground plane are plotted by solid lines, and the radiation patterns over the finite ground plane are plotted by dashed lines. As could be expected there are no noticeable differences between the two types of radiation patterns above the ground plane in the direction of the main beam. The back radiation is below -35dB in comparison with the main beam level for the two cases. As a consequence, the array efficiency is in practice not affected by the finite size of the ground plane and the electronic circuits are sufficiently shielded from the antenna.
Figure 18: Radiation pattern of the array in the E plane with the main beam direction 30 degrees off normal in the E plane
Figure 19: Radiation pattern of the array in the H plane with the main beam direction 30 degrees off normal in the E plane
WP 1240: type of beam steering
1.5.4 General introduction
Beamforming networks can be implemented in various ways. The phase and amplitude of the signals from individual antenna elements can be influenced at different points in the receive (or transmit) chain.
The common architectures are: RF phasesteering:
Figure 20: RF phase steering
IF phase steering:
Figure 21: IF phase steering
Baseband phase steering
Figure 22: Baseband phase steering
We will now discuss the properties of these architectures, keeping following design criteria in mind:
design frequency = 2.4 GHz 100 MHz bandwidth
scalable design low noise figure
1.5.5 RF phasesteering
Both discrete and continuous techniques are known.
1.5.5.1 Discrete techniques
These are usually based on switching additional lengths of transmission line in and out of the feeder network. Switching is usually done by means of PIN-diodes. In Figure 23, part of a 2 bit beamforming network is shown. The black lines represent transmission lines, the green squares show the position and size of the antenna elements, the red squares show the position of the PIN diodes. It is already clear from this small example that this type of phase shifting requires a lot of space and is not very modular.
Figure 23: discrete phase shifter
1.5.5.2 Continuous phase steering
This is usually implemented using lumped elements with variable impedances, mostly varicap diodes. The variable impedance causes a variable reflection angle when reflecting a RF signal. Figure 24 shows a variable impedance phase shifter. The red squares represent the varicap diodes.
RFin RF out
V bias
Figure 24: Variable impedance phase shifter
The design of a variable impedance phase shifter is always a trade-off between steering range and bandwidth. In a practical implementation it is impossible to realise 360° range. Putting multiple shifters in series can solve this. This causes an increase in the component count and needed surface area, and increased signal losses.
1.5.5.3 Discussion
A common problem in both RF phase shifters is the signal loss, which is a function of the steering angle. This means the phase shifters cause in addition to (wanted) phase variations also (unwanted) amplitude variations.
1.5.5.4 Phase steering by variable amplification
Figure 26: phasor diagramme
A double balanced mixer can be used as a 4-quadrant multiplier. The combination of two 4-quadrant multipliers, two splitter/combiners and a delay line can be used as a phase shifting and variable amplification building block.
In Figure 25, the received signal is first split into two parts, one of them delayed by 90°. Any phase and amplitude variation of the original signal can now be realised as a linear combination of these two quadrature signals (Figure 26).
The properties of this type of phase shifter are: Broadband design
Easy to implement 360° steering
disadvantage: higher cost.
1.5.6 IF phase steering
Two different strategies are to be considered
1.5.6.1 RF-techniques
All RF techniques mentioned above are also usable at lower IF frequencies. The lower frequency has both positive and negative consequences. Because of the lower frequency, circuit design in general becomes easier, components are more readily available, circuit losses are lower and so on. On the other hand, delay lines become bigger (longer) and the necessary relative bandwidth increases.
1.5.6.2 LO-steering
LO steering is easier to implement than steering in the signal path. Unwanted amplitude variations are easy to compensate for. By using multipliers, it is possible to reduce the steering range of the phase shifters. A multiplication of the LO frequency also causes a multiplication of the phase differences.
1.5.6.3 Discussion
A common problem in all IF schemes, is mirror frequency rejection (Figure 28). Because each element of the array has its own mixer, each element also needs its own image reject filter. This increases costs significantly.
Figure 28: Image rejection
Finally, IF steering can increase Inter-Symbol Interference (ISI). A low IF might seem interesting from a design viewpoint, but the distortion can become too high.
30 Mbaud -> symbol = 33 ns 300 MHz -> 360° delay = 3 ns 50 MHz -> 360° delay = 20 ns
1.5.7 Baseband techniques
'Direct conversion' is a possible solution to the image reject and ISI problems in the IF techniques.
Figure 29: DC mixing scheme
Direct conversion can be seen as mixing to an IF of 0 Hz. A disadvantage of this technique is the need for quadrature conversion to be able to reconstruct the original signal from the baseband signal(s).
Phase and amplitude control is done after down conversion, usually in DSP technology.
Figure 31: DSP baseband beamforming
How much processing power do we need?
E.g.: 100 antenna elements * 2 channels/antenna * 60 Msamples/s * 10 operations/sample = 120 G operations/s
This is not feasible with readily available components.
Therefore, we are looking at ways to implement the baseband signal processing in an analogue way.
1.5.7.1 Analogue baseband processing
The phase-shifting principle is very similar to the RF DBM method. One can rotate the I and Q baseband signals by using 4-quadrant multipliers ().
Figure 32: Baseband rotation
The rotated I’ and Q’ signals are a linear combination of the original I and Q signals. Beamforming is realized by summing the rotated signals of all elements ().
1.6 WP 1250: type of phase shifters
1.6.1 Baseband processing
A broadband analogue baseband phase shifter has been evaluated. It consists of a CLC522 two-quadrant multiplier together with a regular opamp, configured as a four-quadrant multiplier. The potential bandwidth of this set up is 160 MHz.
Also, a second phaseshifter, based on a DAC8840, has been built. This is a four-quadrant multiplying DAC with a 1 MHz bandwidth. This phase shifter provides limited bandwidth, but is still useful as a technology demonstrator.
1.6.2 RF processing: QAM modulation of received signal with DBMs
Variable attenuation was demonstrated on a Minicircuits TFM-335 Double Balanced Mixer. The performance was as expected.
1.7 WP1300: Selection of a candidate architecture
Two beamforming strategies are being prototyped and compared.1.7.1 Prototype 1: Baseband downconverter + baseband beamforming
1.7.1.1 Downconverter
A 2.4 GHz direct conversion receiver was built on standard FR4 substrate. The most important properties of this receiver are:
low noise figure thanks to the integrated LNA +100 MHz bandwidth
tunable center frequency (2.1 – 2.5 GHz) 20-60 dB baseband gain
good phase and amplitude balance between I and Q channels
Size approx. 5cm x 5cm. This can probably be reduced to 4-5cm² in the next prototype.
Almost all signal traces are on the component (top) layer. The bottom layer serves as a ground plane. This layer can also be used as the ground plane of a patch antenna, to make a compact antenna-receiver-phase shifter module.
1.7.1.2 Analogue baseband phase shifter
1.7.1.2.1 Design
A baseband QAM modulator, based on a National Semiconductors DAC8840 multiplying DAC was designed.
The QAM modulator has a resolution of 8 bits on both I and Q channel, giving rise to a constellation of 65536 points.
Figure 34: constellation plot of the 65536-QAM modulator
Phase shift can be achieved by transforming (‘modulating’) the original signal to one of the constellation points on the dashed blue line representing the unity circle. A change in amplitude can be achieved by choosing points on a smaller circle.
Figure 35: phase accuracy vs. attenuation level
In case of phase steering only, the phase error is limited to less than 0.5°, with an amplitude error of less than 0.05dB.
When the modulator is also used for variable attenuation, the phase accuracy stays within 1°, and the amplitude accuracy remains better than 0.1dB over a 15 dB amplitude range. (15 dB of amplitude control is sufficient to achieve a significant level of control over the side lobes and/or nulls in the radiation pattern of the array.
1.7.1.2.2 Implementation
The DAC8840-based QAM modulator was built. The necessary buffer and summing amplifiers were added, and a suitable serially programmable interface was added.
1.7.1.2.3 Measurements
Measurements on a 100 kHz signal yielded the following result:
Figure 38: Measurement results on the 65536-QAM modulator
There is a 3.5° error between the I and Q channel. The cause of this error is not yet identified. However, this is not important, because the phase error can be taken into account when programming the QAM modulator.
1.7.1.3 2x1 array test setup.
A 2x1 test array was built and measured. Although there is room for improvement, the results are good.
Figure 39: radiation patterns of the 2x1 array
The solid lines represent simulation results, the dashed lines are the measured results. The different lines are for different values of phase shift between the elements.
1.7.2 Prototype 2: RF-phase steering
This beamforming hardware consists of a low-noise amplifier, a QAM modulator and power combiners.
1.7.2.1 Low-noise amplifier
For evaluation purposes, a noise figure of 2-3 dB seems acceptable. To overcome the losses in the next stage, the phase shifters, at least 20 dB gain is necessary. A two-stage 2.4 GHz low noise amplifier was designed with these criteria in mind. Special care was taken to minimize parasitic effects of the used components at this frequency. The complete schematic and print layout of the low noise amplifier is included in Figure 40. A prototype was built and measured. The measured noise figure was 3.15 dB, about 1 dB worse than expected. Gain was 20 dB.
1.7.2.2 Phase shifter
The QAM modulator consists of a resistive signal splitter, a 90° delay line in the Q channel, two buffering/isolating amplifiers, two double balanced mixers and a resistive signal combiner. This setup is, apart from the 90° delay line, very broadband.
Figure 40: PCB layout of the LNA
Figure 42: PCB layout of the amplifier + phase shifter
Figure 43: Photograph of the amplifier + phase shifter
A prototype was built and measured. Some inaccuracies in the first design were LNA
PHASE SHIFTERS
Figure 44: Polar transmission plot of the MBA-26
With ideal phase-linear attenuators, the polar graph of transmission as a function of DC bias should be a straight line. The mixers used here show a phase response dependent of the attenuation (Figure 44). Other makes and models of mixers are to be analyzed for future use.
1.7.2.3 Integrated design
The redesigned preamplifier and QAM modulator were combined with the probe–fed patch antenna. Schematic, print layout and photos are included in Figure 42 and . The isolation and phase offset of the two channels has improved with respect to the first prototype. The mixers were not replaced. Digital predistortion of the excitation signals however resulted in predictable behaviour and correct steering of amplitude and phase of the signals.
Two modules were built. Their behaviour was measured in the anechoic antenna measurement room. The results are promising. Beamforming was demonstrated on this 2x1 array.
1.7.3 Prototype 3: 8x1 Baseband downconverter + baseband
beamforming
1.7.3.1 Description
A second, larger, baseband prototype was built to verify the beamforming properties of this baseband technique. An 8x1 array allows verifying the generation of more complex patterns with reduced side lobes.
The RF and base band hardware is very similar to the one used in prototype1, apart from the PCB layouts and the number of channels. The antennas used in this array are simple monopoles of 2.5 cm, soldered on the downconverter PCBs with ground plane included of 2 cm by 1.5 cm.
This time, a calibration procedure was used to correct for fixed LO phase offsets and I/Q channel phase and amplitude offsets. (as seen in Figure 38). The calibration is performed at a base band frequency of 100 kHz, the mixing product of a 2.4001 GHz RF signal and a 2.4 GHz LO signal. During calibration, all but one variable gain amplifier are switched off. The remaining VGA is set to unity gain and the amplitude and phase of the resulting signal is measured.
For each antenna element this yields the calibration matrix C.
) _ Im( ) _ Re( ) _ Im( ) _ Re( channel Q channel Q channel I channel I C
The calibrated values of the array factor are then calculated using (for both I’ and Q’ signals): Q I cal Q cal I Gain Gain C inv Gain Gain * ) ( _ _
This calibration procedure only takes into account phase and amplitude offsets. It assumes there is no signal leakage when the programmable gain is set to zero.
The result of this procedure can be seen in .
Figure 47: Calibrated response of down converter + shifter/amplifier
Figure 48: 8x1 beamformer
1.7.3.2 Measurement results
The array was put in the anechoic room. An automatic calibration procedure was performed. This procedure measures LO offset between elements and phase and amplitude differences between the I and Q channels of one element.
–15 dB chebychev array factors were then programmed into the phase shifters/amplifiers, and array patterns were measured.
Some of the measurement results are shown in Figure 49 - Figure 51. The measured patterns (red) are in good agreement with the predicted values (blue). Differences between measured and predicted values can be attributed to the far from ideal monopole antenna implementation and residual reflections in the anechoic room.
Figure 49: -15 dB Chebychev array, -10°.
Figure 51: -15 dB Chebychev array, -30°
1.7.4 Final implementation: 8x8 patch array.
The final task was to build an 8x8 patch array using the base band beamforming technique developed and tested in the previous phases of this project. A lot of effort was put into creating a modular, testable design. Some rather large design changes with respect to the first, smaller prototype were made. Most of them proved to be well worth the effort, although there definitely is still plenty of room for improvements.
1.7.4.1 Antenna + receiver
The antenna element and receiver, used in previous setups, were integrated into a single module. To achieve this, the receiver layout was redone on four-layer PCB, using the bottom layer as the ground plane for the patch antenna.
Figure 52: Photographs of the receiver module.
The antenna is a rectangular patch antenna with an air dielectric. The patch is supported by an FR4 superstrate. The antenna signal is fed to the receiver through a probe. The receiver contains a low-noise preamplifer, downconverter and LF amplifiers. The LO signal for the receiver is fed through a short coaxial cable. The supply voltage, gain control voltage, LNA on/off voltage towards the receiver board and the received signals from the board are transported through a short CAT5 cable with RJ45 connectors.
Figure 53: Schematic of the downconverter
The phase shifters use the technique described in paragraph 1.7.1.2, but were completely redesigned, using Analog Devices MLT04 four-quadrant analogue multipliers. This allows for a 16 MHz channel bandwidth, significantly more than the previous version (2 MHz) using the National Semiconductors DAC8840 digitally programmable multipliers. Unfortunately, this new device requires far more peripheral circuitry, increasing the complexity and size of the design. However, by the time the new design was finished, Analog Devices introduced a new range of faster digitally programmable four-quadrant multipliers which would greatly reduce the complexity of the design.
One multiplier building block now consists of a 10-bit DAC (Maxim MAX5841), an opamp for matching the output levels of the DAC to the input levels of the analog multiplier (one section of a TL072), and the analog multiplier (one section of an MLT04). A phaseshifter block consists of four multiplier blocks. Four phase shifter blocks are combined onto one PCB and process the signals coming from four antenna elements. Four processed quadrature signals are summed in an LM6172 opamp before leaving the board.
1.7.4.3 Signal combiner (2).
On the combiner board, the signals coming from the processing boards are all summed into the final signal by another LM6271 opamp.
1.7.4.4 Power and LO distribution
Figure 56: Power and LO distribution PCB.
One PCB contains the power distribution and LO splitting electronics. Power is fed to the other PCBs through CAT5 ethernet cable, LO is distributed through coax cables.
1.7.4.5 Interfacing + communication.
All DACs are interfaced through atmel at89c4051 microcontrollers. Each first-level combiner board contains an individually addressable controller, connected to a TTL-level shared RS-232 bus. This controller is able to relay the multiplier values directly to the DACs (direct mode) or send one of a set of pre-programmed set of values (memory mode).
1.7.4.6 Assembly
The final assembly is done on a 70 cm x 70 cm plexiglass board. On the front side are all the antennas/receivers, on the back side are the signal processors, combiners, power supply and so on. Apart from the power supply itself (a standard PC supply), the whole antenna system is self-contained.
Figure 57: Assembly of the eight-by-eight array.
1.7.4.7 Measurement results
This array was again put in the anechoic measurement room, and selected patterns were programmed and measured to verify the correct functioning of the array. An explanation for the non-symmetrical patterns must be found in reflections in the room. The difference in side lobe levels for Chebychev tapering is due to finite ground planes.
1.8 Technical conclusions
From a literature study, it was seen that a specific form of electronic beam steering was never reported on. The technique involved steering in base band, based on a quadrature baseband phase shifting. The architecture was investigated and a steerable prototype array of 8 by 8 elements was designed and built. The system functions as expected, delivering the proof of concept of this new architecture.
1.9 Educational demonstration set-up
Since each element can be steered completely independently, just by programming it via a PC, the 8 x 8 array built is extremely flexible. It is ideal for incorporation in a demo. With this demo, not only the (new) concept of electronic beam steering can be demonstrated, but also the basic properties of electromagnetic waves.
Part of the KULSAT project has been indeed to upgrade the antenna prototype so that it becomes part of an integrated demo. This demo will be operational during the Open Door Days of our department.
1.10 Future (necessary) work
Within the KULSAT project a proof of concept for a new way of electronic beam steering was delivered. In order to make this concept attractive for commercial applications, further research is necessary. This research is less fundamental, and more focused on the optimization of the architecture, sub-topologies used, and components, in relation to the intrinsic advantages. Apart from the reduction of costs, which is mandatory for commercial applications, the following points have to be addressed in detail:
1.10.1 Power consumption
It is essential to investigate in detail how much power the new concept requires in comparison to other beam forming techniques. This is also related to 1.10.4, because in space, this information is crucial.
1.10.2 Bandwidth
At this moment, the bandwidth of the prototype is limited by the bandwidth of the components and subsystems used. Inherently, the bandwidth of the concept is much larger. A detailed survey has to be made concerning the specific sub-architectures used in our topology. It is perfectly possible that small changes will allow the use of other, more broadband, commercially available components. Since the bandwidth is one of the advantages of our architecture, this issue is crucial.
1.10.3 Use at higher frequencies
The concept itself is not linked to a certain frequency. The issue whether it can be used at higher frequencies depends on the components and subsystems available at these higher frequencies. This has to be investigated.
1.10.4 Use under space conditions
A fundamental decision has to be made here. A first option is to use only space-qualified components. A first study was made within the KULSAT project itself. It turns out that the use of space-qualified components increases the costs enormously.
However, in many cases, under LEO satellite conditions, it is not necessary to use only space qualified components and materials. An example is the SUNSAT satellite. In this satellite a compromise is made between using space qualified components, application of special techniques (for example shielding of certain components from the severs space conditions) and just observing in practise that many cheap “down to earth” components actually perform very well in space.
1.11 Diffusion action with respect to possible users of the new
beam steering technology
At the end of the project several possible industrial partners were approached in order to investigate the possibility of follow-up projects to bring this concept further to the market. The developed beam steering technology was presented to them.
1.11.1 Within Flanders
A sector that could benefit directly from this research is the sector involved in space and satellite applications. Although they are not performing the design of antennas, in general several Flemish companies are using space technology to build applications involving satellite communication (Alcatel, Verhaert, SAIT, Newtech, VRI, …). They hope to play an important role in the near future in the development of LEO satellite networks, which is expected to become a growing market. For the communication with these satellites, cheap and flexible LEO-satellite terminals are necessary. The application of electronic beam steering and high speed data conversion interfaces will be crucial technologies in the development of these terminals. The development of the new steering concept offers them an alternative to existing expensive solutions. Since these Flemish partners aren’t really antenna companies, they were interested to use the existing and newly developed expertise of TELEMIC in new projects, where TELEMIC could operate as the “antenna”-partner. One of the concrete results of the KULSAT project in this respect was the question of Verhaert to ESAT-TELEMIC to be involved in a consortium to make a proposal for the ARGOS mission.
The KUL spin-off company OMP is involved in the design and production of cheap single-element antennas and very small arrays. The new beam steering was introduced to them, but presently, this type of antennas is too complicated in regard of the basic strategy of the company.
1.11.2 Within Europe
Contact was established with THALES Nederland. This company is heavily involved in the development of radars. They were invited to our premises where the concept was introduced and discussed. The result was the following. Since they are not really involved
The new beam steering concept was reported on within the context of the FP6 ACE NoE (Network of Excellence) of the EU. There it was part of the inventory established and compared to other beam forming techniques.
1.11.3 Globally
As this concept of a modular antenna with a phase shifter that does not suffer from signal discontinuities is a promising candidate for micro-satellites in LEO, the team working on the SUNSAT satellites is very much interested in cooperation. The phased array has the advantage that no vibrations occur that could lower the resolution of an imager for earth observation. And the avoidance of discontinuities in the signal allows getting higher bit rates, as in the case of switching in the signal path, during scanning a lot of symbol errors would occur. Therefore, a mission from KUL to Stellenbosch was organized, where the concept was introduced and discussed, both with the university groups involved in the SUNSAT projects, and with the company SUNSPACE. A Memorandum of Understanding was signed concerning cooperation: either party would look for national funds in order to be able to incorporate the new beam steering concept in the new satellites to be developed.
1.12 WP2100: Architecture and design of high-speed CMOS
analog to digital converter
1.12.1 Introduction
High-speed A/D converters used in automated test equipment, oscilloscopes and in digital data reading (e.g. hard disk drives and DVD) require very high sampling speeds, whereas resolutions as low as 6 bit are sufficient. Also, the enhanced capability of digital signal processing (DSP) circuits pushes the design of A/D converters towards ever-increasing sampling speeds.
Not only the sampling speed is going up, also the maximum input frequency which has to be converted increases. Therefore, bandwidth-, distortion- and error rate- specifications are of utmost importance. Error rate is an aspect in the design of high-speed A/D converters which is often overlooked or underestimated. When the error rate is extremely high, the digitized waveform appears to disintegrate and the signal-to-noise ratio (SNR) deteriorates rapidly. Since the error rate increases exponentially with the acquisition frequency, the meta-stability errors might increase by orders of magnitude for very high speed converters. Therefore, to achieve a good performance at high frequencies the problem of metastability must be tackled.
Flash-type architectures are typically the simplest and fastest structures that can be used to implement these very high-speed A/D converters [xviii,xix,xx,xxi]. Figure 58 shows the
detailed block diagram of the implemented flash A/D converter. Because of the difficulty of implementing a high-speed sample-and-hold, the input is applied directly at the gates of the pre-amplifiers. The resistive ladder divides the converter reference voltages in a set of2 reference voltages (with n the number of bits of the A/D converter), which aren compared in parallel with the analog input signal. A logic encoder converts the thermometer code generated by the comparators into a Gray code. Not shown in this schematic are the output-drivers after the dynamic latches.
Figure 59 shows the detailed schematic of one of the 63 slices of the implemented 6 bit ADC. The schematic has been divided into three parts: the pre-amplifier, the comparator and the nand-gate. The output Siselects one of the 63 ROM-lines.
Figure 59: Detailed Schematic Slice A/D Converter
Next section deals with the design of the different building blocks of the slice shown in the figure. After this section, measurement results are shown, followed by an introduction to the layout of this high-speed analog to digital converter.
1.12.2 Building Blocks
1.12.2.1 Resistive reference ladder and pre-amplifier
To reduce the input-referred offset and kickback noise from the comparator, a pre-amplifier is put in front of the comparator. The pre-pre-amplifier amplifies the difference between the input voltage and its reference voltage. The reference voltages are generated by a resistive ladder. The ladder network divides the converter reference voltages in equal reference voltages for each pre-amplifier, which should be constant under all conditions. One important source of errors in flash A/D converter is caused by the capacitive feed-through of the high frequency input signal to the resistive reference-ladder.
C R
Vinput Rtot = 64* R Ctot = 64* C
This is shown in Figure 60. Consequently, the voltage at each tap of the ladder network can change substantially from its nominal DC value, degrading the converter performance especially at high input frequencies. The feedthrough to the midpoint of the ladder (worst case point) is given by [xxii]
RC f V V IN IN MID 4
(1)
Typically, resistance is scaled down to achieve a small feedthrough to the reference ladder. This can lead to a considerable power-consumption in the reference ladder network (for high input frequencies).
In addition, the matching of the different resistors in the ladder network is very important, since it directly influences the differential and integral non-linearity of the converter. The pitch of the comparator, which is minimized to reduce the effects of clock- and signal-skew, sets the length of the ladder elements. This matching demand and the maximum resistance value given by the feedthrough problem determine the width of the resistors.
1.12.2.2 Preamplifier
The pre-amplifier consists of an optimized differential amplifier with resistances as load. To achieve good performance metrics over the whole input-range the bandwidth of the pre-amplifier must exceed the highest input frequency by almost a factor of 5 [Error: Reference source not found]. This is due to the problem of variable signal delay caused by the parallel structure of the different comparators (also called dispersion [Error: Reference source not found]). This is an inherent problem of flash A/D converters without front-end sample-and-hold. Suppose the A/D input is a large, high frequency sinusoidal signal. Each pre-amplifier “sees” a different section of the sinusoid and so there is a large variation in slope seen by each pre-amplifier. Each pre-amplifier can be modeled by a first-order RC network. The response of such a first network differs for different input slopes. This difference in comparator-delay leads to a third order distortion, which can limit the SNDR of the high speed converter if the bandwidth of the pre-amplifier is not high enough.
A formula has been derived by R. Vdpl. for the resulting third order distortion as a function of the internal poles of preamplifier stages. Although the given formulas were derived for bipolar preamplifiers, similar equation can be derived for CMOS amplifier stages. The results of these calculations are depicted in Fig. 21 for a targeted third order distortion, the oversampling ratio Preamplifier Bandwidth/Input Frequency can be determined, given a choice of Vgs-Vt .
Figure 61: Third order distortion as a function amplifier bandwidth/input frequency for a given Vgs-Vt
In this design, a Vgs-Vt of 0.3 V was chosen, resulting in a Preamplifier Bandwidth/Input Frequency ratio of 3. Which means that for a sampling speed of 1GS/s (Nyquist rate 500 MHz), the internal poles of the preamplifier should be located above 1500MHz, in order to have 50dB 3rd order distortion (>6bit). Which implies that only a phase shift of 12 is admissible at Nyquist frequency:
18,4 3 1 atan NYQUIST 1.12.2.3 Regenerative Comparator
After the pre-amplifier, the comparator regenerates the amplified input difference into valid digital logical levels. The comparator used in this flash converter is a very fast regenerative structure. During one clock phase, the comparator is reset at the same time that the clocked differential pair composed by transistors M3A and M3B injects a current imbalance in the regeneration nodes proportional to the pre-amplifier output signal. In the next clock phase, the voltage imbalance that exists between the two regeneration nodes is amplified by the nMOS and PMOS regeneration loops to digital levels. In this way a sample-and-hold is not required, which allows this architecture to achieve the highest acquisition speed. The regeneration speed is governed by a positive pole approximately given by eq M M REG C g g p 5 6
(2)
Note that both the nMOS and pMOS regeneration loops contribute with transconductance and parasitic capacitance to the definition of this pole. In this design, the
transconductance and capacitance of nMOS and pMOS have been made equal, to maximize the very high acquisition speed obtained with this converter.
1.12.2.4 Digital Backend and Error Correction
As stated in the beginning, error correction is very important to achieve good resolution at high input frequencies. The purpose of the digital backend is to convert the comparator outputs into a 6-bit code word and to reduce the effects of errors. Under perfect conditions, all comparator outputs below the input level are one and vice versa (thermometer code). Under such conditions, the thermometer code can easily be converted into a binary code by transforming this code in a 1-of-n code followed by a ROM with a binary pattern. A flash converter with this type of structure typically suffers from two problems: bubbles (or sparkles) in the thermometer code and meta-stability [Error: Reference source not found][Error: Reference source not found][xxiii]. These two
problems will be discussed now. Bubbles
Timing differences between the clock lines and signal lines can cause the effective sampling moments between comparators to be different. This can cause a bubble in the thermometer code where a one may be found among zeros and vice versa. A number of circuit techniques are used to suppress these bubbles. These techniques fall into three categories: first, preventing bubbles from occurring, preventing it from propagating towards the ROM and third, choosing a ROM coding scheme to minimize the resulting error at the ADC output (if the bubble still propagates). Therefore the comparators-layout is done very carefully to minimize the skew (reduces first problem). Secondly, a three-input nand-gate is used after the comparators to prevent a bubble from propagating to the output and third a Gray-encoded ROM is used to minimize the error at the output (see Figure 58).
Meta-stability Error Reduction
Meta-stability in a flash converter can occur when the applied input signal is very close to one of the reference voltages. In this case, the comparator might be unable to toggle to a valid logic level. Therefore, the logic gates driven by that comparator output might interpret the input as different levels. As a consequence, zero, one or two ROM-lines might be selected leading to severe errors in the digital output code. The most effective way of reducing the metastability errors is to increase the positive regenerative pole. Although this provides an efficient way of reducing the error rate, other approaches have been used to reduce the metastability errors even further and to make the converter degrade gracefully in the presence of an error.
One possible approach consists in introducing pipelined latches immediately after the comparator outputs and before the logic decoder, increasing the regeneration gain of the comparator. However each pipeline stage needs2n 1latches, increasing the die area and power consumption. An other approach consists of using Gray-encoded ROM’s, which is
Figure 62: Error Propagation in Gray / Binary Encoded ROM
The output of the ROM is the logic-OR function of the two lines (if both X are one). In the case of the binary ROM, this leads to severe output errors and degradation in the SNDR of the converter. With a Gray-encoded ROM only one bit is wrong and this can be digitally recovered. However, if none of the ROM lines is selected, the Gray-ROM output bits are all one since they are determined by the ROM pull-up network, leading to a severe error in the output code. It can be concluded from the previous discussion that a Gray-encoded ROM is an effective solution to reduce the metastability errors caused by an undecided comparator if the case of having no lines selected is eliminated by design [5]. In this design, this is guaranteed by construction by putting two CMOS inverters at the output of the comparator (see figure 23, detail of figure 19). The ratio between the size of the pMOS and nMOS transistors used in this inverters has been made higher than the ratio between the size of PMOS and nMOS transistors used in the regenerative comparator. Consequently, the threshold voltage of the inverters is higher than the threshold voltage of the comparator. This means that when the comparator remains undecided, the outputs of the comparator are at the metastable state and therefore the output of the inverters is a logic one.
Vout1 Vin1 Vout2 Vin2 C O M P A R A T O R Vout Vin Reset Regeneration
Figure 63: Avoiding meta-stability errors with a circuit that always ensures one logic level and its corresponding signals
1.12.3 Total Flash Simulations
Simulations have been done to have an idea of the overall specifications of the A/D converter. The input frequency is 104 MHz and the clock frequency is 1 Ghz. SFDR is well above the 36 dB. Several distortion sources are becoming dominant at these frequencies.
1.12.4 Introduction to layout of the high-speed analog to digital
converter
The targeted technology is the 0.35 micron technology from Alcatel Micro-electronics. The aim was to have a semi-automated layout of this converter. The critical parts (e.g. comparator) were laid out manually whereas the non-critical parts were generated automatically. This can be done because of the modular structure of a flash analog-to-digital converter e.g. ROM layout… .This automation reduces the time for the layout drastically and also the possibility for faults.
In the layout thus fare, we used two layout programs which where made in house (MICAS laboratories) :
Transistor Generator Module, used for the layout of the transistors
Modular Structure Generator, Mondriaan, used for the layout of the modular structures in the design (ROM encoder and clock generator)
INPUT frequency DC of the input Harmonic Distortion
1.12.5 Important Layout Issues
Some very important layout issues, which can determine the overall performance of the converter are listed here:
Clock Distribution on chip (Delay)
Equal paths for equal signals (Distortion possibility) Electro-migration
Cross-talk between analog and digital parts on same chip Layout of matching transistors (see further)
Influence of bonding wires on design (inductance)
Influence of bonding pads on design (resistance and capacitance)
1.12.6 Layout of Matching transistors
Because some transistors must be made equal as much as possible, this is reflected in the layout of the matching transistors. Several things can be done to improve this matching. In the layout of analog transistors it is important to have a:
Accurate aspect ratio Reduced gate resistance
Reduced parasitic source and drain resistance Figure 64 shows a layout of an analog transistor.
For wide transistors, it is preferable to split them into several smaller, but parallel, transistors (stacked configuration). Other important aspects are shown in the following pictures.
Also the biasing of the transistors must be as close as possible to the transistor itself as shown in next picture.
1.12.7 A layout example: Layout of the ROM encoder
Because the ROM lines are rather long, it is preferable to have a very small capacitance from each rom transistor. Therefore the transitor was folded around its drain contact area
The layout of the total ROM encoder was done with the aid of the Modular Structure generator Mondriaan.
1.12.8 Realization
The designed analog to digital converter was layouted in a 0.25 µm CMOS technology. The active area of the chip is only 0.12 mm² which is almost equal to the area of the smallest available 6-bit converter in 0.18 µm technology[xxiv] and much smaller than
comparable ADC’s in 0.35 µm technology (0.8mm²)[xxv]. The power supply for the
analog part is only 1.8V and so this ADC has the lowest analog power supply reported for high-speed 6-bit CMOS converters (1.95V in [Error: Reference source not found] and 3.3V in [Error: Reference source not found]). A die photo of the chip is shown below in Figure 64. One can clearly see the reference ladders on the left, next to it the parallel array of preamplifiers and comparators and the digital backend with the output drivers on the right. A large portion of the chip is decoupling capacitance (0.5nF) as needed to avoid that ground and power bounce effect degrades the performance.
1.12.9 Measurement setup
Figure 66: photograph of the die mounted in a shielding box
Figure 67: schematic diagram used for the measurement
The die is mounted on a ceramic substrate inside of a cupper shielding box. The connections to the output consist of Al with low resistance. The only extra components needed are 100nF decoupling capacitors. For the low frequency signal range (~ 30MHz) the output signal from a Waevek Model 162 Function Generator was applied. The high frequency range was covered by a HP 83732B (10 MHz .. 20 GHz) signal generator. Clock signals were generated by a 3GHz HP 8133 pulse generator and Signal analysis was done with a HP 16500B. The output from this Logic Analyser was inported in a Matlab script.
1.12.10
Measurement Results
The maximum measured INL for the converter is 0.8 LSB. The DNL of the converter is shown in fig. 29 and is normally 0.4258. All transistors were either standard NMOS or PMOS transistors. The complete circuit, including clock buffer, output drivers, reference generation circuits, consumes 600mW at full speed. Large decoupling capacitance values are used to achieve the specifications.
Figure 68: DNL
The dynamic performance of the ADC is shown in the first figure where the SNDR (signal to noise plus Distortion Ratio) is plotted against the clock frequency. In the second plot of figure 30 the SNDR is plotted as a function of the input frequency for a fixed clock frequency. As can be seen on the figure, the degradation for frequencies near the Nyquist frequency is less than 4dB.
Figure 69: measured SNDR performance for implemented ADC
The ADC specifications are summarized in following table:
Parameter unit target value measured value
STATIC Resolution N # 6 bits 6 bits
INL / DNL LS 1 / 0.5 0.8 / 0.42 DYNAMIC SFDR dB SNDR (Fin=500MHz) dB > 30 dB max 32 dB Sampling frequency MS/S 1300 1300
ENVIRONMENT Conversion - 1 code / clock 1 code / clock
Power V 1.8 / 2.5 1.8 / 2.5
Digital levels - CMOS /
GRAY
CMOS / GRAY
OPTIMIZATION Power mW min 600
Area mm min 0.12
1.12.11
Conclusion
The systematic design and the measured results have been achieved for a low-voltage, high-speed CMOS analog to digital converter. The maximum sampling speed is 1.3GHz and the SNDR at 500MHz is 32dB. The analog supply voltage is only 1.8V. This is one of the lowest published analog power supply used to implement high-speed 6-bit CMOS ADC’s. Several design issues have been discussed and used in the optimization procedure of the ADC (e.g. output pole preamplifier, comparator speed…). It is shown that low-voltage design of high-speed ADC’s is feasible in deep submicron CMOS technologies without sacrificing the maximum conversion speed.
1.13 General conclusions
The KULSAT project has provided the proof of concept of a new way of electronic beam steering. As far as we know, up to now this technique has never been prototyped or even reported on in literature. The new concept is based on quadrature baseband phase shifting. A prototype steerable antenna array of 8 by 8 elements was designed and built, using the new phase shifting technique. This final prototype is a modular system. It is entirely functioning as expected.
In order to make this concept attractive for commercial applications, further research is necessary. This research is less fundamental, and more focused on the optimization of the topologies in relation to its intrinsic advantages.
The design of a fast DAC has been successfully finished. It is clearly shown that low-voltage design of high-speed ADC’s is feasible in deep submicron CMOS technologies without sacrificing the maximum conversion speed.
1.14 Publications on this research
G. A. E. Vandenbosch, P. Delmotte, and M. Vrancken, “The Magmas framework: architecture and capabilities for the analysis and design of multilayered antenna structures”, 26th ESA Antenna Technology Workshop on Satellite Antenna Modelling and Design Tools, ESTEC, Noordwijk, The Netherlands, 12-14 Nov. 2003
V. Volski and G. A. E. Vandenbosch, “Compact Low-Cost 4 elements microstrip antenna array for WLAN”, Proc. of the European Microwave Conference EuMC 2004, Amsterdam, The Netherlands, Oct. 2004.
V. Volski and G. A. E. Vandenbosch, “Comparative analysis of the diffraction a semi-infinite dielectric slab and a semi-semi-infinite grounded dielectric slab”, accepted for presentation at the 5th International Kharkov Symposium on Physics and Engineering of Microwaves, Millimeter and Sub-millimeter Waves (MSMW-04), Kharkov, Ukraine, 21-26 June 2004.
P. Delmotte and G. A. E. Vandenbosch, “An analog implementation of a baseband beamformer”, Proc. of the European Microwave Week EuMW 2003, Munich, Germany, Oct. 2003.
V. Volski and G. A. E. Vandenbosch, “Numerical analysis of the back radiation of a linear microstrip antenna array on a finite ground plane”, Proc. of the International ITG Conference on Antennas 2003, Berlin, Germany, Sep. 2003.
P. Delmotte, W. Aerts, and G. A. E. Vandenbosch, “An analog implementation of a baseband beamformer”, submitted for publication in IEEE Trans. Antennas Propagat., May 2004.
X.-H. Shen, P. Delmotte and G.A.E. Vandenbosch, "Enhancing the gain of microstrip antennas at different frequencies with one substrate-superstrate structure", Microwave and Opt. Techn. Lett., vol. 27, no. 10, pp. 37-40, 5 October 2000.
W. Aerts and G.A.E. Vandenbosch, "Gain Enhancement by Optimizing Interelement Spacing in Linear Array Antennas", Microwave and Optical Technology Letters, vol. 43, no. 4, p.320-324, 20 November 2004.
W. Aerts and G.A.E. Vandenbosch, "Optimal Inter-Element Spacing in Linear Array Antennas and its Application in Satellite Communications", 34th European Microwave Conference, Amsterdam, The Netherlands, pp. 1401-1403, 12-14 October 2004.
