Eindhoven University of Technology MASTER Towards transport on topological surface states in PbSnTe nanowires van de Sande, V.

MASTER

Towards transport on topological surface states in PbSnTe nanowires

van de Sande, V.

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2020

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surface states in Pb _1−x Sn _x Te nanowires

by

Vince van de Sande 0859386

Supervisors: M. Hoskam, S. Schellingerhout, D. Vakulov, E.P.A.M. Bakkers

Master’s thesis

Department of Applied Physics

Eindhoven University of Technology

Final presentation: August 10 2020, 15:00

Lead tin telluride (Pb_1−xSn_xTe) is an alloy of the topological crystalline insulator (TCI) SnTe and the trivial semiconductor PbTe. The advantage of Pb_1−xSn_xTe is that the large hole concentration in the bulk can be reduced by tuning x, while staying in the TCI phase. By depleting the bulk charge carriers using the field effect (pinch-off), transport through the topological surface states might be possi- ble. Based on the metal-oxide-semiconductor (MOS) capacitor system, we define a model for the depletion of Pb_1−xSn_xTe using different gate geometries. We pre- dict that it is possible to achieve pinch-off for x < 0.4 using a 100 nm SiO₂ back gate, and for x < 0.6 using a 10 nm Al₂O₃ top gate. Single crystalline Pb_1−xSn_xTe nanowires were grown with molecular beam epitaxy (MBE). MOSFET devices were fabricated from nanowires with different growth parameters to characterize the elec- tronic properties of MBE-grown Pb_1−xSn_xTe and determine the topological phase transition point. The transfer characterization of Pb_1−xSn_xTe nanowires with vary- ing x using a SiO₂ back gate shows that increasing x shifts the doping from lower p-type/n-type and intrinsic to far p-type. Pinch-off was achieved for both p-type and n-type Pb_0.911Sn_0.089Te nanowires. The carrier density p and mobility µ for the p-type nanowire are p = 2.031 · 10¹⁸ cm⁻³ and µ = 0.5217 cm²/(V · s). For n-type:

n = 8.156 · 10¹⁷ cm⁻³ and µ = 5.806 · 10² cm²/(V · s). For higher x (0.389, 0.394, 0.418 and 1) the back gate can not achieve pinch-off due to the increased carrier density. For Pb_0.611Sn_0.389Te the back gate in combination with an Al₂O₃ top gate is not enough to achieve pinch-off. The Sn/IV ratio from the temperature dependence of the resistance of Pb_0.606Sn_0.394Te is x_transport = 0.363. Schottky contact forma- tion at the metal-semiconductor interface makes the determination of the resistance difficult for Pb_1−xSn_xTe nanowires with relatively low x (0.029 and 0.089).

1 Introduction 5

2 Theory 9

2.1 Topological materials . . . 9

2.1.1 Topological invariants and symmetries . . . 9

2.1.2 Bulk-boundary correspondence . . . 10

2.1.3 Topological insulators . . . 10

2.1.4 Topological crystalline insulators . . . 11

2.2 SnTe and PbTe . . . 13

2.2.1 Crystal structure . . . 13

2.2.2 Topology and surface states . . . 14

2.2.3 Native defects and doping . . . 15

2.2.4 Pb1−xSnxTe . . . 17

2.3 Electrical properties of semiconductor nanowires . . . 19

2.3.1 Intrinsic carrier density . . . 19

2.3.2 Doping in semiconductors . . . 19

2.3.3 Conductivity and resistance . . . 22

2.3.4 Band gap . . . 23

2.4 MOS Capacitor . . . 24

2.4.1 Field effect and depletion region . . . 24

2.4.2 Band diagrams . . . 25

2.4.3 Accumulation, depletion and inversion . . . 26

2.4.4 Capacitance derivation . . . 28

2.4.5 Dielectric materials: oxides . . . 29

2.4.6 Depletion region capacitance . . . 30

2.5 Nanowire MOSFET . . . 32

2.5.1 Transconductance, mobility, carrier density . . . 32

2.5.2 Metal-semiconductor contacts . . . 33

2.5.3 Transport mechanisms: Schottky vs Ohmic . . . 34

2.5.4 Gate characteristics Schottky barrier MOSFET . . . 35

3 Model: depletion of Pb_1−xSn_xTe 37 3.1 MOS capacitor model . . . 37

3.1.1 Assumptions . . . 37

3.1.2 Gate capacitance . . . 38

3.1.3 Total capacitance . . . 38

3.1.4 Surface potential and depletion region width . . . 39

3.1.5 Gate voltage and threshold voltage . . . 39

3.2 Pb_1−xSn_xTe properties . . . 41

3.2.1 Intrinsic carrier density . . . 41

3.2.2 Doping density, dielectric constant and electron affinity . . . . 42

3.3 Model results and discussion . . . 43

3.3.1 Maximum depletion width . . . 43

3.3.2 Depletion width vs gate voltage . . . 44

4 Methods: growth and device fabrication 46 4.1 Nanowire growth . . . 46

4.1.1 Molecular beam epitaxy . . . 46

4.1.2 Vapor-liquid-solid growth . . . 48

4.1.3 Pb_1−xSn_xTe nanowires . . . 49

4.1.4 Estimation of Sn/IV ratio by EDX . . . 52

4.2 Nanowire FET fabrication . . . 53

4.2.1 Device overview . . . 53

4.2.2 Back gate . . . 53

4.2.3 Contact pads, markers and labels . . . 54

4.2.4 Nanowire approach contacts . . . 55

4.2.5 Top gates . . . 57

4.3 Fabrication methods . . . 59

4.3.1 Ion milling of the native oxide . . . 59

4.3.2 Oxygen plasma etch . . . 59

4.3.3 Sputter deposition of normal leads . . . 60

4.3.4 Atomic layer deposition . . . 61

5 Methods: electronic transport 62 5.1 Experimental setup . . . 62

5.1.1 Experimental method . . . 63

5.2 Limitations . . . 64

5.2.1 Contact resistance . . . 64

5.2.2 Compliance and breakdown voltage . . . 64

5.2.3 Charging and temperature effects . . . 65

6 Results and discussion 66 6.1 I-V characterization . . . 66

6.1.1 Contact resistance . . . 66

6.1.2 Ohmic and Schottky contacts . . . 67

6.1.3 Determination of E_g(0) and Sn/IV ratio . . . 68

6.1.4 I-V characteristics overview . . . 70

6.2 Back gate transfer characterization . . . 72

6.2.1 Carrier density and mobility from pinch-off . . . 72

6.2.2 Devices without pinch-off and overview . . . 74

6.3 Top gate devices . . . 76

6.3.1 Breakdown voltage of Al₂O₃ . . . 76

6.3.2 Nanowire top gate device . . . 77

7 Conclusion and outlook 80

A Fabrication recipe 83

A.1 Back gate . . . 83

A.2 Contact pads, markers and labels . . . 83

A.3 Nanowire approach contacts . . . 84

A.4 Top gates . . . 85

B Supplementary data 86 B.1 Contact resistance . . . 86

B.2 I-V characteristics . . . 87

B.3 Gate sweeps . . . 88

Introduction

The basic building block of integrated electronic chips is the silicon field-effect tran- sistor (FET). These transistors have to become smaller each year, in order to keep up with the famous Moore’s law [1]. State-of-the art transistors have sizes not much larger than a few tens of atoms, on the order of nanometers (10⁻⁹ m). However, Moore’s law is starting to fail, as fundamental limits to transistor size are on the horizon, see figure1.1. Electronic transport in silicon FET is dominated by scatter- ing processes that limit the carrier mobility and lead to energy dissipation [2]. The scattering events of the electrons occur due to surface roughness, interface charges and lattice impurities, among others. Inelastic scattering presents a fundamental limit to the size and performance of transistors, as it is impossible to make com- pletely defect-free devices at the nanometer scale. As the electrical interconnects between components also decrease in size, the energy dissipation is becoming a size- able problem. Furthermore, unwanted quantum effects like quantum confinement and quantum tunneling become increasingly important at these sizes.

Figure 1.1: Nominal feature size and transistor gate length versus calendar year.

Figure adapted from [3].

A possible solution to this problem might come from the combination of the fields of topology in mathematics and condensed matter in physics, which has led to the

prediction and realization of exotic states of matter called topological materials.

The topological crystalline insulator (TCI), which is investigated in this research, is perhaps the most interesting of these materials. It has an insulating bulk, but metallic surfaces. The advantage of a TCI is that the non-trivial topology of the bulk leads to electronic transport in the surface states that is robust against back- scattering or disorder. By fabricating the material in certain geometries, the current can be forced to move in one-dimensional channels that each have a quantized value of conductance [4]. The charge carriers within these states or channels can therefore be transported without energy dissipation, which may be useful for applications in integrated circuits.

Another application of TCI that could also solve the problem of Moore’s law is topo- logical quantum computing. The quantum phenomena that are unwanted in classi- cal computing are used by a quantum computer to perform complex computations.

The major problem for the realization of quantum bits (qubits) is decoherence. The topological qubit, which uses the Majorana zero-mode as building block, is topo- logically protected against this decoherence. Combining a semiconductor nanowire with a superconductor can lead to the topological superconductor state, which is predicted to host the Majorana zero-mode [5, 6]. The advantage of using a TCI over a trivial semiconductor is that the bulk TCI gap is orders of magnitude larger than the magnetic field-induced Zeemann gap for a regular semiconductor. The chemical potential has to be tuned inside the gap, which is significantly easier for a larger gap. Furthermore, the induced pairing gap is topologically protected against non-magnetic disorder and impurities [7].

The predecessor of the TCI was first discovered by Klaus von Klitzing, when he discovered the quantum Hall effect (QHE) in 1980 [8]. QHE is an effect that occurs in certain two dimensional systems in the presence of a large external magnetic field.

The transport occurs in quantized one-dimensional channels along the edge of the material, while the bulk is insulating. It was subsequently predicted that such an effect might also occur without any magnetic field present, for electrons that are moving through a crystal lattice [9]. It was later discovered that the relativistic spin-orbit coupling (SOC) effect can lead to the so-called quantum spin Hall (QSH) state [10]. The first prediction of a 2D QSH state in a physical material came in 2006, when it was predicted that single layers of graphene can exhibit a QSH state that is robust against perturbations and disorder [11]. However, experimental ev- idence from transport measurements has yet to be provided. It was subsequently predicted that HgTe quantum wells could be used to realize the 2D QSH effect [12].

A year after the theoretical work, actual devices were fabricated (see figure 1.2a) [13]. Quantized conductance plateaus were measured in Hall effect measurements using an external gate, which demonstrates the 1-dimensional edge channels (see figure 1.2b). As this is still the only experiment that shows these properties, more convincing evidence of the QSH effect in more varied systems is still required.

(a) (b)

Figure 1.2: a) Schematic representation of a HgTe/(Hg,Cd)Te quantum well (QW) structure, including one-dimensional spin-polarized conductance channels along the edges of the device. b) Longitudinal four-terminal resistance R_14,23, of four different QW structures, as a function of gate voltage measured for B = 0 T at T = 30 mK.

The green and red curves, indicated by III and IV, have a conductance plateau close to 2e²/h, which is the conductance quantum. Figures adapted from [13].

The step from the 2D QSH to 3D topological materials was made in 2007, when the topological insulator (TI) was introduced [14], followed by the TCI in 2011 [15].

From a materials point of view, most predicted TI and TCI are semiconductors with an inverted band ordering in the bulk. The interface between the TCI and a trivial insulator (e.g. vacuum) can host gapless surface states, due to a principle in topology called “bulk-boundary correspondence”. An important requirement is that the surface has to preserve the symmetries that are present in the bulk, which are crystal lattice symmetries for TCI. Scattering can occur between different states at the surface, but the topology of the bulk ensures that the surface states can not vanish. Most TCI (and TI) materials are not actually insulating but have a large carrier density in the bulk due to defects. The surface states are difficult to resolve in electronic transport measurements because of the large bulk conductance. There- fore, convincing experimental evidence of electronic transport through topological surface states in TCI has not yet been reported.

Electronic transport of the topological surface states might be possible in Pb_1−xSn_xTe nanowires. The binary compound SnTe is predicted to be a TCI [16]. However, be- cause of the intrinsically large acceptor doping density in bulk SnTe, it is always heavily p-type. PbTe, also a group IV-VI compound, has the same lattice structure as SnTe, and can be tuned to be n-type. Unlike SnTe, PbTe does not have an inverted band ordering, and is therefore a trivial semiconductor. The ternary com- pound Pb_1−xSn_xTe, which is the main focus of this research, undergoes a topological phase transition from trivial to topological for a certain value of x [17]. By lowering the value of x, while staying above the phase transition point, the material stays in the topological phase and the hole density in the bulk is reduced. By growing the material in the nanowire geometry, the bulk-to-surface ratio of the conductance is further reduced. The nanowires are grown using molecular beam epitaxy (MBE), which is the highest purity technique available. MBE can be used to grow at low temperatures, so there will be less thermodynamical defects in the nanowires and

lower hole densities.

This research focuses on the fabrication of metal-oxide-semiconductor field-effect- transistor (MOSFET) devices from Pb1−xSnxTe nanowires with the goal of deplet- ing the bulk charge carriers using gates, which is called pinch-off. By depleting Pb_1−xSn_xTe in the topological phase, electronic transport through the topological surface states might be possible to measure. We start out by measuring nanowires with low Sn content (x), so that pinch-off is possible using a back gate and thereby determine the carrier density. From transport experiments on nanowires with in- creasing x, we aim to achieve pinch-off in the topological regime. Determination of electronic properties like the carrier density and mobility give valuable information about the growth and material quality of the nanowires.

The outline of this report is as follows. Chapter 2 provides theoretical background on topological (crystalline) insulators, in particular the materials SnTe, PbTe and Pb1−xSnxTe are discussed. Furthermore, electronic properties of semiconductor nanowires and theory of MOSFET devices is discussed, with a focus on gating.

In chapter 3 a model for the gating of Pb_1−xSn_xTe nanowires is discussed. The approach of the model is first explained, followed by the results and discussion. In chapter4, first the nanowire growth method is discussed, with a focus on the differ- ent tuning parameters for the MBE growth of Pb_1−xSn_xTe. Then an overview of the device architecture is given, followed by an in depth discussion on the fabrication of the devices. Chapter5discusses the transport methods, including the probe station setup and the experiments that were performed. In chapter 6 the results of the transport experiments are reported, followed by a discussion. Finally, in chapter 7 the most important conclusions of the modelling and transport experiments and an outlook are given.

Theory

2.1 Topological materials

The combination of topology and condensed matter in recent years has led to the discovery of different kinds of topological materials. These are exotic materials that are classified according to the value of a certain topological invariant. If this quantity is preserved in the system, then so is the topological phase of the system.

Topological materials exhibit unique quantum mechanical properties, some of which will be discussed in this section. First, topological invariants and symmetries will be discussed in section 2.1.1. In section 2.1.2, the bulk-boundary correspondence is explained. Then, in section 2.1.3, topological insulators are discussed. Finally, topological crystalline insulators, of which Pb_1−xSn_xTe is an example, are discussed in section 2.1.4.

2.1.1 Topological invariants and symmetries

A topological invariant is defined as a property of an object that is invariant under the adiabatic/continuous deformation of the Hamiltonian [18]. For systems with a forbidden energy band gap, a deformation can be called continuous when the gap does not close. Systems without an energy gap can therefore always be continuously deformed into one another. According to this definition, a trivial insulator and a semiconductor are topologically equivalent materials. When the gap closes, the value of the topological invariant changes and the system undergoes a topological phase transition. There are many different topological invariants that define differ- ent classes of topological materials. Note that a material can be topological when classified according to one topological invariant, but trivial when classified according to another. For example, SnTe has a trivial value of Z₂ topological invariant, (which is non-trivial for topological insulators), but a non-trivial value of n_m, making it a topological crystalline insulator (see sections2.2.1 and 2.2.2).

Symmetries are an important concept in topology. Symmetries lead to conservation laws that determine which topological invariant is of interest. An important example is time-reversal (TR) symmetry, which states that the system is invariant under the transformation of time reversal. Topological insulators are defined by the value of the Z₂ topological invariant, due to this TR symmetry (see section 2.1.3). Other examples are sublattice symmetry in i.e. graphene and particle-hole symmetry in

superconductors [19]. As long as the respective symmetry is preserved and the gap does not close, the value of the topological invariant remains the same.

2.1.2 Bulk-boundary correspondence

The interesting physics occurs when we take into account the boundaries of the ma- terial. The bulk and boundary of topological materials have distinct characteristic properties that are unique to the system. If the properties of the bulk are known, we can predict the properties of the boundary and vice versa. For a condensed matter system, we know whether it is topological if we know the value of the relevant topo- logical invariant. If the symmetries that determine the relevant topological invariant are conserved at the boundary of the system, we know that the boundary will sup- port topologically protected surface states. These surface states do not exist in the bulk, yet the physics of these states is determined by the symmetries and topological invariant of the bulk. This is known as the bulk-boundary correspondence [20].

2.1.3 Topological insulators

Topological insulators (TI) are materials that have an insulating bulk, but have con- ducting metallic surface states. These states are protected against back-scattering and disorder by TR symmetry. Most TI’s are semiconductors with an inverted band gap in the bulk. For trivial semiconductors, the conduction band orbital is s-like and the valence band orbital is p-like. An inverted band gap means that for the states at the top of the valence band and at the bottom of the conduction band, the p-like and s-like characteristics are switched. To achieve this, a strong spin-orbit coupling (SOC) is required. Spin-orbit coupling is a relativistic effect which couples the spin and orbital angular momentum degrees of freedom. Spin-up and spin-down electrons are mixed in real materials, so spin current is not conserved [21]. SOC is mostly strong in heavier elements, since it is proportional to Z⁴ for a given row of the periodic table, with Z being the atomic number [22]. Examples of TI are Bi₂Se₂ and Bi₂Te₃ [23].

The inverted band gap of the TI has to be smoothly connected to the band gap of the material (or vacuum) outside of the TI. This connection at the interface ensures that the bands have to cross each other at the surface of the TI. At the crossing point of the trivial and inverted bands, gapless low energy surface states exist in the TI at the interface. Figure2.1 shows a schematic representation of the interface between a TI and a trivial insulator.

The surface states are robust under local disorder/perturbations, because they are protected by the time-reversal symmetry of the system. For the simple case of a non-interacting system, the surface states are characterized by Dirac cones, and can therefore be described by the physics of Dirac fermions. Spin degeneracy is lifted for these states due to the strong SOC, and their spin is locked to the momentum, which is why they are referred to as ”helical” as opposed to ”chiral”. The number of Dirac cones on a surface can only change when the TI undergoes a topological phase transition [24].

Figure 2.1: Interface between a topological insulator (TI) (green) and a trivial insu- lator (blue). The conduction and valence bands are shows for both materials. The states near the top of the valence band and bottom of the conduction band in the TI are inverted, which is indicated by color. At the surface of the TI, there is a gapless state (Dirac cone) due to the connection between the inverted band gap and the trivial band gap. The Fermi level energy E_F is indicated with a dashed line.

When the surface states on different surfaces are brought into close vicinity with each other, they can no longer be approximated as non-interacting. This is for example the case for a very thin film of TI. The electron in the surface state at the top or bottom will have a finite probability to quantum tunnel to a surface state on the opposite surface. The surface states on opposite surfaces will hybridize with each other, resulting in both states acquiring an energy gap and the fermions acquiring a finite mass [25]. The result is a 2-dimensional TI, which is equivalent to a QSH film.

2.1.4 Topological crystalline insulators

In contrast to TIs, topological crystalline insulators (TCI) do not need time-reversal symmetry. Instead, the surface states of TCI are protected by periodic crystal lat- tice symmetries, or a combination of these with other symmetries, like TR [15].

Unlike TR symmetry, crystal symmetries can be broken on low-symmetry surface facets of the material. The bulk-boundary correspondence dictates therefore that surface states only occur on surface facets that preserve the specific symmetry of the crystal. The gapless surface states are characterized by Dirac cones, similar to surface states in TI materials.

It is furthermore possible to break the symmetry of a surface facet that normally allows gapless surface states. The breaking of crystal symmetry can be achieved by applying an external distortion using for example mechanical strain or ferroelectric- ity. When the symmetry is broken, the surface states acquire an energy gap and Dirac fermions are created that have a finite mass [26]. If the sign of the acquired mass of two surface facets is opposite, then gapless states (without mass) can still exist on the edge between these facets. The topology of the bulk then protects the states at the edges between certain surfaces, but not the states at the surface itself.

This is called a higher-order topological crystalline insulator (HOTCI). The defini-

tion of HOTCI is as follows: an nth order TCI has protected gapless modes at the boundary of the system of codimension n [4]. Here codimension means the difference in dimensions between the bulk material and the system with gapless states at the boundary (surface or edge).

2.2 SnTe and PbTe

In this section the IV-VI compounds SnTe and PbTe are introduced, along with the ternary compound Pb1−xSnxTe, which is the focus of this thesis. First, in section 2.2.1, the crystal structure and band structures of SnTe and PbTe are discussed. The topological surface states of the TCI SnTe are then discussed in section2.2.2. Next, the native defects and doping densities and their influence on transport measure- ments is discussed. Lastly, in section 2.2.3 we get to the alloy Pb_1−xSn_xTe, where it is explained how this material can be used to reduce the bulk carrier density.

2.2.1 Crystal structure

SnTe class IV-VI semiconductors have a rocksalt structure, with a face-centered cubic Brillouin zone. The valence band maximum (VBM) and the conduction band minimum (CBM) are located at the L point in the Brillouin zone, which has four equivalent valleys. PbTe, which is another IV-VI semiconductor, has the same crystal structure as SnTe, and both materials have a narrow band gap. Figure2.2a shows the rock-salt crystal structure of both PbTe and SnTe. SnTe has a band gap of E_g = 0.18 eV at 300 K and PbTe has a band gap of E_g = 0.32 eV at 300 K.

There is an important difference: the ordering of the conduction and valence bands are inverted at the L points in the BZ [17]. As can be seen from first-principles calculations in figure 2.2b, PbTe has a normal band ordering, while SnTe has an inverted band structure. The relative ordering of the L⁺₆ and L⁻₆ states is thereby switched. Since there are four L-points in the BZ, this band inversion occurs at an even number of points, so that PbTe and SnTe in the rocksalt structure are both not conventional Z₂ topological insulators. SnTe, however, is a topological crystalline insulator, which becomes apparent when the symmetries in the crystal lattice are taken into account, as explained in the next section.

(a) (b)

Figure 2.2: a) Rocksalt crystal structure of PbTe/SnTe. Adapted from [16]. b) First principles calculations of the band structures of PbTe (left) and SnTe (right).

The red (blue) dots are p orbital projections of the cation (anion). The L⁺₆ and L⁻₆ states at the top of the valence band and bottom of the conduction band in SnTe have been inverted. Adapted from [27].

2.2.2 Topology and surface states

The topological invariant that dictates the topology of SnTe is the mirror Chern number n_M [16]. In the presence of mirror symmetry, n_M is an integer topological invariant defined as:

n_M = (n_+i− n_−i)/2, (2.1)

where n_+i and n−i are the Chern numbers of the eigenvalues ±i of the Bloch wave- functions on the plane defined by the Γ, L₁ and L₂ points in momentum space, under the mirror operation M . A TCI with mirror symmetry is defined by a non-zero value of n_M. For PbTe, n_M = 0, so it is topologically trivial. The band inversion in SnTe changes the mirror Chern number for the ΓL1L2 plane in momentum space by a value of two, so that n_M = −2. SnTe is thus a topologically distinct phase from PbTe, and predicted to be a TCI.

The crystal momenta on the ΓL₁L₂ plane are invariant about the {110} mirror planes in real space. The topological surface states of SnTe are thus protected by the {110} mirror symmetry of the crystal lattice. The surface facets that preserve the symmetry with respect to the {110} plane are {100}, {111} and {110}, so that gapless surface states, characterized by Dirac cones, only occur at these facets. The number of Dirac cones varies for the different facets, depending on how the ΓL1L2

plane in the bulk BZ projects onto the surface BZ. There are four Dirac cones in the BZ of the {100} and {111} facets and two in the BZ of the {110} facet, see figure 2.3. Note that the Pb1−xSnxTe nanowires that were studied in this research have only {100} facets, which can be seen from scanning electron microscopy (SEM) and transmission electron microscopy (TEM) images in section4.1.3.

Figure 2.3: The bulk Brillouin zone of SnTe and the (110), (111) and (001) surface Brillouin zones, with the corresponding projections of the bulk L points in red. The (110) mirror plane is indicated by the grey shaded area. Figure adapted from [28].

2.2.3 Native defects and doping

The dominant defect in SnTe is the negatively charged cation vacancy (V²⁻_Sn) for both Sn-rich and Te-rich conditions [29]. It is basically a missing Sn atom in the lattice, which acts as a doubly degenerate acceptor. V_Sn²⁻ has a negative formation energy throughout the bulk gap, see figure 2.4. As a consequence, the Fermi level is pushed inside the valence band, so that the formation energy becomes positive again. This means that pure SnTe is always a heavily p-doped material, with a typical hole concentration of 10²⁰ cm⁻³. For PbTe, other defects can dominate in- stead of the cation vacancy. This is mostly a consequence of the high position of the valence band maximum, which is 0.5 eV higher than that of SnTe. PbTe can be both n-type or p-type, according to which specific defects dominate. N-type PbTe typically has an electron concentration of 10¹⁷ cm⁻³.

Figure 2.4: Density functional theory calculations of the formation energy of different native defects as a function of the Fermi level in (a) SnTe and (b) PbTe. Calculations were done for both Sn/Pb-rich and Te-rich conditions. The zero of the Fermi level is set to be the valence band maximum. The range of the Fermi level spans the bulk gap. The Sn vacancy V_Sn is negative under all conditions. Figure adapted from [29].

Due to this large p-type doping, the topological surface states are difficult to directly measure using transport measurements. The surface states are effectively screened by the large amount of bulk conductance, making it hard to distinguish between trivial bulk states and topological surface states in transport experiments. This is a common issue for most TCI materials. Angle-resolved photoemission spectroscopy (ARPES) has been used to determine the surface electronic band structure but, due to the large bulk hole concentration, the Dirac cones are difficult to resolve [30]. It is therefore important that the bulk conductance is minimized. There are a number of methods to tune this for the IV-VI compounds, where it is important to distinguish between tuning material parameters during growth and experimental transport methods. Some methods to tune the material during growth:

1. Increase the surface-to-bulk ratio of the material. This will decrease the rela- tive impact of the bulk with respect to the surface states on the conductance in the material. An excellent way to do this is to grow nanowires of the desired material. See section 4.1 for a discussion on nanowire growth.

2. Tune the IV-VI ratio of the material. This is the ratio of group IV material (Sn/Pb) with respect to the group VI material (Te) that is used to grow the compound. This effect is discussed in section 4.1.3.

3. Introduce n-type doping in the material, in order to counteract the large p-type doping in the bulk.

4. Keep the temperature during growth as low as possible, to reduce the amount of thermodynamic defects, like Sn defects.

5. For SnTe in particular, alloying with Pb can lead to lower carrier densities.

The alloy Pb_1−xSn_xTe will be discussed in the next section.

During transport measurements it is possible to use an external electric field to repel the bulk charge carriers from the material using a gate. A gate is a metal lead that is separated from the semiconductor material by a layer of dielectric material. A voltage is applied onto the gate, which induces an electric field that can repel or attract the charge carriers inside the semiconductor. This is called the field effect, see section 2.4.1. The topological surface states are robust under the effect of the electric field, but the bulk charge carriers are not. When all bulk charge carriers are depleted, it is called ’pinch-off’. However, achieving pinch-off can be challenging for materials with high carrier densities, like SnTe. The gate should therefore be as strong as possible. Some methods to improve the gating:

1. Optimize the gate design using different geometries (back gate, top gate, wrap- around gate). See section 3.1.2for a discussion on different gate geometries.

2. Optimize the gate design using different dielectric materials. See section2.4.5 for a discussion on different dielectric materials.

3. Measure at as low temperature as possible. Lower temperatures lead to lower intrinsic carrier densities in the bulk, and an increased dielectric constant.

Temperature effects on the gating are discussed in the model in chapter 3. For temperatures close to 0 K, freeze-out of donors/acceptors can occur. However, for degenerately doped semiconductors, like SnTe, this effect is negligible (see section 2.3.2).

4. The small dimensions of the nanowire make gating more efficient. A thinner nanowire is easier to deplete, see section 3.3.

2.2.4 Pb

Sn

Te

It was discussed that PbTe has a similar crystal lattice to SnTe (section2.2.1) and can be tuned to be n-type by changing the growth parameters (section 2.2.3). This means that the carrier density in the bulk of SnTe can be reduced by alloying it with Pb, to create Pb_1−xSn_xTe. Here x is the amount of Sn content relative to the sum of the Pb and Sn contents (total group IV) in the material. The doping density in Pb_1−xSn_xTe can thus be tuned by changing the value of x. Figure 2.5a shows the carrier concentrations of Pb_1−xSn_xTe epilayers for different values of x, obtained from Hall measurements in a Van der Pauw geometry [31]. The epilayers were 1-2 µm thick and grown using molecular beam epitaxy (MBE) on cleaved (111) BaF₂ substrates at 350^◦C at a pressure of 10⁻⁹ mbar. The carrier concentration switches from n-type to p-type at x ≈ 12%.

(a) (b)

Figure 2.5: a) Hall carrier concentration versus Sn content for Pb_1−xSn_xTe epilayers.

Figure adapted from [31]. b) E_g versus x in Pb_1−xSn_xTe. Figure adapted from [17].

Pb_1−xSn_xTe can thus be tuned to have different carrier densities in the bulk. How- ever, unlike SnTe, PbTe does not have an inverted band gap in the bulk and is therefore not a TCI. This means that the alloy Pb_1−xSn_xTe undergoes a transition from the topological phase to a trivial phase below a certain x, called the topologi- cal phase transition point. It has been shown in multiple experiments that, at low temperatures (between 0K and 10K), the band gap of Pb_1−xSn_xTe decreases from 0.18 eV (x = 0), becomes zero at the phase transition point, opens up again and finally becomes 0.32 eV (x = 1). Different values of x have been reported in litera- ture to be the topological phase transition point, from around x = 0.28% − 0.37%.

Due to the temperature dependence of the band gap, which increases (decreases) with increasing temperature for PbTe (SnTe) [32], the phase transition point also changes with temperature. Figure2.5bshows the band gap of Pb_1−xSn_xTe versus x for different values of temperature [17].

By tuning x to be as low as possible, but higher than the topological phase tran- sition point, the carrier density will be reduced while Pb_1−xSn_xTe remains in the topological phase. This way, it might be possible to achieve pinch-off in a TCI and directly measure the topological surface states in transport.

2.3 Electrical properties of semiconductor nanowires

In this section, some important semiconductor properties are discussed. The con- cepts in this section have to be understood in order to understand the transport experiments that were conducted. First, in section 2.3.1, the concept of intrinsic carrier density is explained. Then, the effect of doping and the temperature de- pendence of the carrier density are discussed in 2.3.2. Section 2.3.3 discusses the conductivity and resistivity. Finally, in section2.3.4, the Varshni model for the band gap is discussed, and a method to determine the value of x in Pb1−xSnxTe is put forward.

2.3.1 Intrinsic carrier density

An intrinsic semiconductor is defined as a semiconductor without doping or impu- rities. The Fermi energy E_F is then equal to the intrinsic Fermi energy E_i. An intrinsic semiconductor can only have free charge carriers by exciting electrons from the valence band into the conduction band, creating an electron-hole pair. This electron-hole pair generation can only happen when the energy is larger than or equal to the band gap. This can be thermal energy or energy gained by absorbing an incident photon. When there are defect states within the band gap, than the gen- eration can occur in multiple steps with smaller energy. The excited electron-hole pairs can recombine by emitting energy in the form of a phonon or a photon. In ther- mal equilibrium, the generation and recombination rates are equal. The (intrinsic) carrier density for an intrinsic semiconductor is then given by

n_i =p

N_cN_vexp−Eg

2k_bT



, (2.2)

where N_c and N_v are the effective density of states in the conduction and valence band respectively and E_g is the band gap energy. From a fabrication point of view, it is impossible to make a semiconductor so pure that it can be called intrinsic, because there will always be impurities in the lattice. Even so, the concept of in- trinsic carrier density is important for both the calculation of the energy band gap in section 2.3.4 and the MOS capacitor model in section 2.4.

2.3.2 Doping in semiconductors

The carrier density can be increased or decreased by many orders of magnitude by introducing doping into the material. Doping is basically adding electrically active impurities to a semiconductor [33]. There are two types of doped semiconductors.

An n-type semiconductor has donors, which are impurities that can contribute an electron to the conduction band. A p-type semiconductor has acceptors, which are impurities that can accept an electron from the valence band, thereby creating a free hole. The acceptors (donors) have a certain activation or ionization energy E_A (E_D) that has to be reached in order for them to accept (donate) electrons. An ionized donor has a net positive charge, while an ionized acceptor has a net negative charge.

The position of the Fermi energy EF inside a doped semiconductor depends on the donor density N_D and the acceptor density N_A. When E_F lies at least 3kT away from either band edge, the semiconductor is said the be non-degenerate. For a p- type semiconductor, the Fermi level will lie below Ei and will become more negative (with respect to E_i) with increasing N_A. When N_Abecomes so large that E_F comes closer than 3kT to E_c (or lies below E_c), then the semiconductor is said to be de- generate. Pure SnTe is heavily p-type, with NA ≈ 10²⁰ cm⁻³, so it is degenerate (see section2.2.3).

For a p-type semiconductor (NA>> ND), the hole density depends on temperature according to the Arrhenius equation:

p ∝ exp−E_a kbT



, (2.3)

where E_ais the activation energy for electrical conduction. The compound Pb_1−xSn_xTe transitions from n-type to p-type with increasing x. Most experiments were con- ducted for values of x for which the material is partially compensated, meaning that there is a large acceptor density, and additionally a small donor density, to reduce the hole density in the bulk [34]. Figure2.6 shows a plot of the carrier concentration against temperature for a partially compensated semiconductor. When considering the temperature dependence, three limiting cases are important [33].

Figure 2.6: Hole concentration as a function of reciprocal temperature for a par- tially compensated p-type semiconductor. Three different regimes are highlighted:

intrinsic regime, saturation regime and ionization regime (or freeze-out). The ion- ization regime is characterized by two different slopes, due to the different activation energies. Figure adapted from [34].

1. For very low temperatures we have E_a = E_A, so that equation 2.3 becomes p ∝ exp−E_A

k_bT



. (2.4)

This is called the freeze-out or ionization regime of carriers. The thermal energy is so low, that many acceptors can not accept an electron from the valence band. The donors are considered to be ionized over the entire tem- perature range, because holes prefer to occupy higher-energy donor states at all temperatures. The carrier concentration depends exponentially on tem- perature. For slightly higher temperatures, when the ionized acceptor density equals the ionized donor density, we have Ea= ¹₂EA, so that

p ∝ exp

−E_A 2k_bT



. (2.5)

Note that higher doped semiconductors have a lower freeze-out temperature than lightly doped semiconductors. For degenerately doped semiconductors, like SnTe, the freeze-out range can effectively be neglected.

2. At intermediate temperatures, we have

p ≈ N_A= constant, (2.6)

where NAis the acceptor doping density. This is called the saturation regime.

The thermal energy of the carriers is sufficient to ionize all acceptors. The carrier density is constant and equals the acceptor density.

3. At even higher temperatures, the electron-hole pair generation across the band gap becomes important, and eventually dominates over the carrier density due to doping. This is called the intrinsic regime, because the material starts to behave as an intrinsic semiconductor. We can use Ea= ¹₂Eg(0) to obtain

n_i ∝ exp−Eg(0) 2k_bT



, (2.7)

where Eg(0) is the band gap at T = 0 K.

2.3.3 Conductivity and resistance

The electrical conductivity of a semiconductor nanowire in the diffusive regime is defined as follows:

σ = 1 ρ = l

R · A, (2.8)

where ρ is the resistivity of the material, l is the length of the nanowire, R is the resistance and A is the cross-section of the nanowire. The conductivity can also be expressed using the number of charge carriers, their charge, and their mobility:

σ = peµ_h+ neµ_e, (2.9)

where p is the density of holes and n is the density of electrons in m⁻³, e = 1.602 · 10⁻¹⁹ C is the elemental electron charge, µ_h is the hole mobility and µ_e is the electron mobility in m²s⁻¹V⁻¹. The mobility is a parameter that character- izes the influence of the electric field on the velocity of a charged particle. It is related to the amount of scattering events a charge carrier encounters inside the semiconductor. The carrier mobility is further discussed in section 2.5.1.

At large temperatures, the temperature dependence of the conductivity is mostly determined by the change in carrier density. This is because µ_h and µ_e have a power law dependence on the temperature, which can be neglected due to the exponential term in equation2.2[35]. N_cand N_v are also weakly temperature dependent, but this can be neglected for the same reason. For a p-type semiconductor, the conductivity is determined by both the intrinsic carriers and the holes from the acceptors:

σ = µe(p + n_i). (2.10)

In the intrinsic regime (large temperatures), the extrinsic hole density p is approx- imately constant, so that the only important temperature dependence comes from n_i (equation2.7):

σ ∝ exp

−E_g(0) 2k_bT



. (2.11)

The parameter E_g(0) can be determined by measuring the resistance R at different temperatures. This is because R is inversely proportional to σ, as can be seen from equation 2.8. According to equation 2.11, the temperature dependence of the resistance in the intrinsic regime is then

log (R) ∝ E_g(0)

2k_bT . (2.12)

The slope of a linear fit of log (R) against _T¹ in this regime should therefore be equal to^E_2k^g(0)

b . See section6.1.3for the results of this method for the Pb_1−xSn_xTe nanowire devices.

2.3.4 Band gap

The band gap of semiconductor materials typically decreases with increasing tem- perature. This is because of the electron-phonon interactions and the expansion of the crystal lattice [34]. For most semiconductors, the temperature dependence of the band gap can be described by the empirical Varshni model [36], given by:

E_g(T ) = E_g(0) − αT²

T + β, (2.13)

where α is the volume coefficient and β is the volume compressibility. There is an exception for the lead salts PbS, PbSe and PbTe. The valence band maximum (VBM) and conduction band minimum (CBM) for these materials are located at the L⁺₆ and L⁻₆ points respectively (see section2.2.1). The energy levels at these points shift with increasing temperature such that their separation increases. The band gap can therefore be described by a modified version of the Varshni model [32]:

Eg(T ) = Eg(0) + αT²

T + β, (2.14)

where the only difference with equation2.13is the change in sign of the temperature dependent term. For PbTe, the expression becomes [37]:

E_g(T ) = 0.19 +4.5 · 10⁻⁴· T²

T + 50 . (2.15)

The Varshni model can be extended for Pb1−xSnxTe by including a x term [38]:

E_g(T ) = 0.19 +4.5 · 10⁻⁴· T²

T + 50 − 0.48 · x. (2.16)

Figure2.7 shows a plot of |E_g| as a function of x for different values of T .

Figure 2.7: Absolute value of Eg of Pb1−xSnxTe as a function of x, for different values of T .

From equation2.16, it can be seen that E_g(0) = 0.19 − 0.48 · x, for Pb_1−xSn_xTe. So, using the method to determine E_g(0), described in section 2.3.3, an estimation of x can be made. The results of this method for Pb1−xSnxTe nanowire devices can be found in section6.1.3.

2.4 MOS Capacitor

The nanowire devices that were fabricated for this research have basically the same working principles as the metal-oxide-semiconductor field-effect transistor (MOS- FET). The metal-oxide-semiconductor (MOS) structure, which acts as a capacitor, represents then the metal gate that is used to tune the electronic properties of the nanowire during transport. This section discusses some theoretical concepts of the MOS capacitor, which are important to understand the devices (see section 4.2) and the results of the analytical model (see chapter 3). Section 2.4.1 discusses the field effect and the depletion region. The band diagram of the MOS capacitor is introduced in section 2.4.2. Section 2.4.3 discusses the different modes and accord- ing band bending of the MOS capacitor. A method to derive the capacitance is introduced in section2.4.4. Then, properties of different dielectric materials are dis- cussed in section2.4.5. Finally, the capacitance of the depletion region is discussed in section 2.4.6.

2.4.1 Field effect and depletion region

The gate of a metal-oxide-semiconductor field-effect-transistor (MOSFET) device can be seen as an MOS capacitor, see figure2.8.

Figure 2.8: Schematic representation of a metal (grey)-oxide (green)-semiconductor (blue) (MOS) capacitor, for a p-type semiconductor. The metal has a large density of positive charges (holes) at the interface, resulting in an electric field (indicated by grey arrows) that penetrates into the semiconductor and repels the holes. The depletion region (red) has a net negative charge due to the stationary acceptor ions.

The metal has a very large concentration of charge carriers, both electrons and holes.

The semiconductor is p-type in this case, so N_A >> N_D. We can make the metal gate at the interface have a positive charge by applying a positive gate voltage V_g on the metal. The positive charge will be concentrated very close to the metal surface.

This will create an electric field that repels the holes inside the semiconductor from the interface, leaving a net negative charge region consisting of ionized acceptors.

This effect is called the field effect. The region without holes is then called the depletion region. The charge inside the depletion region is exactly equal to the charge on the metal at the interface, so that charge neutrality is preserved. In order to achieve pinch-off, the depletion region has to extend into the entire semiconductor material. The strength of the electric field for a certain V_g depends on the oxide material. A discussion on different oxides and their properties can be found in2.4.5.

2.4.2 Band diagrams

In order to understand the MOS capacitor model in chapter3, we have to look at the energy band diagrams of the device. The band structure of each material indi- vidually is shown in figure2.9.

(a) metal (b) oxide (c) p-type semiconductor

Figure 2.9: Band diagrams of the different materials of the MOS capacitor. a) The Fermi level E_f of the metal lies within one of the bands, so E_c = E_f. b) The oxide typically has a large bandgap, on the order of 1-10 eV (no to scale here). The Fermi level is unimportant so left out. c) The p-type semiconductor has a Fermi level that lies below the intrinsic Fermi level E_i.

Here E0 is the vacuum energy, Ef is the Fermi energy, Ec is the conduction band energy and E_v is the valence band energy. φ_m and φ_sc are the work functions of the metal and semiconductor respectively. The work function is the amount of energy that is needed for an electron to be completely removed from a material (excited to the vacuum level). It is defined as the energy difference between the Fermi level and the vacuum level:

qφ = E₀− E_f. (2.17)

χ_ox and χ_sc are the electron affinities of the oxide and semiconductor respectively.

The electron affinity is defined as the energy difference between the conduction band and the vacuum level:

qχ = E0− Ec. (2.18)

If we bring the materials into contact with each other (see figure 2.10), the bands need to be aligned with each other in such a way that two conditions are met. First, in thermal equilibrium, Ef is invariant in the entire system. Second, E0 has to be continuous in the entire system.

For most materials, φ_m 6= φ_sc, so the Fermi levels are not aligned. The band structures of the materials are therefore shifted with respect to each other. Inside the oxide, there is a voltage drop V_ox, which leads to a linear slope in the bands of the oxide and a constant electric field. Inside the semiconductor, the potential varies quadratically, leading to a linearly decreasing field. The band bending inside

Figure 2.10: Band diagram of the MOS capacitor without applied voltage. Ef is constant and E₀ is continuous throughout the system.

the semiconductor is equal to qψ_s, where ψ_s is the surface potential. The total amount of band bending in the system without gate voltage is defined as the flat band voltage V_{F B}:

V_{F B} = φ_m− φ_sc = ψ_s+ V_ox. (2.19) The Fermi potential in the bulk of the semiconductor, ψF p, is defined as

ψ_{F p} = E_i,bulk− E_f. (2.20)

2.4.3 Accumulation, depletion and inversion

The band bending can be tuned by applying a voltage onto the gate, so that a potential difference is induced between the semiconductor and the gate. Applying an external voltage means the system is no longer in thermal equilibrium, so E_f is no longer invariant in the system. The Fermi level in the metal will be raised or lowered depending on the applied gate voltage V_g, while the Fermi levels of the oxide and semiconductor remain constant. The potential difference due to V_g is divided between the oxide and the semiconductor according to V_g = ∆V_ox+ ∆ψ_s. The total amount of bend bending under applied voltage is given by

V_{F B} + V_g = ψ_s+ V_ox. (2.21) The device has three operating modes, depending on the sign and size of Vg: accu- mulation, depletion and inversion.

1. For V_g < 0, the device is in accumulation mode. The bands in the oxide and semiconductor will bend upwards and holes will be attracted to oxide- semiconductor interface, due to the electric field. Figure2.11ashows the band diagram for the device in accumulation mode.

2. For 0 < V_g < V_T, the device is in depletion mode. The bands in the ox- ide and semiconductor will bend downwards, holes will be repelled from the

(a) (b)

Figure 2.11: Band diagrams of the MOS capacitor with applied gate voltage V_g. a) Accumulation mode for V_g < 0. b) depletion mode for 0 < V_g < V_T.

oxide-semiconductor interface and a depletion region will be formed inside the semiconductor (see section 2.4.1).The bands in the semiconductor then bend down far enough so that E_f = E_i. The surface potential required to achieve this is

ψ_s= ψ_{F p} (2.22)

When the voltage is increased, the depletion region will extend further into the semiconductor. Figure 2.11b shows the band diagram for the device in depletion mode.

3. For V_g > V_T, the device is in inversion mode. The voltage is so large that E_i can bend down below E_f, leading to n-type behaviour. A layer of inversion charge will form at the interface, which is explained as follows. In thermal equilibrium, the generation and recombination of electron-hole pairs occurs at the same rate. If there is a strong electric field present however, the generated electrons/holes will be attracted to/repelled from the interface, before they get a chance to recombine. At the threshold voltage V_T, the electron density at the interface is equal to the ionized acceptor density. This point is called the onset of strong inversion and the surface potential required to achieve this is

ψ_s = 2ψ_{F p}. (2.23)

At the onset of strong inversion, the depletion region has its maximum width and stops growing.

In chapter 3, an analytical model of the depletion mode of the MOS capacitor with Pb_1−xSn_xTe as the semiconductor material is presented. Using the model, the maximum depletion width as a function of x is calculated.

2.4.4 Capacitance derivation

The capacitance of the gate has to be estimated in order to calculate the mobility and carrier density from the experimental data (see section6.2.1) and the depletion region width from the model (see section3.1.4). The total capacitance is a combi- nation of the gate capacitance and depletion region capacitance, which is discussed in section 2.4.6.

Different methods can be used to determine the gate capacitance. The most com- monly used method uses the cylindrical capacitor model, which assumes that the nanowire is an infinite metallic cylinder [39, 40]. Due to the rectangular cross-section of our nanowires (see section 4.1), we can use a simpler model, namely the infinite parallel plate capacitor. This model assumes two parallel metallic plates with a di- electric material in between. The nanowires are still assumed to be metallic, which is a valid assumption for doping concentrations larger than 10¹⁷ cm⁻³. This is true for both PbTe and SnTe (see section 2.2.3). A benefit of the simplicity of this model is that the materials and gate geometry can easily be adjusted, as long as the nanowire is rectangular. This way, the capacitance of devices with different gates (bottom/back gate and top gate) can be calculated.

The capacitance of a parallel plate capacitor is given by C_ox = Q

V , (2.24)

where Q is the total charge on one of the plates and V is the electric potential difference between the plates. V can be determined from the electric field:

V = − Z

E · ~~ dl. (2.25)

The electric field is constant between the plates, so this expression simplifies to

V = −E · t_ox (2.26)

where t_ox is the thickness of the oxide (distance between the plates). The electric field can be determined from the electric charge on the plates using Gauss’s law for the total electric flux through a closed surface:

I

E · ~~ dA = Q_enc

₀_r, (2.27)

where Q_enc is the total electric charge enclosed by the surface, _r is the relative dielectric constant of the material between the plates, and A is the area of the plate.

We can simplify this expression by assuming a uniform electric field between the plates:

E = σ

2₀_r, (2.28)

where the charge density on the plate is given by σ = Qenc/A. Combining equations 2.24,2.26 and 2.28, the final expression for the capacitance becomes

C_ox = 2A₀_r

t_ox . (2.29)

This expression is only dependent on rand the geometry of the system. This is true for capacitors in general. If the geometry of the device is known, the capacitance can be calculated. See section3.1.2for a discussion on the different gate geometries and their capacitance.

2.4.5 Dielectric materials: oxides

The oxide dielectric material has to be considered carefully when designing a MOS- FET device. As can be seen from equation2.29, the capacitance of a parallel plate capacitor scales linearly with the dielectric constant _r of the oxide, and inversely with the thickness of the oxide. However, we can not simply choose the oxide with highest dielectric constant and make it as thin as possible. We have to consider the breakdown field of the oxide. This is the maximum electric field that the oxide can generate, before it starts to break down, and the gate starts to leak current into the semiconductor. The breakdown field is defined as

E_BD = V_BD

t_ox , (2.30)

where VBD is the gate voltage at which the oxide starts to break down and tox is the oxide thickness. V_BD depends on the bandgap of the material. A larger bandgap means a larger V_BD, but unfortunately it also generally means a lower dielectric con- stant [41]. Figure2.12 shows a plot of the bandgap versus static dielectric constant for the most common oxides.

Figure 2.12: Bandgap plotted against the static dielectric constant for different oxides. The ideal case of a large bandgap and large dielectric constant is highlighted.

Figure adapted from [41].

The charge density at breakdown is given by

Q_BD = C_oxV_BD. (2.31)

The appropriate oxide material and thickness is therefore always a trade-off between the capacitance and the breakdown field. In general, the highest value of Q_BD gives the best result.

2.4.6 Depletion region capacitance

The depletion region inside the semiconductor acts as an additional capacitor itself.

Due to the small width of the depletion layer, the contribution is usually negligible in MOSFET devices, but for the very thin oxide layers (≈10 nm) that are used for the top gate devices it has to be considered, see section3.1.3. The total capacitance of the system is a series combination of the oxide capacitance C_ox and the depletion region capacitance C_D [42]:

C = C_oxC_D

C_ox+ C_D. (2.32)

Cox is constant, but CD is a function of the surface potential ψs and thus of the applied gate voltage V_G, see section3.1.3 [43]. A simulation of the total capacitance against gate voltage is shown in figure 2.13.

Figure 2.13: Total capacitance per unit area plotted against gate voltage for a p- type semiconductor with N_A = 10¹⁷ and t_ox = 10 nm. The numbered regions of the curve are 1. accumulation, 2. depletion, 3. weak inversion, 4. strong inversion.

Figure adapted from [42].

Four regions of the C − V_G curve are indicated in the figure:

1. Accumulation mode. The capacitance saturates at C_max = C_ox for sufficiently negative gate voltage Vg.

2. Depletion mode. The depletion region width W increases with increasing V_g, so the total capacitance C decreases.

3. Weak inversion. The inversion charge density is still smaller than the doping density inside the depletion region. The capacitance reaches the minimum value C_min.

4. Strong inversion. The inversion charge density is larger than the doping density inside the depletion region. The depletion region has achieved its maximum width W_max. The inversion region grows with increasing V_g. The capacitance saturates again at C_max= C_ox for sufficiently large V_g.

2.5 Nanowire MOSFET

The MOS capacitor can be extended to a metal-oxide-semiconductor field effect transistor (MOSFET) by including source and drain contacts at the ends of the Pb_1−xSn_xTe nanowire. The MOSFET device can be used to determine the elec- tronic properties of different semiconductor materials, and is widely used for the characterization of semiconducting nanowires. In section 2.5.1 is discussed how to determine important electronic properties from transport measurements on MOS- FET. The different metal-semiconductor contacts are discussed and a prediction is made for the Pb1−xSnxTe nanowires in section2.5.2. The transport mechanisms for Ohmic and Schottky contacts are discussed in section 2.5.3. Lastly, in section2.5.4 the gate characteristics of a MOSFET with Schottky barriers are discussed.

2.5.1 Transconductance, mobility, carrier density

By applying a voltage VSD between the source and the drain, a current ISD will flow through the nanowire. By applying a voltage V_G on the gate, the current through the wire can be tuned, due to the field effect. For a p-type semiconductor nanowire, ISD will decrease with increasing VG, which can be understood as the depletion mode. The holes flowing through the nanowire will be repelled from the oxide-semiconductor interface and a depletion region will form, as discussed in sec- tion 2.4.1. Due to the small dimensions of nanowires, with radii down to tens of nm’s, the field effect can be used to completely deplete all charge carriers from the nanowire, which is called “pinch-off”.

For large V_SD, the current saturates at a certain value, depending on V_g. Below saturation, I is linearly dependent on V_SD:

V_SD = IR, (2.33)

where R is the resistance. The conductance G scales inversely with R, so:

G = I

V_SD. (2.34)

The source-drain current I depends on the applied gate voltage V_g according to

dI_D = g_mdV_g, (2.35)

where gm is the transconductance. In the linear regime, the accumulation/depletion charge Q at the semiconductor-oxide interface is given by

Q = C(Vg− VT), (2.36)

where C is the total gate capacitance (see section2.4.6) and V_T is the gate voltage for which I becomes zero (pinch-off). The source-drain current as a function of Vg

can be derived as [44]:

I = Z

qpvdA = µ_e,hQV_SD

L² = µ_e,hC(V_g− V_g,T)V_SD

L² , (2.37)

where q is the electron charge, p is the hole concentration, v is the drift velocity, µ_e,h is the electron/hole mobility, L is the nanowire channel length and A is the area of