Two-step beam-forming using space-frequency trans-formation in a time-multiplexed phased array receiver

formation in a time-multiplexed phased array receiver

Citation for published version (APA):

Deng, W. (2011). Two-step beam-forming using space-frequency trans-formation in a time-multiplexed phased array receiver. Technische Universiteit Eindhoven. https://doi.org/10.6100/IR723153

DOI:

10.6100/IR723153

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Two-Step Beam-Forming Using Space-Frequency

Transformation in a Time-Multiplexed Phased-Array

Receiver

Front cover:

Chip photo of the system presented in Chapter 8

Back cover:

Two-Step Beam-Forming Using Space-Frequency

Transformation in a Time-Multiplexed Phased-Array

Receiver

PROEFSCHRIFT

ter verkrijging van de graad van doctor aan de

Technische Universiteit Eindhoven, op gezag van de

rector magnificus, prof.dr.ir. C.J. van Duijn, voor een

commissie aangewezen door het College voor

Promoties in het openbaar te verdedigen

op maandag 28 november 2011 om 14.00 uur

door

Wei Deng

Dit proefschrift is goedgekeurd door de promotor:

prof.dr.ir. A.H.M. van Roermund

Copromotor: dr.ir. R. Mahmoudi

A catalogue record is available from the Eindhoven University of Technology Library.

CIP-DATA LIBRARY TECHNISCHE UNIVERSITEIT EINDHOVEN

Wei Deng

Two-Step Beam-Forming Using Space-Frequency Transformation in a Time-Multiplexed Phased-Array Receiver / by Wei Deng. – Eindhoven : Technische Universiteit Eindhoven, 2011.

Proefschrift. – ISBN: NUR 959

Key words: 30GHz / SiGe mm wave integrated circuit design / phased array / receiver / beam forming / multiplexing / switching

Copyright © 2011 by Wei Deng, Eindhoven

All rights reserved. No part of this publication may be reproduced or transmitted in any form or by any means, electronic, mechanical, including photocopy, recording, or any information sto-rage and retrieval system without the prior written permission of the copyright owner.

To my parents,

and to my wife, Yan Huang.

Samenstelling van de promotiecommissie:

prof. dr. ir. A.C.P.M. Backx, Technische Universiteit Eindhoven, voorzitter prof. dr. ir. A.H.M. van Roermund, Technische Universiteit Eindhoven, promotor dr. ir. R. Mahmoudi, Technische Universiteit Eindhoven, co-promotor prof. dr. ir. D.M.W. Leenaerts, Technische Universiteit Eindhoven prof. dr. ir. F.E. Vliet, University of Twente prof. ir. A. van Ardenne, Chalmers University of Technology prof. dr. ir. A.B. Smolders, Technische Universiteit Eindhoven dr. ir. G.H.C. van Werkhoven, Thales Nederland

.

vii

Contents

Contents ... vii

Glossary ... xi

1

Introduction ... 1

1.1 Motivation ... 1 1.2 Background... 3

1.3 Problem statement and research strategy ... 4

1.4 Thesis outline ... 5

2

Basic concepts ... 7

2.1 Receiver system basics ... 7

2.1.1 Noise ... 8

2.1.2 Non-linearity ... 10

2.1.3 Dynamic Range ... 13

2.2 Phase modulation basics ... 14

2.3 Phased-array basics ... 18

3

Single and multipath receiver: a system approach ...25

3.1 Translating ADC parameters to RF domain ... 26

3.1.2 ADC noise ... 27

3.1.3 ADC non-linearity ... 29

3.2 Mapping ADC parameters to system design ... 32

3.3 Receiver system optimization method ... 35

3.3.1 Receiver signal flow diagram ... 35

3.3.2 Optimization method ... 38

3.4 Analog beam-forming ... 39

3.5 Digital beam-forming ... 45

3.6 General case of beam-forming ... 50

3.7 Conclusion ... 52

4

Two-step beam-forming: multiplexing architecture ...53

4.1 Multiplexing architecture introduction ... 53

4.2 Spatial to frequency mapping ... 57

4.3 Two steps of spatial filtering ... 57

4.4 Phased-array analog and digital co-design ... 58

4.5 Generalized phased-array system design ... 58

5

Multiplexing architecture, ideal behavior ... 61

5.1 Analog multiplexing ... 62

5.1.1 Properties of the switching signal ... 62

5.1.2 Pulse modulation ... 64

5.1.3 Combination in the analog domain ... 68

5.2 Spatial to frequency mapping ... 70

5.2.1 Space to frequency mapping coefficient Dn ... 70

5.2.2 Translation from voltage to power domain, Dn to Pxn ... 76

5.2.3 Coarse beam pattern RxN by frequency selectivity ... 79

5.3 Digital de-multiplexing and phase-shifting ... 82

5.4 Array pattern ... 86

Contents ix

6

Multiplexing architecture, non-ideal behavior ... 91

6.1 Angle deviation ... 92

6.2 Non-ideal switches ... 93

6.3 Noise in a multiplexing system ... 96

6.4 Frequency mixing ... 99

6.5 System simulations ... 100

6.6 Power flow diagram for a multiplexed architecture ... 103

6.7 Conclusion ... 105

7

Designs for the 30GHz components ... 107

7.1 Design requirements ... 107

7.2 LNA and Multiplexer ... 108

7.2.1 Circuit design ... 108 7.2.2 Measurements ... 111 7.3 LNA-multiplexer-mixer combination... 114 7.3.1 Circuit design ... 114 7.3.2 Measurements ... 116 7.4 Clock generator ... 117 7.4.1 Circuit design ... 117 7.4.2 Measurements ... 120

7.5 Input delay line... 121

7.5.1 Circuit design ... 121 7.5.2 Measurements ... 126 7.6 Power amplifier ... 127 7.6.1 Circuit design ... 127 7.6.2 Measurements ... 129 7.6.3 Trouble shooting ... 131 7.7 Conclusion ... 135

8

System integration and verification ... 137

8.2 System with four channels ... 140

8.2.1 Demonstration with one input signal ... 141

8.2.2 Demonstration with two input signals ... 145

8.3 Conclusion ... 150

9

Conclusions and future works ... 151

9.1 Conclusion ... 151 9.2 Future works ... 153

10

Original contributions ... 155

References ... 157

Publications ... 163

Summary ... 165

Samenvatting ... 167

Acknowledgement ... 169

Curriculum vitae ... 171

xi

Glossary

Symbol Description Unit

A Signal amplitude V

BW Bandwidth Hz

cn Complex Fourier coefficients for generic switching signal

c’n Complex Fourier coefficients for equal time slot duration τ

d Adjacent antenna distance m

Dn Coefficient function of the n-th order harmonic V

fC Carrier frequency Hz

fMUL Sampling rate for multiplexer in the multiplexing system Hz

fS Sampling rate for each path in the multiplexing system Hz

k Antenna number

K Number of antennas

L Power rejection ratio of desired viewing angle to un-desired viewing angle

n Harmonic number

N Number of harmonics

Pxn Power contained in the n-th pair of side frequency mW

Pyn Power transferred to the fundamental frequency from the n-th pair mW

RxN Array coarse pattern mW

RxN Array final pattern mW

SNR Signal to noise ratio

tS Starting time delay of the switching signal s

TS Period of the switching signal s

∆N Angle deviation degree

∆DFE Distortion contribution by the RF front-end referred to ADC output

∆NFE Noise contribution by the RF front-end referred to ADC input

∆P1 Margin to the ADC full scale range power

∆P2 Energy reduction from one tone input to two tone inputs (by each tone)

∆S Distance difference for adjacent channels in the wave propagation direction m

∆t Progressive time delay between two adjacent channels, caused by θ s

α1 Positive amplitude of the switch signal V

α1 Negative amplitude of the switch signal V

β1 Interference suppression flexibility of the general beam-forming system

φ Electric phase difference between two adjacent channels caused by θ rad/degree

θ Angle of incidence in spatial domain degree

Ø Angle of electric phase shifter γ in spatial domain degree

γ Electric phase shifter between two adjacent channels rad/degree

λ Wavelength m

τ Duration for each time slot (pulse width) in the multiplexing system s

χ1 Interference suppression flexibility of the multiplexed architecture

1

C h a p t e r

1

1

Introduction

1.1

Motivation

Silicon-based technology has had a dramatic impact on the world of wireless technology. Wireless devices have become part of our life: smart phones, satellite navigation system, home wireless network, etc, and it is getting more and more popular. Today we can access digital in-formation in virtually every corner of the globe. This trend has made the wireless communication one of the fastest growing segments of the modern technology industry.

The vast majority of today’s wireless standards and applications are accommodated around 1 to 6GHz. This is initially due to the early technology access. Along with the technology progress indicated by Moore’s law [1], the components expenses around these frequencies are getting cheaper, leading to a rapid expansion of these systems. One of the downsides of this expansion is the resulting limitations of available bandwidth. The defined systems are capable of supporting light or moderate levels of wireless data traffic. As in Bluetooth [2], its maximum data rate is 3Mbps at 2.4GHz.

Driven by the customer demands, especially the fast growing wireless portable devices market, the requirement of supporting multi-standard applications has been recognized. Lacking of channel capacity has become one of the bottlenecks of low frequency applications. Furthermore, as predicted by Edholm’s law [3], the required data rates (and associated bandwidths) have doubled every eighteen months over the last decade. This trend is shown in Fig. 1.1 for cellular, wireless local area networks and wireless personal area networks for last sixteen years.

Fig. 1.1: Data rate trend predicted by Edholm’s law

Applications operating at 1 to 6GHz are suitable for long distance communications. However, the spectrum congestion and data rate limitation motive designers exploring new solutions. As stated by Shannon [4], the maximum available capacity of a communication system increases linearly with channel bandwidth and logarithmically with the signal-to-noise ratio. Therefore, one of the choices is to look upwards in the high frequencies where more bandwidth could be available.

One of the high frequency applications is the indoor personal communications and wireless fidelity at 60GHz [5]. Around 7GHz spectral spaces has been allocated worldwide for unlicensed use. In order to design circuits at 60GHz, the transistor cut-off frequency fT needs to be typically

around 200GHz. At this moment, the process for making such a device is still relatively expen-sive than lower frequency transistors. On contrary, making transistors with fT around 100GHz is

1.2 Background 3

to demonstrate the principles outlined in this thesis, the system and circuits are implemented at 30GHz.

Besides, there are two applications defined by the Federal Communications Commission (FCC) around 30GHz. Local Multipoint Distribution Services (LMDS) [6], can be considered as one of these applications. It is a broadband wireless access technology originally designed for digital television transmission (DTV). It was conceived as a fixed wireless, point-to-multipoint tech-nology for utilization in the last mile. LMDS commonly operates on microwave frequencies across the 26GHz and 31GHz bands. Another application is the satellite Ka-band communica-tion [7]. Ka-band transmission is viewed as a primary means for meeting the increasing demands for high data rate services of space exploration missions. At Ka-band, deep space communica-tions is allocated 500MHz of bandwidth compare to the 50MHz of bandwidth allocated to the X-band [8]; leading to even greater increase in throughput when using Ka-band.

1.2

Background

At 30GHz, the wave propagation path loss, the noise of the receiver, and the output power of the transmitter are more problematic to cope with than low frequencies. However, at this fre-quency, the millimeter-wave operation can facilitate very small antenna apertures for the array receptors, since the electromagnetic wavelength is very short. This property allows highly mi-niaturized, lightweight phased-array to be manufactured, a key for compensating the path loss and alleviating the RF transceiver front-end requirements.

The ability to individually control both amplitude and phase of each element in the array is known as beam-forming1 _{[9]. Beam-forming can be separated into two categories: analog}

beam-forming, and digital beam-forming. As indicated by its name, analog beam-forming con-trols the amplitude and phase of each element in the analog part of the receiver chain. Phase shifters are commonly used in the analog beam-forming phased-array architecture for adjusting the phase of each antenna path and steering the beam [10-11]. Phase shifter can be implemented in different parts of a transceiver, such as at RF [12-15], at IF [16-19], or at LO [20-22]. On the other hand, digital beam-forming controls the amplitude and phase of each element in the digital part of the receiver chain. As a result, the phase shifter is implemented in the digital domain by various algorithms [23-27]. In practice, these two beam-forming techniques have their own pros and cons. The analog beam-forming technique enhances the SNR and rejects the interferences before the ADC and the ADC dynamic range is relaxed. However, due to the phase compen-sation in the analog domain, the phase information of the incidence signal is not available for digital signal processing. On the other hand, the digital beam-forming technique conveys the incidence signal amplitude and phase information into the digital domain, which provides more

1 _{Phased-array architecture is usually used together with beam-forming technique. Sometimes, we also use ‘beam-steering’ or}

flexibility. Nevertheless, the hardware implementation per antenna channel, especially the power hungry ADCs, will increase the overall power consumption, area and cost. The demand for a flexible phased-array architecture that takes advantage of both analog and digital beam-forming is enormous.

In the past few years, research has been performed in this area. Reference [28] presents a tech-nique for realizing phase-amplitude weighting for phased-array antennas using sampling of an-tenna elements signals. In this architecture, beam-forming is achieved in the analog domain. Traditional phase shifters are replaced by programmable switches that improve the flexibility of the analog beam-forming. The drawback for this architecture is similar as other analog beam-forming structures: phase information of the incidence signal is lost before the digital signal processing, which limits the further flexibility improvement. Reference [29] presents a code-modulating path-sharing multi-antenna receiver for spatial multiplexing and beam-forming. It uses code modulation in the RF domain to distinguish antenna signals before combining them and sending the resulting signal through a single path, so it is possible to recover the signals in the digital domain. This architecture realizes beam-forming in the digital domain, and compared to digital beam-forming, it reduces hardware consumption in the analog domain. The drawbacks for this architecture are that the signal bandwidth expansion after the channel coding requires a very demanding ADC, and the coding complexity makes it not suitable for a large number of arrays. Instead of code modulation, reference [30] presents a similar concept using a time division multiplexed scheme for digital beam-forming which achieves a reduction of RF hardware by multiplexing several individual elements of the antenna array into a single RF channel prior to the LNA, and de-multiplexing the combined signal before the analog low pass filter and ADC. This architecture has only limited improvement on the hardware consumption, and it achieves no improvement on the use of multiple ADCs. It introduces a noise problem because the pin diode multiplexer is placed before the LNA.

1.3

Problem statement and research strategy

As previously mentioned, current literature mostly focuses on phased-array circuit implementa-tions. A system approach analysis method is lacking. This leads to a non-optimized result. Fur-thermore, a flexible phased-array receiver that can relax the ADC design in the analog domain (advantage of analog beam-forming), and still preserves the initial phase information in the dig-ital domain (advantage of digdig-ital beam-forming) is needed. Moreover, from implementation point of view, the possibility to realize this idea at 30GHz with low-cost technology is of par-ticular interested. Hence, the main research objectives of this thesis are therefore:

• provide a system approach analysis method for phased-array receivers.

• investigate a flexible phased-array structure with both analog and digital beam-forming properties.

1.4 Thesis outline 5

• investigate a real low-cost integrated solution of the 30GHz phased-array front-end sys-tem and verify its performance and to draw conclusions on future work.

The research strategy for the first objective is to introduce a system optimization method for a single path receiver; mapping a phased-array receiver to an equivalent single path receiver model; and then apply the optimization method to the equivalent model.

The research strategy for the second objective is shown in Fig. 1.2. It shows a functional block diagram of such a phased-array receiver. It combines K paths into one path by an analog com-bination block, with initial phase information preserved. Then, an analog signal processing block processes the combined signal to relax the ADC design. After the ADC, the digital signal processing block separates the combined signal into the original K paths, and the initial phase information is recovered. The phase shifters are implemented in the digital domain just like a traditional digital beam-forming. And, at last, the phase compensated signals are added together to form the desired beam-pattern.

Fig. 1.2: Flexible phased-array receiver shown in functional blocks.

The research strategy for the third objective is: based on the provide technology, identify the critical components of the system and characterize them individually at 30GHz before complete system integration; implement system firstly with only one channel to check the initial integration performance; implement the complete phased-array system with four channels and verify the measurement result with pre-developed theory.

1.4

Thesis outline

This thesis is organized in the following way. Chapter 2 introduces some basics concepts and required theories that will be used in the following chapters. To be more particular, it includes

receiver system basics, phase modulation basics, and phased-array basics. Chapter 3 provides a system approach analysis method for single and multi-path receivers, which is the answer to the first objective of this thesis. The research strategy is applied to analog and digital beam-forming in this chapter. Using the results from the previous analysis, the system approach for the general case of beam-forming is extracted.

Chapters 4, 5, and 6 provide a multiplexing architecture with analog and digital beam-forming properties, which is the answer to the second objective of this thesis. Chapter 4 introduces the architecture, and the tagged along new concepts. Chapter 5 provides a detailed analysis for the multiplexing architecture. Chapter 6 studies the non-ideal behaviors of this architecture.

Chapters 7 and 8 are about the circuit and system implementation of the multiplexing phased-array architecture, which is the answer to the third objective of this thesis. Chapter 7 addresses the component design at 30GHz. Chapter 8 discusses the system integration of the individual components listed in chapter 7. Note that this thesis mainly covers the multiplexing phased-array receiver part. For the transmitter part, only a power amplifier component design is described in section 7.6 to explore the feasibility. Chapter 9 is reserved for conclusions and future work recommendations. Chapter 10 summarizes the original contributions of this work.

7

C h a p t e r

2

2

Basic concepts

This chapter introduces some basics concepts and required theories that will be used in the following chapters. Section 2.1 explains basic concepts in communication systems, including noise, linearity, and dynamic range which will be frequently used in chapter 3 and 4. Section 2.2 explains phase modulation basics, which will be used as the guideline to analysis and explain the multiplexing phased-array system in chapter 4. Section 2.3 discusses the basic theory of phased-array.

2.1

Receiver system basics

Noise and linearity are the most frequently used concepts in receiver designs. Low noise and high linearity are desired and demanded in most communication systems. However, to achieve low noise and high linearity is not always easy.

2.1.1

Noise

The noise performance of the receiver is measured with noise factor (F), which is a measure of how much the signal-to-noise ratio is degraded through the system [31]. We note that

(

)

outsource added out source out total out total out in source in in out in

N

N

N

N

N

G

S

N

S

SNR

SNR

F

, , , , , ,

1

/

/

+

=

=

⋅

=

=

(2.1)

where Sin is the available input signal power, G is the available power gain, Nout,total is the total noise

power at the output, Nout,source is the noise power at the output originating at the source, and Nout,add

is the noise power at the output added by the electronic circuitry. This shows that the minimum possible noise factor, which occurs if the electronics adds no noise, is equal to 1. Noise figure NF is related to noise factor F by

F

NF

=

10

log

₁₀ (2.2) It can be derived that NF is the ratio of the receiver’s signal-to-noise ratio (SNR) at the output to that at the input, which can be expressed in dB format as follows

NF

SNR

SNR

_out,_dB

=

_in,_dB

−

(2.3)

Equation (2.3) indicates that the NF represents the amount of SNR degradation after the signal is processed by the receiver.

G1 NF1 G2 NF2 G3 NF3 Gn NFn

Fig. 2.1: Noise cascading system

In Fig. 2.1, assuming that all stages are matched to the system characteristic impedance, the overall noise factor of the system is determined by the gain and noise factor of each stage as in (2.4), and the overall gain of the system is shown in (2.5)

2.1 Receiver system basics 9 1 2 1 2 1 3 1 2 1

1

1

1

−

−

+

+

−

+

−

+

=

n n total

G

G

G

F

G

G

F

G

F

F

F

(2.4) n n total

G

G

G

G

G

=

1

⋅

2

₋₁

⋅

(2.5)

Equation (2.4) is known as Friis’s formula [32], which indicates that the noise factor of the first stage is most critical to the system noise performance because the noise due to each cascade stage is suppressed by the available power gain preceding it.

Fig. 2.2 shows the equivalent noise model of a single receiver stage. Neq,in is the input equivalent

noise, and Neq,out is the output equivalent noise.

G

NF

N

eq,in

N

eq,out

Fig. 2.2: Equivalent noise model of a single receiver stage

The output equivalent noise can be expressed as

dB dBm floor dB dBm in eq dBm out eq

G

NF

N

G

N

N

+

+

=

+

=

, , , , , (2.6)

where Nfloor represents the noise floor of the stage. In a cascaded system (Fig. 2.1), the output of

one stage feeds the input of the next. The total output equivalent noise can be expressed as

(

)

(

)

, , , , ,

10 log

174

10 log

total eq out dBm total total dB

total total dB

N

kT BW

NF

G

dBm

BW

NF

G

=

⋅

+

+

= −

+

+

+

(2.7)

where kT*BW is the receiver input noise floor, and NFtotal and Gtotal are the system total noise

figure and gain, respectively. In (2.7), k=1.38*10-23 _{J/K is the Boltzmann’s constant [33]. T is the}

temperature. BW is the bandwidth in Hertz. kT corresponds to the minimum equivalent noise per Herz for a receiver at room temperature (290K), that is -174dBm/Hz. NFtotal is the total noise

figure of the system, and it is derived in (2.4). Gtotal is the total available gain (in dB) of the system,

2.1.2

Non-linearity

Any unwanted signal fed into a receiver is called interference and it generally degrades the signal to noise ratio of the wanted signal. Most interference comes from the signals intended for other users or other applications. The interference power can be orders of magnitude higher than the desired signal power and may corrupt the signal as a result of receiving non-linear behavior. Any real receiver is a nonlinear system that responses linearly only if the input signal is sufficiently small. When the input signal increases beyond some extent, the nonlinear behavior of the re-ceiver becomes evident.

If a sinusoid is applied to a nonlinear system, the output generally exhibits frequency compo-nents that are integer multiples of the input frequency. They are called harmonics of the input frequency.

Fig. 2.3: Nonlinear system, one tone input

For simplicity, assuming nonlinear property of the system can be written as Taylor expansion, we limit our analysis to third order, and assume nonlinear terms above the third order are negligible, y(t) in Fig. 2.3 can be derived as

( )

( )

( )

( )

(

)

(

)























































harmonics l fundamenta DC

t

A

t

A

t

A

A

A

t

A

t

A

t

A

t

y

ω

α

ω

α

ω

α

α

α

ω

α

ω

α

ω

α

3

cos

4

2

cos

2

cos

4

3

2

cos

cos

cos

)

(

3 3 2 2 3 3 1 2 2 3 3 3 2 2 2 1

+

+













+

+

=

⋅

+

⋅

+

⋅

=

(2.8)

One figure of merit for receiver linearity is the gain compression point. Theoretically, the re-ceiver’s output power increases linearly with the injected input power regardless of the input power level, as shown in Fig. 2.4 [34] by the dashed line. The solid line in Fig. 2.4 depicts a typical input/output transfer function of a real receiver.

2.1 Receiver system basics 11

1dB

ICP 1dB

OCP 1dB

P

in

[dBm]

P

out

[dBm]

Fig. 2.4: 1-dB compression point

It can be seen that at low input power level, the real I/O curve can be approximated with the straight line. As Pin increases, Pout gradually deviates from the linear curve and is eventually

satu-rated. The point at which Pout is 1dB lower than its linear theoretical value is called the input 1-dB compression point (ICP1dB). The importance of this point is that it indicates where the receiver starts to leave the linear region and the saturation becomes a potentially serious problem. The receiver also generates spurs at the harmonics of the signal frequency when the receiver goes into compression.

Fig. 2.5: Nonlinear system, two tone input

Fig. 2.5 shows two closely spaced interferences at f1 and f2 in the vicinity of signal band, where the

strongest interference commonly originates. After passing the nonlinear system, the output signal ytwo(t) can be derived as

(

)

[

]

(

)

[

]

(

)

(

)

(

)

[

]

(

)

[

]

(

)

(

)

(

)

[

]

(

)

(

)

[

cos

2

cos

2

]

(

3

)

2

cos

2

cos

4

3

3

3

cos

3

cos

4

1

2

cos

cos

2

2

cos

2

cos

2

1

cos

cos

4

9

)

(

)

(

)

(

)

(

1 2 1 2 2 1 2 1 3 3 2 1 3 3 2 1 2 1 2 2 2 1 2 2 2 1 2 3 1 2 2 3 3 2 2 1

IM

t

t

t

t

A

HD

t

t

A

IM

t

t

A

HD

t

t

A

l

Fundamenta

t

t

A

A

DC

A

t

x

t

x

t

x

t

y

_{two two two two}













−

+

+

+

−

+

+

+

+

+

−

+

+

+

+

+

+













+

+

=

+

+

=

ω

ω

ω

ω

ω

ω

ω

ω

α

ω

ω

α

ω

ω

ω

ω

α

ω

ω

α

ω

ω

α

α

α

α

α

α

(2.9)

One of the important linearity specifications in (2.9) is the third-order intermodulation point (IM3). When the interference power is high enough, the receiver generates noticeable spurs at ±nf1±mf2 due to intermodulation, where n and m are integers including zero. Two of these spurs,

located at 2f1- f2 and 2f2-f1, are particularly threatening to the received signal because they can fall

into the signal band and become impossible to eliminate by filtering. The power of the 3rd order distortion increases 3dB per 1dB increase of the input power. Fig. 2.6 shows the typical curves of the main tone and the third-order intermodulation power as a function of Pin.

P

in

[dBm]

P

out

[dBm]

1st

3rd

IIP

3

Fig. 2.6: Third order input intercept point

The third-order interception point is obtained by extrapolating the main-tone output at the slope of 1dB/1dB and the third-order distortion curve at 3dB/1dB from the low input power level

2.1 Receiver system basics 13

until they intersect with each other, as shown in Fig. 2.6. The x-coordinate of the intersection point is called the input referred third-order interception point (IIP3), and the y-coordinate is called the output referred third-order interception point (OIP3).

In a cascaded system as shown in Fig. 2.1, the overall IIP3 of the system is given by

n n total

IIP

G

G

G

G

IIP

G

G

IIP

G

IIP

IIP

_3, 1 3 2 1 3 , 3 2 1 2 , 3 1 1 , 3 , 3

1

1

₌

₊

₊

₊

₊

−

(2.10)

It can be seen from (2.10) that in a cascade system the linearity requirements on the receiver components at the back-end are more stringent because their effects on the overall system are ‘magnified’ by the preceding gain. We should emphasize that (2.10) is merely an approximation. In practice, more precise calculations or simulations must be performed to predict the overall IP3.

2.1.3

Dynamic Range

Dynamic range (DR) is defined as the ratio of the maximum input power level that the circuit can tolerate to the minimum input power level that the circuit can properly detect [35]. DR specifies how well the system can handle signals with various power levels.

The lower bound of the dynamic range is set by the receiver sensitivity, defined as the lowest input signal power a receiver can appropriately process. To calculate the receiver sensitivity, one starts from the maximum bit error rate (BER) the data transmission can tolerate in the absence of interference. To achieve this BER, the receiver must provide a minimum SNRout to the

subse-quent demodulator. Therefore, a minimum SNRin must be achieved at the receiver input, which

is given by total dB out dB in

SNR

NF

SNR

,min.

=

,min,

+

(2.11)

Assuming the receiver input is impedance matched to the antenna, the receiver sensitivity can be obtained as

(

)

,min, ,min, ,min,

10 log

174

10 log(

)

in dBm total out dB total out dB

P

NF

kT BW

SNR

NF

dBm

BW

SNR

=

+

⋅

+

=

−

+

+

(2.12)

The upper limit of the dynamic range has various definitions that result in different bounds [36], but all are related to the linearity of the receiver. For instance, the most common definition, the spurious-free dynamic range (SFDR), defines the maximum allowed input signal power as the one causing the maximum intermodulation product equal to the output noise power. From Fig. 2.6, this input power level can be solved by using the graphical method, which is given by

[

174

10

log(

)

]

3

1

3

2

, , 3 max, ,

IIP

NF

dBm

BW

P

_{in dBm}

=

_totaldB

+

_total

−

+

(2.13)

From (2.12) and (2.13), the receiver dynamic range can be found by

[

totaldB total

]

out dB dBm in dBm in dB

SNR

BW

dBm

NF

IIP

P

P

DR

min, , , , 3 min, , max, ,

)

log(

10

174

3

2

−

−

+

−

=

−

=

(2.14)

2.2

Phase modulation basics

Modulation is the process of modifying a high-frequency signal (called the carrier signal) with low-frequency information (called the modulating signal). The two most common types of modulation are amplitude modulation (AM) and frequency modulation (FM) [37]. These two forms of modulation modify the carrier’s amplitude or frequency, respectively, according to the instantaneous value of the modulating signal. Phase modulation (PM) is similar to frequency modulation (FM) except that the phase of the carrier waveform is varied, rather than its fre-quency.

Assume carrier signal vc(t) and modulating signal vm(t)

( )

[

( )

]

(

c c

)

c c c c

t

f

V

t

V

t

φ

π

θ

υ

+

=

=

2

cos

cos

(2.15)

( )

t

V

_m

(

f

_m

t

)

m

π

υ

=

cos

2

(2.16)

where V, f, and Ø are the amplitude, frequency and phase, respectively. Combining (2.15) and (2.16), the phase modulated signal in time domain is given by

( )

t

V

_c

[

f

_c

t

_c

k

_{p m}

( )

t

]

pm

π

φ

υ

2.2 Phase modulation basics 15

The instantaneous phase Øi of the carrier is

( )

t

k

_{p m}

c

i

φ

υ

φ

=

+

⋅

(2.18)

where kp is the change in carrier phase per volt of modulating signal, called phase sensitivity

(rad/volt). Øc is usually 0. Defining β as the phase deviation, the max amount by which the carrier

phase deviates from its unmodulated value, we get

( )

p m m p

t

k

V

k

⋅

=

⋅

=

υ

_max

β

(2.19)

Substituting (2.19) into (2.17), the phase modulated signal can be expressed as

( )

[

(

)

]

(

)

[

f

t

f

t

]

V

t

f

V

k

t

f

V

t

m c c m m p c c pm

π

β

π

π

π

υ

2

cos

2

cos

2

cos

2

cos

⋅

+

⋅

=

⋅

⋅

+

⋅

=

(2.20)

Expanding the above equation with Fourier analysis, and using the Bessel function [38] to de-termine the spectrum of a phase modulated signal, we achieve

( )

( )

(

)

( )

(

)

(

)

( )

{

[

(

)

]

[

(

)

]

}

( )

(

)

(

)

( )

{

[

(

)

]

[

(

)

]

}

( )

(

)

(

)

+





















+

−

+









+

+

⋅

⋅

+

−

+

+

⋅

⋅

+





















−

−

+









−

+

⋅

⋅

+

+

−

+

+

+

⋅

⋅

+





















+

−

+









+

+

⋅

⋅

+

⋅

⋅

=

2

5

2

cos

2

5

2

cos

4

2

cos

4

2

cos

2

3

2

cos

2

3

2

cos

2

2

cos

2

2

cos

2

2

cos

2

2

cos

2

cos

5 4 3 2 1 0

π

π

π

π

β

π

π

β

π

π

π

π

β

π

π

π

π

β

π

π

π

π

β

π

β

υ

t

f

f

t

f

f

J

V

t

f

f

t

f

f

J

V

t

f

f

t

f

f

J

V

t

f

f

t

f

f

J

V

t

f

f

t

f

f

J

V

t

f

J

V

t

m c m c c m c m c c m c m c c m c m c c m c m c c c c pm (2.21)

Fig. 2.7 shows the Bessel function Jn(β) versus β for n=0 to n=6.

Fig. 2.7: Bessel functions for n=0 to n=6

Some properties of the Bessel function can be discovered as follows:

• The higher side frequencies are insignificant in the PM spectrum when β is low.

• When β≤0.25, only J0(β), J1(β) have a significant value.

The power in a sinusoidal signal depends only on its amplitude and is independent of frequency and phase. It follows that the power in a PM signal equals the power in the un-modulated carrier

2

2

1

c PM

V

P

=

⋅

(2.22)

2.2 Phase modulation basics 17

The total power in a PM signal is the sum of the power of the sidebands and the carrier power. Hence, for the 1-tone modulation, the total power can also be obtained by summing the power in all spectral components in the PM spectrum

( )

( )













+

=

=

∑

∞ =1 2 2 0 2 2

2

2

1

2

1

n n c c PM

V

V

J

J

P

β

β

(2.23)

Obviously, the power in the side frequencies is obtained only at the expense of the carrier power

( )

2

( )

1

1 2 2 0

+

∑

=

∞ = n n

J

J

β

β

(2.24)

Power contained in the carrier frequency and the first N pairs of side frequencies is given by

( )

∑

( )

=

+

=

N n n N

J

J

r

1 2 2 0

β

2

β

(2.25)

Because the exact spectrum of the phase modulated signals is difficult to evaluate in general, formulas for the approximation of the spectra are very useful. As a rule-of-thumb, when N=β+1

( )

2

( )

0

.

9844

1 1 2 2 0 1

=

+

∑

=

+ = + β β

β

β

n n

J

J

r

_(2.26)

Equation (2.26) indicates that approximately 98% of the power of a phase modulated signal lies within the bandwidth covered by the first N=β+1 pairs of side frequencies. It is the minimum number of pairs of side frequencies that along with fc., account for 98% of the total PM power.

Carson’s bandwidth can be defined as

(

)

m

c

f

BW

=

2

⋅

β

+

1

⋅

(2.27) This formula gives a rule-of-thumb expression for evaluating the transmission bandwidth of PM signals; it is called Carson’s rule [39]. It gives an easy way to compute the effective bandwidth of PM signals from power perspective. In later chapters, this method will be used to evaluate the effective bandwidth of the time multiplexed receiver.

2.3

Phased-array basics

Phased-array antenna systems is one of the widely used multiple antenna systems in high fre-quency applications. In wave theory, a phased-array is a group of antennas in which the relative phases of the respective signals feeding the antennas are varied in such a way that the effective radiation pattern of the array is reinforced in a desired direction and suppressed in undesired directions [40]. Comparing with a conventional single path antenna system, two of the main benefits that a phased-array can provide are signal to noise ratio (SNR) enhancement and in-terference suppression [41-47] as a result of beam-forming.

A phased-array receiver consists of several signal paths, each connected to a separate antenna. Generally, radiated signal arrives at spatially separated antenna elements at different times. An ideal phased-array compensates for the time-delay difference between the elements and com-bines the signal coherently to enhance the reception from the desired direction, while rejecting emissions from other directions. The antenna elements of the array can be arranged in different spatial configurations.

d

θ

S

∆

θ

Fig. 2.8: (a) Simplified phased-array system model. (b) Time and phase relation.

Fig 2.8 (a) shows a simplified phased-array system model. For a plane wave, the signal arrives at each antenna element with a progressive time delay ∆t as in Fig. 2.8(b). This delay difference between two adjacent elements is related to their distance d and the signal angle of incidence θ by

c

d

t

=

⋅

sin

θ

∆

(2.28)

where c is the speed of light. While an ideal delay can compensate the arrival time differences at all frequencies, in narrow-band applications it can be approximated via other means. For a narrow-band signal, the amplitude and phase change slowly relatively to the carrier frequency. Therefore, we only need to compensate for the progressive phase difference

2.3 Phased-array basics 19

2

sin

S

π

d

ϕ

β

θ

λ

=

⋅ ∆ =

⋅

_(2.29)

Where φ is the electric phase difference between two adjacent channels; β is the phase constant; ∆S is the distance difference for adjacent channel in the wave propagation direction; λ=c/f is the wave-length in the air. Assume that d= λ/2,

sin

sin

2

t

f

ϕ

π

θ

θ

=

⋅







∆ =





(2.30)

For example, the incoming angle of 7.2° corresponds to an electrical phase shift of 22.5°. From the above equation, we can also find the relation between φ and ∆t as

2

S

t

T

ϕ

=

π

⋅

∆

_(2.31)

where Ts is the period of the propagation wave. Fig. 2.8(b) shows the relation between time and phase.

In a receiver chain, for a given modulation scheme, a maximum acceptable bit error rate (BER) translates to a minimum signal-to-noise ratio (SNR) at the base band output of the receiver (input of the demodulator). For a given receiver sensitivity, the output SNR sets an upper limit on the noise figure of the receiver. The noise figure (NF) is defined as the ratio of the total output noise power to the output noise power caused only by the source, as shown in (2.11), which cannot be directly applied to multiport systems, such as phased-arrays. Consider the n-path phased-array system, shown in Fig. 2.9. Sin is the input signal power; Nin is the input noise power;

N1 and N2 are the 1st and 2nd stage added noise power, respectively; G1 and G2 are the available

power gain of the 1st _{and 2}nd _{stage, respectively; k is the antenna number; K is the number of}

antennas; Ø is the phase difference between two adjacent channels to compensate the phase difference introduced by angle of incidence θ. We assume here that the noise power Nin and N1

G1 Sin G1 G1 G1 N1 N1 N1 N1 N2 G2 Sin Sin Sin Nin Nin Nin Nin Sout Nout 1 2 k K 3Ø 2Ø Ø 0

Fig. 2.9: Simplified model for n channels phased-array

Since the input signals are added coherently, taking into account the weighting factor for each channel when combiners are implemented in analog domain [48], then

in out

KG

G

S

S

=

_{1 2} (2.32)

The antenna’s noise contribution is primarily determined by the temperature of the object(s) at which it is pointed. When antenna noise sources are uncorrelated, such as in indoor environ-ment, and also the front-end noise sources are uncorrelated, the output total noise power is given by

(

N

N

1

)

G

1

G

2

N

2

G

2

N

_out

=

_in

+

⋅

+

(2.33) Thus, compared to the output SNR of a single-path receiver, the output SNR of the array is improved by a factor between K and K2, depending on the noise and gain contribution of dif-ferent stages. The array noise factor can be expressed as

(

)

out in in in

SNR

SNR

K

G

G

KN

G

N

G

G

N

N

K

F

=

+

+

=

2 1 2 2 2 1 1 (2.34)

2.3 Phased-array basics 21

which shows that the SNR at the phased-array output can be even larger than the SNR at the input if K>F. For a given NF, an n-array receiver improves the sensitivity by 10log(K) in decibels compared to a single-path receiver. For instance, an 8 element phased array can improve the receiver sensitivity by 9dB.

0

P

0

20 log

P

+

K

At the main beam direction 0 P 1 2 0 P 0 P 0 P k K 3Ø 2Ø Ø 0

Fig. 2.10: Simplified model of phased-array receiving system

Phased-array can enhance the receiving signal power, as shown in Fig. 2.10. Assume each an-tenna of a phased-array receives P0 power form the main beam direction. After phase shift and

combining, assuming no loss in between, the combined power in the main beam direction is P0+20log(K).

An additional advantage of a phased array is its ability to significantly attenuate the incident interference power from other directions. In a single-chain receiver, the linearity performance reflects on the third order input intercept point (IIP3). It is in many cases dominated by the interferer instead of the desired signal. A phased-array receiver has the advantage of enhancing the desired signal by adding the path signals in-phase, and reject the unwanted interferer (from another angle) by adding the path signals out-of-phase. This can be expressed as

( )

2 ( 1) ( 1) 1 C K j k j k j f t SUM k

s

A t

e

π

e

− ϕ

e

− − γ =

=

∑

⋅

⋅

⋅

_(2.35)

Where sSUM is the signal at the output; A(t) is the amplitude of the incoming signal and fC is the

carrier frequency; φis the input signal electric phase difference (can be either desired or unwanted signal), and γ is the electric phase compensation (for desired signal) on each path and γ=B*sinØ; k is the antenna number; K is the number of antennas. Furthermore, assuming antenna spacing

d=λ/2 (λ is the signal wavelength), the space angle θ(deg) can be transferred to a phase difference by 2 sin sin d π ϕ θ π θ λ = ⋅ ⋅ = ⋅ (2.36)

Combining (2.35) and (2.36), and taking only the absolute amplitude of sSUM, the normalized array

gain, ASUM, can be expressed as (for normalized signal amplitude, A(t)=1V)

( 1) sin ( 1) sin 1 K j k j k SUM k A e − π θ e− − π φ = =

∑

⋅ (2.37)

When K=1, it is a single antenna receiver without any directivity. Hence, the array gain is unity for all angles of incidence. When K≠1, multiple antennas produce antenna patterns which are a function of K, desired viewing angle θd, and un-desired viewing angle θi. Assuming θd=0°,

ad-justing Ø to the desired signal results Ø=0°. ASUM can be expressed in (2.38), and plotted in Fig.

2.11 with K=1, 2, 4, 8 as examples. ( 1) sin , 1

20 log

K j k SUM dB k

A

e

− π θ =

=

∑

_(2.38)

2.3 Phased-array basics 23

Here, we define a suppression factor L that describes the power rejection for θi relatively to the

power at θd

(

n i d

)

f

L= ,

θ

,

θ

(2.39)

For example, assume K=4 and θi=35° as shown in Fig. 2.11, the suppression from the peak

(K=4) is 12dB-(-5dB)=17dB, hence L= f(n=4, θi=35°, θd=0°)=-17dB (note that L in terms of dB

25

C h a p t e r

3

3

Single and multipath receiver: a

system approach

There are many ways to categorize receiver architectures. One of them is to categorize them into single-path receiver and multi-path receivers. A multi-path receiver is composed of many sin-gle-path receivers, hence they have some properties in common. Nevertheless, multi-path gives another dimension of design freedom to the receiver structure: the spatial dimension. In other words, a multi-path receiver has more properties than a single-path receiver. In this chapter, we will discuss single- and multi-path receivers from a system point of view.

We will start with single-path receiver analysis. As we know that a receiver chain can be separated into RF and ADC parts, at section 3.1, ADC parameters are translated into the RF domain, so that we can have a fair comparison/trade-off between them on system level. After that, the design trade-offs are discussed in section 3.2. The discussions are based on noise and linearity. An optimization method is introduced in section 3.3 to optimize the system for different ap-plications and purposes. The two categories of phased-array receivers: analog beam-forming and digital beam-forming are discussed in section 3.4 and 3.5, respectively. Both of them are first made equivalent to a single-path receiver, and then analyzed by the method in sections 3.1-3.3.

Section 3.6 introduces receiver structure that takes optimum advantage of both analog and dig-ital beam-forming. Section 3.7 concludes this chapter.

3.1

Translating ADC parameters to RF domain

The rapid growth of wireless communication has resulted in a shift of RF applications towards high frequencies. The increased bandwidth and dynamic range requires a systematic design strategy for RF receivers. RF system engineers are mainly focusing on the performance and power consumption of RF front-ends. The lack of a proper relation between RF blocks and ADC has led to the over-specifications of these blocks and a non-optimized system [49-58].

Fig. 3.1: Simplified receiver chain

Fig. 3.1 shows a simplified receiver chain including both RF front-end and ADC, where the interferers cause the dominant distortion. RF front-ends are usually characterized by noise figure (NF), power gain, third order input intercept point (IIP3) and power consumption [59]. The established theory enables the calculation of overall NF and IIP3 in cascaded RF blocks through the transformation of NF and IIP3 of each individual block. An extension of this theory enables the optimization of the overall power consumption through proper dimensioning of the indi-vidual RF blocks [60]. However, the main obstacles to a systematic design strategy for overall optimization are the lack of:

• a proper translation of ADC parameters into RF domain;

• a proper design flow reflecting the relation between RF and ADC blocks;

3.1 Translating ADC parameters to RF domain 27

3.1.1

ADC model

Fig. 3.2 shows the simplified front-end and ADC model. The main task of the Nyquist filter and the VGA consists in reducing the dynamic range of the ADC by providing some filtering of the blocking signals and the adjacent channels interference, and adjusting the signal level to the input range of the ADC.

Fig. 3.2: Simplified front-end and ADC model

The ADC component is modeled by two blocks: the non-linearity block and the ADC noise block. It is assumed that the transferred output signal has a unity gain, and no offset errors, compared to the input analog signal.

3.1.2

ADC noise

In ADC design, the parameters of interest are peak-to-peak full scale voltage (vFS)2, sampling

frequency (fsample), and number of bits (n). When noise is the product of quantization, the signal to

quantization noise ratio (SQNR) of an ideal ADC with full scale sinusoid wave as input is given by SQNR=6.02n+1.76 [61]. Fig. 3.3 shows the ADC quantization mechanism, where qS is the

ADC quantization noise in fundamental interval (fsample/2).

peak v peak v − s

q

FS

v

Fig. 3.3: ADC quantization mechanism

In case of oversampling, the signal bandwidth (BW) is less than fsample/2. Hence the ADC

quan-tization noise in the signal bandwidth BW can be further reduced as a result of the process gain, which is indicated by fsample/(2*BW). Fig. 3.4 shows the voltage relations.

SQNR FS

v

2 sample f BW ⋅

BW

Fig. 3.4: Voltage relations in ADC design

However, in practice, the ADC is not a stand-alone component; it is used in combination with the RF blocks in a receiver chain. From this perspective, assuming the input impedance of the ADC is 50Ω, the parameters of interest can be described as full scale input signal power3 _(P

FS),

sampling frequency (fsample), ADC signal to noise ratio (SNRADC), channel bandwidth (BW), and

ADC noise factor (FADC). Fig. 3.5 shows the conceptual translation from ADC noise design

parameters in volt to RF design parameters in mW. Note that this translation assumes a 50Ω matching at the input of the ADC, and the ADC noise factor (FADC) contains the contribution of

quantization as well as thermal noise.

3.1 Translating ADC parameters to RF domain 29 SQNR FS

v

ADC

SNR

FS

P

ADC

N

ADC

F

kT BW⋅ 2 sample f BW ⋅

BW

2

sample

f

BW

⋅

Fig. 3.5: Conceptual translation of ADC noise parameters to RF domain

It is more suitable to use effective number of bits (ENOBnoise) instead of n, because it includes

both ADC quantization noise (Q noise) and thermal noise (T noise), assuming that quantization noise behaves the same as thermal noise and has no correlation with the signal. In this case, one can write: SNRADC=6.02ENOBnoise+1.76. After proper derivation, the noise figure of the ADC,

NFADC, can be expressed as

(

)

, , 6.02 1.76 10 log 10 log 2 noise sample ADC FS dBm ADC dB ENOB f NF P kT BW SNR BW +  _{ }    = −_ ⋅ +  + _ ⋅      (3.1)

With the help of (3.1), we can directly include ADC noise into cascaded noise calculations of receiver systems.

3.1.3

ADC non-linearity

Non-linearity is the other major concern in ADC design. In a typical design, there are two pa-rameters of interest. Firstly, the effective full scale range voltage (vFS,eff), and secondly, the

har-monic distortion. For simplicity, we limit our analysis to memory-less, time-variant systems and assume then ) ( ) ( ) ( ) (t ₁x t ₂x2 t ₃x3 t y ≈

α

+

α

+

α

(3.2)

Fig. 3.6 visualizes the non-linearity model of the ADC. input

v

v

_h1 3 h

v

2 h

v

Fig. 3.6: Non-linearity model of ADC

where vinput is the magnitude of the fundamental of the analog input spectrum, note that v in-put<vFS,eff.. vh1 is the magnitude of the fundamental at the output. vh2 and vh3 is the magnitude of the

second and third harmonic at the output, respectively. In (3.2), if vinput=A, and x(t)=Acosωt, then

  2 2 3 3 1 2 3 3 3 2 2 3 3 2 2 1 2 3 1

( ) cos cos cos 3

cos cos 2 cos 3

2 4 2 4 h h h y t A t A t A t A A A A A t t t v v v α ω α ω α ω α α α α α ω ω ω = + +   = + +  + +    (3.3)

However, from RF system perspective, interferer signals often cause the dominant distortion (see Fig. 3.1). Thus the third order input intercept point IIP3ADC can be used to describe the ADC

global nonlinear property. IIP3ADC is a function of the fundamental output interference signal

(Iout), output third order intermodulation distortion product (DIM3,adc). Considering the unity

transfer of the ADC (GADC=1), one can express IIP3ADC as

, , 1 , , , 3, , 3 3 3 3 1 2 2 2 ADC dBm ADC dBm ADC dB

out dBm out dBm IM ADC dBm

IIP OIP IM I I D − = = + = − (3.4)

where OIP3ADC is the ADC output 3rd order intercept point, and (IM3ADC) -1

is the ratio between Iout and DIM3,ADC. Fig. 3.7 shows intermodulation in an ADC system. The input two tone signals

3.1 Translating ADC parameters to RF domain 31

property described in Fig. 3.6, and the output third order intermodulation product falls in fre-quency 2f1-f2 and 2f2-f1, respectively.

2 input v 3, IM ADC v fund

v

Fig. 3.7: Intermodulation in an ADC system

Similar to (3.3), vinput=A. Assuming input x(t)=(A/2)*(cosω1t+ cosω2t), then

(

)

(

)

(

)

2 1 3 1 2 3 3 2 1 1 2 3, 9 ( ) cos cos 4 2 3 cos 2 cos 2 4 2 fund IM ADC A y t A t t v A t t v

α

α

ω

ω

α

ω

ω

ω

ω

 _{ }  = +    +         + _{  } − + − _+   
 (3.5)

From (3.3) and (3.5), we can find the relation between vh3 and vIM3,ADC as

3 3 3 , 3 8 3 2 4 3 h ADC IM v A v  =      =

α

(3.6)

Hence, (3.4) can be re-written in terms of 3rd _{order harmonic power as}

, , ,

3 1 3

3 3 10 log

2 2 8

ADC dBm out dBm ADC dBm

IIP = I − H − (3.7)

where H3ADC is the power of the ADC 3rd order harmonics. To guarantee the integrity of the

• ∆P₁is the margin to the ADC full scale range power, for example DC offset and over-loading behavior, which depends on the ADC architecture. PFS/∆P1 indicates the ADC

effective input full scale power, which is the counterpart of vFS,eff.

• ∆P₂is the energy reduction from one tone input to two tone inputs (by each tone), which is usually half of voltage (6 dB). Hence, PFS/(∆P1*∆P2) is the input interferer power (by

each tone).

Fig. 3.8 shows the conceptual translation from ADC non-linearity design parameters in volt to RF design parameters in dBm. Note that this translation assumes a 50Ω matching at the input of ADC. , FS eff

v

3

_ADC

OIP

(=DADC) 3_ADC H Iout 3, IM ADC D (=IIP3ADC) FS

P

(=I_in) 2

P

∆

1

3

_ADC

IM

− 3 h

v

FS

v

1 P ∆

Fig. 3.8: Conceptual translated ADC non-linearity parameters to RF domain.

In the following chapters, it is assumed that interference signals are the dominant causes for ADC distortion in the desired channel, which means that DIM3,ADC is the dominant distortion

component. Moreover, DIM3,ADC is replaced by DADC which means ADC distortion power.

3.2

Mapping ADC parameters to system design

In many cases, the system performance is defined in terms of BER, which is a function of signal to noise and distortion ratio (SNDR). SNDR can be separated into signal to noise ratio (SNR) and signal to distortion ratio (SDR), in order to distinguish the contribution of noise and dis-tortion, and to enable the possibility of a trade-off for an optimum performance. From this perspective, it is very important to analyze the impact of ADC noise and distortion on the