Calibration of current-steering D/A Converters

(1)

Calibration of current-steering D/A Converters

Citation for published version (APA):

Radulov, G. I., Quinn, P. J., Hegt, J. A., & Roermund, van, A. H. M. (2009). Calibration of current-steering D/A Converters. In Proceedings of Analog/Mixed-signal Innovation Network "Digitally Assisted Analogue", 22nd October 2009, Dublin, Ireland (pp. 1-26)

Document status and date: Published: 01/01/2009 Document Version:

Publisher’s PDF, also known as Version of Record (includes final page, issue and volume numbers) Please check the document version of this publication:

• A submitted manuscript is the version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website.

• The final author version and the galley proof are versions of the publication after peer review.

• The final published version features the final layout of the paper including the volume, issue and page numbers.

Link to publication

General rights

Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. • Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain

• You may freely distribute the URL identifying the publication in the public portal.

If the publication is distributed under the terms of Article 25fa of the Dutch Copyright Act, indicated by the “Taverne” license above, please follow below link for the End User Agreement:

www.tue.nl/taverne

Take down policy

If you believe that this document breaches copyright please contact us at:

openaccess@tue.nl

providing details and we will investigate your claim. Download date: 04. Oct. 2021

(2)

Calibration of Current Steering

D/A Converters

ir. Georgi Radulov

1 _{, dr. ir. Patrick Quinn}

2 _{, dr. ir. Hans Hegt}

1 _,

prof. dr. ir. Arthur van Roermund

1

1 _{Eindhoven University of Technology}

(3)

Current-steering D/A converters

Applications demand performance;

Errors

limit performance;

Small errors demand huge resources.

Correction methods:

Improve performance and

Relax design requirements

(4)

Overview

• Mismatch problem;

• Current calibration method;

• MSB unary currents calibration in a 12b 250nm DAC

• All (MSB unary and LSB binary) currents calibration in a

quad-core 12b 180nm DAC;

• All currents calibration in a 12b-16b flexible 40nm DAC

• Conclusions

(5)

Mismatch problem

• Elements’ real values

deviate

• Deviation

depends on:

– Area

– Tech. and Circuit parameters

• High resolution D/A require

I

PDF(I)

I

MEAN

2 K

σ





∼

4 • High resolution D/A require

– Many and accurate elements

– Large silicon areas

• Large silicon areas

cause

– Systematic errors

– Drop of performance

(

)

_I

I

K

W

L

I

σ













~

∼

×

max

I

INL

I

n

⋅



_

σ



_





∼

~

(6)

I

_offset

1-bit

ADC

φ

φA: open

φ

φA: closed

FSM

Start-up calibration scheme

• Mismatch correction;

• Input offset cancellation;

• Two phases: φA, φB;

ADC

I

_temp

I

_ref

I

_th

(i)

temp

CALDAC

CALDAC(i)

φ

φA: open

φ

φB: closed

φ

φA: closed

φ

φB: open

φA: I

_temp

=I

_ref

- I

_offset

;

φB: I

_th

(i)=I

_temp

+ I

_offset

=I

_ref

;

with I

_ref

=ΣI

_bin

+ I

_LSB

;

(7)

12bit self-calibrating DAC in 250nm CMOS,

(8)

• 12b current-steering DAC;

• Segmentation: 6LSB/

6MSB

;

• 63 thermo bits calibrated;

12bit DAC implementation

• 6 binary not calibrated;

• Reference: binary bits;

• 5bit signed CALDACs;

• CMOS 0.25µm; Vdd 2.5V.

(9)

Chip micrograph

Latches

&

Decoder

Latches

&

Decoder

Input

drivers

• CMOS 0.25µm, 1P5M;

• Coarse (main) current

sources designed for 10b

accuracy in 0.1mm

2 ;

1.16mm

Coarse current sources

Array of CALDACs

FSM & 1bit ADC

Decoder

accuracy in 0.1mm ;

• Fully integrated

self-calibration in 0.3mm

2 _;

• 5 extra pads for calibration:

4 in & 1 out;

8 Cascodes M2, M3a, M3b

0 .9

8 m

m

(10)

Self-calibration of MSB unary currents

measurements

SFDR = 81dB

SFDR = 68dB

9

(11)

Self-calibration of MSB unary currents

measurements

HD (2,3,4,5)

(max) improvement +18dB

SFDR

improvement +13dB

10

(12)

Calibration potential

Distribution before calibration

• 3.5 LSB span,

σ

=1.06LSB;

• Tech. and design tolerances;

Distribution after calibration

• 0.2 LSB span,

σ

=0.03LSB;

• Calibration step sets the span;

technische universiteit eindhoven

Unary

currents:

(13)

-1.5 -1 -0.5 0 0.5 1 1.5 2 IN L [ L S B ] 2

• MSB unary part

dominate;

• INL

_max

= 1.5LSB;

Before

10b

Static performance

INL:

-2 0 500 1000 1500 2000 2500 3000 3500 4000 Digital code -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 0 500 1000 1500 2000 2500 3000 3500 4000 IN L [ L S B ] Digital code

After

12b

• LSB non-calibrated

binary part dominate;

• INL

_max

= 0.4LSB

12 technische universiteit eindhoven

INL:

+2b

(14)

Calibration of binary currents

Binary

_{no redundancy}

New sub-DAC segmentation (M binary sets)

redundancy

_ _ 1 _ 1 1 _ 1 _

( )(1)

( )(2)

( )(

1 :

( )(1) 1

:

2 :

( )(1) 1

:

1)

( )(2

:

)

:

3

ref bn ref bn B bin ref u i I B bin ref u bin bin b i I ref b n u in i

I

i

LSB

I

i

LSB

I

B

I

B

I

B

I

B

− = − =

+

=

+

=

+

=

∑

13 equal

1/2

(15)

12b-14b self-calibrating flexible DAC in

180nm CMOS,

(16)

Parallel sub-DAC units architecture

Current-steering DACs:

Parallel current sources (switch current cells),

which are switched in groups to create the

analog output;

a) Unary (Thermometer) grouping;

technische universiteit eindhoven

b) Binary grouping;

c) Segmented grouping;

d) Our NEW grouping: parallel sub-DACs

(with an exemplary implementation).

(17)

A 12-bit self-calibrated quad-core

current-steering DAC

recall:

1mm

2 f

or the

presented 12b DAC

(250nm CMOS)

16 0,2mm

2 per 12b DAC

(180nm CMOS)

(250nm CMOS)

-Large LSB binary part;

-Full calibration.

(18)

Calibration of unary and binary currents,

measurements

Before calibration

After calibration

INL

17 Before calibration

After calibration

(19)

Calibration of all DAC currents,

measurements

DAC accuracy depends only on a design parameter

(20)

Calibration of all DAC currents,

dynamic measurements

SFDR = 80dB

19

(21)

12b-16b self-calibrating flexible DAC in

40nm CMOS,

(22)

A 12b-16b self-calibrated flexible DAC in 40nm CMOS

Analog output

Construction of the full transfer characteristic

Off-chip

calibration

engine;

Flexibility;

A B C D E F G H I J K L M N O P A B C D E F G H I J K L M N O A B C D E F G H I J K L M N A B C D E F G H I J K L M A B C D E F G H I J K L A B C D E F G H I J K A B C D E F G H I J A B C D E F G H I A B C D E F G H A B C D E F G A B C D E F A B C D E A B C D A B C A B A B C DE F G HI J KL MN O P C DE F G HI J KL MN O P DE F G HI J KL MN O P EF G HI J KL MN OP F G HI J K L MN O P G HI J K L MN OP HI J K L MN OP I J K L MN OP J KL MN O P KL MN O P L MN O P MN OP NO P OP P