Original Article
Fabrication, electrical characterization and device simulation of
vertical P3HT
field-effect transistors
Bojian Xu
a,b,c, Tamer Dogan
a, Janine G.E. Wilbers
a,1, Michel P. de Jong
a,
Peter A. Bobbert
a,d,*, Wilfred G. van der Wiel
a,**aNanoElectronics Group, MESAþ Institute for Nanotechnology, University of Twente, P.O. Box 217, 7500 AE Enschede, The Netherlands bShenzhen Guohua Optoelectronics Tech. Co. Ltd., Shenzhen 518110, China
cSCNU-TUE Joint Lab of Device Integrated Responsive Materials (DIRM), National Center for International Research on Green Optoelectronics, South China
Normal University, No. 378, West Waihuan Road, Guangzhou Higher Education Mega Center, Guangzhou 510006, China
dMolecular Materials and Nanosystems, Department of Applied Physics, Eindhoven University of Technology, P.O. Box 513, 5600 MB Eindhoven, The
Netherlands
a r t i c l e i n f o
Article history:
Received 13 October 2017 Received in revised form 9 November 2017 Accepted 11 November 2017 Available online 20 November 2017
Keywords:
Vertical organicfield-effect transistor (VOFET)
P3HT (poly[3-hexylthiophene-2,5-diyl]) Wedging transfer
Reactive ion etching ATLAS device simulation
a b s t r a c t
Vertical organicfield-effect transistors (VOFETs) provide an advantage over lateral ones with respect to the possibility to conveniently reduce the channel length. This is beneficial for increasing both the cut-off frequency and current density in organicfield-effect transistor devices. We prepared P3HT (poly[3-hexylthiophene-2,5-diyl]) VOFETs with a surrounding gate electrode and gate dielectric around the vertical P3HT pillar junction. Measured output and transfer characteristics do not show a distinct gate effect, in contrast to device simulations. By introducing in the simulations an edge layer with a strongly reduced charge mobility, the gate effect is significantly reduced. We therefore propose that a damaged layer at the P3HT/dielectric interface could be the reason for the strong suppression of the gate effect. We also simulated how the gate effect depends on the device parameters. A smaller pillar diameter and a larger gate electrode-dielectric overlap both lead to better gate control. Our findings thus provide important design parameters for future VOFETs.
© 2017 The Authors. Publishing services by Elsevier B.V. on behalf of Vietnam National University, Hanoi. This is an open access article under the CC BY license (http://creativecommons.org/licenses/by/4.0/).
1. Introduction
Organicfield-effect transistors (OFETs) are extensively applied in low-cost[1],flexible[2], and biocompatible[3]electronic de-vices. It is critical to achieve high cutoff frequencies (~10 MHz) and large current densities (10e20 mA/cm2) to improve the device
performance for many OFET applications, such as organic light-emitting transistors or display pixel drivers[4e6]. In addition to applying high-mobility organic semiconductors, this can be ach-ieved by decreasing the OFET channel length[7e9]. Short-channel
OFETs are also beneficial for low-power electronic applications, since sizeable current densities can be obtained, even operating at low voltages[10,11].
In typical lateral OFETs, also known as organic thinfilm tran-sistors (OTFTs), the source and drain electrodes are in the same plane[12]. Usually, nanolithography techniques or high-resolution shadow masks are needed to fabricate short spacing electrodes
[13e15]. In VOFETs, by contrast, the source is positioned above the drain, or vice versa, and the current mainlyflows vertically. VOFETs are very attractive with respect to down scaling the channel length, since the distance between the top and bottom electrodes can be easily reduced in organic thin-film technology[7]. Although OFETs have been intensively studied, there are much less reports on VOFETs. Several approaches for realizing VOFETs have already been reported. Examples include the organic Schottky barrier transistors
[7,16e21], the step-edge VOFETs[7,22e28], the interdigitated ver-tical-channel OFETs [6,7], the vertical multichannel organic tran-sistors[7,29], the three-dimensional VOFETs[7,30e33], the central-gate vertical molecular transistors[34], the vertical organic light-* Corresponding author. NanoElectronics Group, MESAþ Institute for
Nanotechnology, University of Twente, P.O. Box 217, 7500 AE Enschede, The Netherlands.
** Corresponding author.
E-mail addresses:p.a.bobbert@tue.nl(P.A. Bobbert),w.g.vanderwiel@utwente.nl (W.G. van der Wiel).
Peer review under responsibility of Vietnam National University, Hanoi.
1 Present address: Raith B.V., De Dintel 27a, 5684 PS Best, The Netherlands.
Contents lists available atScienceDirect
Journal of Science: Advanced Materials and Devices
j o u r n a l h o m e p a g e : w w w . e l s e v i e r . c o m / l o c a t e / j s a m d
https://doi.org/10.1016/j.jsamd.2017.11.003
2468-2179/© 2017 The Authors. Publishing services by Elsevier B.V. on behalf of Vietnam National University, Hanoi. This is an open access article under the CC BY license (http://creativecommons.org/licenses/by/4.0/).
Fig. 1. Fabrication of VOFET devices. In each subfigure, the top is a top view and the bottom is a side view of the devices. (a) Fabrication of bottom electrodes (Pd, with Ti as adhesion layer) on SiO2substrates by photolithography. (b) Spin-coating of P3HT. (c) Wedging transfer of EBL patterned Pd disks. (d) RIE with O2ions for pillar formation. (e) ALD of Al2O3. (f)
Al gate electrodes patterned by photolithography. (g) Spin-coating of HSQ. (h) CHF3RIE to open the Al and Al2O3on top of the Pd top contacts. (i) Ar mechanical ion etching to
remove the Al, Al2O3, and partly HSQ, to open the Pd top contacts. (j) Second HSQ spin-coating; (k) CHF3RIE to open the Pd top contacts. (l) Patterning of large top electrodes by
emitting transistors (OLETs)[7,35e37]and the vertical OTFTs[38]. These vertical devices have different device structures and working principles. Due to the huge variety of device structures, it is chal-lenging to develop a unified working principle for VOFETs, and to compare between different device configurations.
In this report, the following pillar-shaped VOFET configuration is studied (see Fig. 1). An organicfilm is sandwiched between source and drain electrodes. The gate electrode and dielectric are either completely surrounding the two-terminal pillar or are only deposited from one side. Hence, the channel length is deter-mined by the organic layer thickness. This particular VOFET ge-ometry has to the best of our knowledge not yet been investigated. In this vertical configuration, fabricating contacts on top of the thin organicfilm, and patterning of the organic film are challenging. For the top contacting, the main difficulty is to de-posit the metal contact without damaging the organic film or introducing an additional resistance or an oxide layer. As for the patterning, chemicals used in standard nanolithography, e.g., photolithography and electron beam lithography as well as lift-off processes can affect the organicfilms [39,40]. In our previ-ous work [4], we have already demonstrated a fabrication method that can realize robust vertical P3HT (poly[3-hexylthiophene-2,5-diyl]) pillar devices with ultrashort (down to 5 nm) junction length, and submicron lateral dimensions (down to 200 nm). Following up on that work, we fabricated a surrounding gate electrode and a gate dielectric around the vertical P3HT pillars to add gate control to the electrical trans-port. On applying a voltage to the surrounding gate electrode, we expect the formation of a conductive channel at the circumfer-ence of the P3HT pillars. We measured output and transfer characteristics of those novel devices (see Section3). Numerical device simulations using the ATLAS software [43] were per-formed as well (see Section4).
2. Device fabrication
In this section, the fabrication process of the gated devices is briefly described. More details are provided in Refs. [4,41]. The whole fabrication process is schematically shown in Fig. 1. We employed a water-based wedging transfer technique [42] and directional oxygen plasma reactive ion etching (RIE) to prepare P3HT pillars with palladium top contacts (Fig. 1(a)e(d)). The P3HT thickness of the gated devices was 100 nm, and the pillars had diameters d¼ 2
m
m, 1m
m, 500 nm and 200 nm. The main difference with the process described in Ref. [4] is that the Al2O3 gatedielectric and Al gate electrodes were fabricated before applying the contact pads of the top electrodes. The conformal Al2O3gate
dielectric was grown by atomic layer deposition (ALD) (Fig. 1(e)). The Al gate electrodes were evaporated and patterned by photoli-thography (Fig. 1(f)).
We found that when the sample straightly faced the evaporation source during the Al deposition, the overlap of the gate dielectric and the gate electrode around the pillars was very small, as shown inFig. 2(a). The reason is that the top Pd contact acts as a shadow mask, and suppresses the deposition of Al in the region closely around the gate dielectric. Hence, we tilted the sample by 45such that the Al was evaporated from one side. Using this method, we found that the overlap became larger, as shown inFig. 2(b). The disadvantage is that the gate electrode does not contact the gate dielectric at the other side of the pillar. In the following, the former device type is called“full-gate” and the latter type is called “half-gate”.
After fabrication of the Al gate electrodes, hydrogen silses-quioxane (HSQ) was spin-coated to planarize the sample surface (Fig. 1(g)). After this, CHF3reactive ion etching (RIE) was used to
remove the HSQ on top of the pillars, thereby opening the Al on top of the pillars (Fig. 1(h)). In the following step, the Al and Al2O3 on top of the pillars were etched away by reactive ion
beam etching (RIBE) with Ar ions (Fig. 1(i)) to expose the top Pd contacts. At RIE, one has a plasma between two electrodes, with a substrate usually lying on one of the electrodes. The ions collide due to the small free path length (1 mme1 cm) with other atoms and ions. So one etches with ions and not directionally. At RIBE, one has a plasma between two electrodes whose negative elec-trode is a grid, causing the ions to pass through. The ions are then accelerated by a negative acceleration voltage and then neutralized by a neutralizer. The pressure in the room is lower and the free path length is much larger (a few meters). One thus etches with neutral argon atoms and directionally. Conductive-probe AFM was used to check if the Pd top contacts were completely exposed. Once the exposure was verified, we spin-coated a new HSQ layer (Fig. 1(j)) since thefirst HSQ layer was already very thin and not well insulating after the above two steps of dry etching. Back-etching of the new HSQ layer was performed to open the Pd top contacts (Fig. 1(k)). After this step, conductive-probe AFM was used again to check if the HSQ on top of the Pd top contacts was etched away. Finally, large top elec-trodes were deposited and patterned by photolithography and mechanically by RIE (Fig. 1(l)).
3. Electrical characterization
The electrical transport properties of the devices were measured at room temperature (294 K) in a turbo-pumped vacuum (~105106mbar) to suppress the air instability mentioned in
Ref.[4]. We used a probe station connected with an Agilent B2912A precision source/measure unit for these measurement. The bottom Pd electrodes were set as the source electrodes, which were always the common ground.
Fig. 2. Colored SEM images showing cross sections of the full-gate (a) and the half-gate (b) test devices: P3HT (100 nm, green), Pd top electrode (150 nm, yellow), Pd bottom electrode (20 nm, yellow), Al2O3gate dielectric (25 nm, purple), and Al gate
Fig. 3shows the transport characteristics of a half-gate device with d¼ 1
m
m P3HT diameter. InFig. 3(a), the top panel shows a measurement of the drain current IDwhen sweeping thesource-drain voltage and alternating the gate-source voltage VGS
be-tween 10 V and 10 V. The top panel ofFig. 3(b) shows IDas a
function of VGS, at different drain-source voltage VDS. The bottom
panels in Fig. 3 show the corresponding gate leakage measure-ments. The results do not show a distinct gate effect, apart from a small drift of ID when sweeping VGS and keeping VDS constant
(Fig. 3(b)). All full-gate and most half-gate devices show similar results. We also exchanged the source and drain electrodes, that is, we grounded the top Pd electrodes. Again, no distinct gate effect was observed.
We observed somewhat different IDeVGSresults in two devices,
one with d¼ 1
m
m and one with d¼ 200 nm, although the output properties of the two devices did not show a distinct gate effect. While measuring transfer characteristics, IDslightly changed withthe gate voltage. Specifically, IDincreased when VGSbecame more
negative. In addition, when VGSwas swept from negative to
posi-tive, IDdecreased, as shown inFig. 4. Linearfitting reveals that the
transconductance ((IDmaxeIDmin)/(VGSmaxeVGSmin), similarly
here-after) is 1 pS for VDS¼ 3 V and 3 pS for VDS¼ 5 V for the device
with d¼ 1
m
m (Fig. 4(a)). For the device with d¼ 200 nm, the transconductance is only 0.13 pS when VDS¼ 5 V (Fig. 4(b)). Thetwo devices were measured again before breakdown due to a too large gate voltage applied. The weak effect was reproducible. It is not likely that this weak gate dependence is due to the drift of the drain current. As shown inFig. 3(b), the drift of IDis always in one
direction, regardless of the sweep direction of the gate voltage. It is not likely either that the weak gate dependence is due to the leakage between the gate and the drain. During the measurement, the source was the common ground in the IDand IGmeasurement
circuits. If there was leakage through the dielectric between the gate and the drain, the IGsignal would add to the IDone, thereby
making IDmore positive when IGbecomes more negative. One can
see in the bottom panel ofFigs. 3(b) and 4thatjIGj is getting larger
thanjIDj when VGSapproaches to10 V. The weak gate dependence
indicates that there is probably some p-type channel behavior in the devices, which could be related to the p-type semiconductor nature of P3HT. We cannot draw a definite conclusion, however,
Fig. 4. Transfer characteristics of two half-gate devices. Symbols are measured data and green lines are linearfits. (a) d ¼ 1mm. (b) d¼ 200 nm. VGSwasfirst swept from 0 to 12 V,
then to12 V, and finally back to 0 V. The gate leakage results are similar toFig. 3(b).
Fig. 3. Output (top panel of (a)) and transfer (top panel of (b)) characteristics of a half-gate device with d¼ 1mm P3HT diameter. The bottom panels are corresponding IG
measurement results. (a) VGSwas set to 0 (black squares), 10 (red dots), 0 (blue up triangles),10 (pink down triangles), and 0 V (green diamonds), respectively. VDSwasfirst swept
from 0 to 2 V, then to2 V, and finally back to 0 V. (b) VDSwas set to 1.75 V (black squares),1 V (red dots), and 2 V (blue up triangles), respectively. VGSwasfirst swept from 0 to
because of the small effect, and because it was only observed in two devices.
In summary, neither of the full-gate and half-gate devices showed a significant gate effect. Two half-gate devices showed a weak gate effect. In the following section we discuss device simu-lation results and possible reasons for the absence of a significant gate effect.
4. ATLAS device simulations
We performed numerical device simulations using ATLAS soft-ware[43]to investigate the output and transfer characteristics of the gated P3HT pillar devices. The simulations are based on the drift-diffusion model for electrical transport with a Gaussian den-sity of states (DOS) [44]. Since the pillar structures are radially
Fig. 6. Simulation results for the device with a 200 nm diameter P3HT layer with 73 nm gate electrode height and 25 nm oxide thickness. (a) Output characteristics for three different values of VGS. (b) Transfer characteristics for VDS¼ 5 V. (c) Hole concentration (log scale) in the whole P3HT region for VGS¼ VDS¼ 5 V. (d) Hole current density (log
scale) in the region close to the interface when VGS¼ VDS¼ 5 V. The rightmost oxide region is not completely shown here (similarly hereafter).
Fig. 5. The 2D cylindrical mesh. (a) Rotation of a 2D rectangle to form a 3D cylinder. (b) Mesh grid on the 2D rectangle. The rightmost part of the rectangle is the gate dielectric; source, drain and gate electrodes were set as top, bottom and right boundaries, respectively (similarly hereafter). The X axis is the distance from the center of the pillars, and the Y axis is the distance from the source, which is always at Y¼ 0 (similarly hereafter). The drawn situation corresponds to a 3D pillar device with P3HT diameter of 2mm and thickness of 100 nm, and a thickness of the gate dielectric of 20 nm. All the regions close to the interfaces werefinely meshed with a 1 nm mesh size. Other regions were more coarsely meshed.
symmetric, we employed a 2D cylindrical mesh method to transfer the 3D structure to a 2D structure in order to decrease simulation time.Fig. 5(a) schematically shows the construction of the 2D cy-lindrical mesh. When a 2D rectangle is rotated by 360with one of its sides as the axis of rotation, it forms a cylinder. In this method, only the 2D rectangle needs to be meshed. The simulation results for the rectangle are then rotated to obtain the results in the 3D device (Fig. 5(b)). Although the half-gate devices are not radially symmetric, we assume that the gating at only side only implies a partial loss of the gate control. Hence, we used the same mesh method to simulate the half-gate devices.
We simulated the characteristics of device with d ¼ 200 nm P3HT diameter. We took 25 nm and 73 nm for the gate dielectric thickness and gate electrode height (the vertical length of the contact area between the gate electrode and the gate dielectric), respectively, according to the SEM image of the half-gate device (Fig. 2(b)). Since we obtained excellent agreement of the modeled
and the measured results for the two-terminal devices with 100 nm P3HT thickness in Ref.[4], we used the same parameters in the drift-diffusion model incorporated in ATLAS for the device simulations in this report. Hence, we set the room-temperature, zero-concentration, zero-field hopping mobility
m
0 to7 109m2/Vs, the site density N
tto 1.5 1026m3, and the width
of the Gaussian DOS
s
to 0.075 eV. The P3HT dielectric constant εr¼ 4.4 was taken from Ref.[45].The simulation results demonstrate a distinct gate effect, as shown in the simulated output and transfer characteristics (Fig. 6(a) and (b)). The hole concentration and hole current density distributions demonstrate that the accumulation layer thickness is only a few nanometers (Fig. 6(c) and (d)). The transconductance is of the order of nS, which is much larger than what we measured in the devices that showed some gate control (Fig. 4(b)). Further-more, the simulated current is many times larger than the measured results (Fig. 7(e) and (f)). When V< 3 V, we can see
Fig. 7. Discrepancy between simulated and measured results for full-gate and half-gate devices with four different diameters of the P3HT layers. In (a)e(d), red open circles are averaged measurement results of all full-gate devices and red solid circles are simulated results of the full-gate devices (10 nm gate electrode height) at VGS¼ 0 V; blue open
triangles are averaged measurement results of all half-gate devices and blue solid triangles are simulated results of the half-gate devices (73 nm gate electrode height) at VGS¼ 0 V;
black solid squares are simulated results of the non-gated devices. Dashed and solid lines represent the slope k¼ 1 and k ¼ 2, respectively. (e)e(f) Ratio of the simulated to the measured results of full-gate (e) and half-gate (f) devices with different P3HT pillar diameters.
that the ratio of the simulated to the measured drain currents at zero gate voltage decreases when the voltage approaches5 V. When V> 3 V (smaller negative voltages), the conductivity of devices with d¼ 200 nm P3HT diameter is very low. Therefore, the measured results are very noisy and limited by noise level (Fig. 7(d)), with an unstable ratio that decreases with increasing voltage (Fig. 7(e) and (f)). Half-gate devices and full-gate devices (with a smaller gate electrode height than the half-gate devices, set as 10 nm in accordance withFig. 2(a)) with larger diameters than d¼ 200 nm were simulated as well. The simulated results all show a distinct gate effect. Different from the device with d¼ 200 nm P3HT diameter, the ratio is smaller and decreases from more than an order of magnitude to a few times when the voltage changes from0.2 V to 5 V, as shown inFig. 7(e) and (f). The dependence of the ratio on the voltage is related to the difference between the simulated and the measured JeV characteristics. In
Fig. 7(a)e(c), the slope k of the measured logJelogV characteristics reaches 2 at lower voltages than in the simulated results. In our device, Pd was used for both top and bottom contacts and the injection barrier is expected to be very low according to our
previous results[4]. For such kind of devices, the slope k¼ 2 in-dicates the space-charge-limited current (SCLC) regime. According to the SCLC theory, there is usually an ohmic regime where k¼ 1 at sufficiently low voltages[46e48]. Although the simulations and the measurements in this report did not cover that voltage regime completely, we can see inFigs. 7(a)e(c) that there is a transition from k< 2 to k ¼ 2. In the ohmic regime, the current is due to the thermal equilibrium charge carriers. With increasing voltage, more and more charge carriers are injected into the organic, thereby building up electric potential, and hence limiting the charge carrier injection. When the injected charge carrier density exceeds the thermal equilibrium density of charge carriers that have diffused from the electrodes into the organic layer, the cur-rent changes from ohmic to SCLC. So, the transition voltage at which the lines with k¼ 1 and k ¼ 2 intersect is proportional to the thermal equilibrium charge carrier density [46,48]. It has been pointed out that the ohmic regime in such kind of devices is due to the charge carriers that have diffused from the electrodes into the organic layer. A smaller transition voltage indicates a smaller thermal equilibrium charge carrier density, leading to a lower charge carrier mobility[47,49].Figs. 7(a)e(d) show that the dif-ference between half-gate and full-gate devices is largest for 200 nm, both in experiment and simulations, and that this dif-ference vanishes for larger diameter. We suppose this is due to the overall increase of the effect of gating for the thinnest devices. From the simulation results we conclude that there is not only a difference between simulations and experiments regarding the gate effect, but also regarding the size of the conductivity of the devices, especially for the device with d¼ 200 nm P3HT diameter. In the following simulation results, we will show how the mobility affects the gate effect and the device conductivity.
Since gate control of transistors is mainly caused by the gener-ation of an accumulgener-ation layer in the region close to the semi-conductor/dielectric interface, the reason for the almost absent gate effect in our devices probably lies in the region where the accumulation layer is supposed to be created. We used directional O2plasma RIE to etch the P3HT, but it is very likely that the oxygen
ions are scattered and spread out. Therefore, the outermost part of the P3HT pillars is possibly damaged by the oxygen ions, leading to dangling bonds and therefore traps in that region. Even though charge carriers could be accumulated there by the gatefield, they would not freely move. We therefore assume a smaller room-temperature, zero-concentration, zero-field, hopping mobility
m
0in a thin edge region of the P3HT pillar close to the P3HT/Al2O3
interface, as shown inFig. 8. Fig. 8. 5 nm thick damaged region (the shaded area) close to the interface with the
oxide of a half-gate device with d¼ 200 nm P3HT diameter (73 nm gate electrode height and 25 nm oxide thickness). In reality, the damaged region will very likely have a different shape. We assigned a smaller mobility to the damaged region than to the undamaged P3HT. We only modulated the thickness and the mobility of the damaged region in our analysis.
Fig. 9. Transfer characteristics simulated with and without the damaged layers. (a) Different thicknesses of the damaged layer for a mobility in the damaged layer reduced by a factor 0.01: 0 nm (black squares), 5 nm (red dots) and 50 nm (blue up triangles). (b) Damaged layer with thickness of 5 nm and unreduced mobility (black squares), and mobilities reduced by a factor 0.1 (blue up triangles), 0.01 (red solid circles), and 0.001 (pink down triangles).
The simulation results shown inFig. 9reveal that even a 5 nm damaged layer with 10% of the mobility of undamaged P3HT can already significantly suppress the gate effect. The hole current flow in the damaged region is suppressed, but the hole accumulation in the damaged layer is not significantly affected, as shown inFig. 10. These simulation results indicate that a damaged layer could indeed be the cause of the strong suppression of the gate effect. Therefore, to prevent the formation of such a layer in fabrication, using RIE to
form P3HT pillars is probably not the most suitable method. We need to consider alternative methods for the fabrication of VOFETs with a similar structure as described in this report. For example, we can fill in the pores of an anodic Al2O3 (AAO) template with an
organic semiconductor to form organic-dielectric coreeshell struc-tures[50e52]. The bottom and the surrounding electrodes, and the top electrodes could be fabricated before and after the filling respectively, thereby obtaining organic nanowire transistors[53].
Fig. 10. Hole concentration ((a)e(c), log scale) and hole current density ((d)e(f), log scale) in the region close to the organic/dielectric interface, for VGS¼ VDS¼ 5 V. In (a) and (d)
there is no damaged layer. The damaged layer thickness is 5 nm for (b), (c), (e) and (f). The mobility of the damaged layer was set to 0.1 of the mobility of undamaged P3HT for (b) and (e), and to 0.001 of this mobility for (c) and (f).
However, both the gate effect and the magnitude of the drain current simulated with the damaged layer, either 5 nm thick with 0.001
m
0or 50 nm thick with 0.01m
0, are still largerthan the experimental results. Therefore, wefixed the decreased mobility at a very low value (1010
m
0), corresponding to theassumption that the damaged part is completely insulating, and then changed the thickness of the damaged layer to see when the simulated transconductance matches the experimental re-sults. The simulation results reveal that, for the device with d¼ 200 nm P3HT diameter, when the damaged layer is 81 nm thick, the transconductance drops to about 0.9 pS, which is close to the experimental result. Moreover, the magnitude of the current is then close to the measured result as well, as shown in
Fig. 11. Hence, both the weak gate effect and the small current in the experiment can be explained by assuming a thick damaged layer. We performed similar simulations for the devices with 1
m
m P3HT diameter. Wefind that the thickness of the damaged layer then has to be about 200 nm to obtain simulation results for the gate effect and the size of the current that are roughly equal to the measured data. As for the devices with d¼ 2m
m and 500 nm, we find that the damaged layer thickness has to be about 500 nm and 100 nm respectively, to obtain a rough agreement. These results suggest that the damaged P3HT region in those devices is very thick. It seems unlikely that RIE can lead to such thick damaged regions. Hence, there are probably other factors that lead to a reduction of the gate effect and the current. It has been reported that P3HT OFETs stored in air can be affected by water and oxygen[54]. The fabrication and storage time for the gated P3HT devices, the time span between the beginning of the device fabrication and the measurements, is aboutfive months for the present gated devices. By contrast, the corresponding time span for the devices with 100 nm P3HT thickness mentioned in Ref.[4]is about two weeks. Hence, we suspect that the gated P3HT devices were probably severely affected by water and oxygen due to the long fabrication and storage time.4.1. Gate electrode height dependence
Fig. 2shows that the full-gate device has a much smaller gate electrode height than the half-gate devices. Hence, we examined the influence of the height of the gate electrodes on the gate effect. We simulated three devices that all had a d¼ 2
m
m P3HT diameter and a 20 nm oxide thickness, but three different gate electrodeheights: 10 nm, 52 nm and 100 nm, respectively. FromFig. 12we see that the gate effect is strengthened when the gate electrode height is increased. The hole concentration plots reveal that the stronger gate effect is caused both by a larger hole concentration around the source contact atfinite gate voltage (Fig. 13(a) and (b)) and a stronger depletion of charge carriers around the drain contact at zero gate voltage (Fig. 13(c) and (d)).
4.2. Dependence on the diameter of the P3HT pillars
Also the influence of the diameter d of the P3HT pillars on the gate effect was investigated. We found that even for a gate elec-trode height of 100 nm, that is, a gate elecelec-trode fully covering the gate dielectric around the pillars, the source-drain current in the output characteristics was still not saturated in devices with a large P3HT pillar diameter (e.g., d¼ 2
m
m) when the source-drain voltage was larger than the gate voltage (Fig. 14(a)). As the diameter d was decreased, the source-drain current became more and more satu-rated for non-zero gate voltage. At zero gate voltage, the source-drain current became smaller and smaller with decreasing d until it was essentially zero (Fig. 14(b)e(d)). This effect is similar to the short-channel effect in lateral OFETs [55], resulting from a decreasing channel length. The reason behind this phenomenon is the dominance of the total current by the bulk SCLC, instead of the channel conduction. It was reported that limiting the bulk SCLC region can suppress the short channel effect[56,57]. This is anal-ogous to the situation in the vertical P3HT devices, where the current in the bulk region decreases relatively to that in the channel by decreasing the P3HT pillar diameter. FromFig. 15we can see that in the region far (~200 nm) away from the gate dielectric in the device with the larger P3HT pillar diameter the hole concentration distribution is not affected by the gate voltage. By contrast, in the device with the smaller P3HT pillar diameter the distribution in the whole region is affected by the gate voltage.4.3. Gate electrode position dependence
Above, we concluded that the higher the gate electrode, the better the gate control. But when the gate electrode does not completely cover the gate dielectric between source and drain, would it then matter if the gate is close to the source or the drain? Device simulation results show that the gate effect is also Fig. 11. Simulated transfer characteristic of a device with d¼ 200 nm P3HT diameter,
73 nm gate electrode height, 25 nm oxide thickness and 81 nm damaged region thickness.
Fig. 12. Simulated transfer characteristics of three devices with different gate elec-trode height. The devices have a P3HT diameter and oxide thickness of 2mm and 20 nm, respectively. The height of the gate electrodes is 10 nm, 52 nm and 100 nm, respectively, as shown schematically on the top.
Fig. 13. Hole concentration distributions (log scale) in two devices, zoomed into the region close to the organic/dielectric interface. (a) 100 nm high gate electrode, with VGS¼ VDS¼ 5 V.
(b) 10 nm high gate electrode, with VGS¼ VDS¼ 5 V. (c) 100 nm high gate electrode, with VGS¼ 0 V, VDS¼ 5 V. (d) 10 nm high gate electrode, with VGS¼ 0 V, VDS¼ 5 V.
Fig. 14. Simulated output characteristics of gated P3HT devices with four different P3HT pillar diameters d. The gate electrode height is 100 nm and the oxide thickness is 20 nm. The gate voltage VGSwasfixed at three values: 0 V (blue left triangles), 2.5 V (pink down triangles) and 5 V (green diamonds). In (c), the maximum size of IDat zero VGSis
influenced by the position of the gate electrode when the gate electrode does not completely cover the dielectric. We simulated transfer properties of devices with 10 nm high gate electrodes at different positions: close to the drain, close to the source, and in the middle between the drain and the source, as shown schematically in the top ofFig. 16. The simulated transfer properties reveal that
devices with a gate in the middle have the largest transconductance (see main panel inFig. 16).
To understand this, we compare both the hole concentration and the hole current density distributions for the three cases. When VGS¼ 5 V, devices with gate electrodes close to the drain
have the smallest hole concentration around the source (Fig. 17(c)), because the gate electrodes are far away from the source. A poor accumulation layer results in a small conductivity (Fig. 17(f)). Devices with gate electrodes close to the source have the largest hole concentration in the accumulation layer around the source (Fig. 17(a)). However, their channel region is farther away from the drain than for devices with the gate in the middle (Fig. 17(b)). Therefore, a longer SCLC region is needed to bridge the channel region and the drain. Eventually, the total conductivity is smaller in the devices with the gate close to the source than in the devices with the gate in the middle; see the difference between
Fig. 17(d) and (e).
Similarly, when VGS ¼ 0 V, devices with gate close to source
have the smallest depletion region around the drain (Fig. 18(a)). Hence, those devices show the largest conductivity (Fig. 18(d)). As for devices with the gate close to the drain, although they have the strongest carrier depletion around the drain, the charge car-riers around the source are the least depleted, because the gate electrode is further away from the source (Fig. 18(c)) as compared to the other two types of devices. The charge carrier conduction path between source and drain is built up as shown inFig. 18(f). Fig. 15. Hole concentration (log scale) in the devices corresponding to the simulation results ofFig. 14. (a) d¼ 2mm, VGS¼ 5 V and VDS¼ 15 V. (b) d ¼ 50 nm, VGS¼ 5 V and
VDS¼ 15 V. (c) d ¼ 2mm, VGS¼ 0 V and VDS¼ 15 V. (b) d ¼ 50 nm, VGS¼ 0 V and VDS¼ 15 V.
Fig. 16. Simulated transfer characteristics of three devices with different gate electrode positions. The three devices have the same P3HT pillar diameter d¼ 2mm, the same oxide thickness of 20 nm, and the same gate electrode height of 10 nm. The position of the gate electrode is shown schematically on the top.
As for the devices with gate in the middle, they have a moderate depletion around both drain and source (Fig. 18(b)), and eventu-ally the most suppressed conduction close to the interface (Fig. 18(e)).
5. Conclusion
We have fabricated vertical organic field-effect transistors (VOFETs) that consist of pillars of poly[3-hexylthiophene-2,5-diyl] (P3HT) with a gate that completely or half surrounds the pillars. We found that measured electrical characteristics do not show a distinct gate effect. Only two of our half-gate devices show a weak gate effect. Simulation results of ideal devices show not only a distinct gate effect, but also a larger drain current than in the
experiment. Both the size of the gate effect and the drain current are dramatically reduced in the simulations by assuming a layer at the edge of the P3HT pillars that is damaged by the reactive-ion etching. This suggest that a damaged layer could be a reason for the reduction of the gate effect and the conductivity. To obtain a reasonable agreement between simulated and measured results, however, the damaged layer has to be assumed to be very thick. Therefore, we believe that there are also other reasons for the reduction of the gate effect and the conductivity. We suspect that the devices were probably severely affected by water and oxygen due to the long fabrication and storage time before the measure-ments. Device simulation results also show that a smaller diameter of the P3HT pillars, a larger overlap of the gate dielectric and gate electrode both lead to better gate control. In future work on these Fig. 17. Hole concentration (log scale, (a)e(c)) and hole current density (linear scale, (d)e(f)) distribution corresponding to the results ofFig. 16when VGS¼ 5 V and VDS¼ 5 V.
VOFETs, the most critical issue is to keep the organic/dielectric interface as intact as possible during the fabrication. In addition, regions with a large bulk current, small overlap of the gate dielectric and gate electrode, should all be avoided as much as possible to enhance the gate control.
Acknowledgements
This work wasfinancially supported by the NWO-nano (STW) program, grant no. 11470 (W.G. van der Wiel), the China Scholarship
Council (grant no. 201206090154) and the Guangdong Innovative Research Team Program (No. 2013C102). We thank Martin H. Siekman, Thijs Bolhuis and Johnny G.M. Sanderink for technical support. We thank Dr. Ray J. E. Hueting for fruitful discussions.We thank Prof. Dr. Guofu Zhou for technical discussion.
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