Field-plate assisted RESURF power
devices:
Gradient based optimization,
degradation and analysis
dr. ir. J.J. Koning Eindhoven University of Technology
dr. G.E.J. Koops ON Semiconductor
This work is part of the Dutch Point-One program and is supported financially by Agentschap NL, an agency of the Dutch Ministry of Economic Affairs.
MESA+ Institute for Nanotechnology, University of Twente
P.O.Box 217, 7500 AE Enschede, the Netherlands
Copyright c 2015 by Boni K. Boksteen, Enschede, The Netherlands.
This work is licensed under the Creative Commons Attribution-Non-Commercial 3.0 Netherlands License. To view a copy of this license, visit
http://creativecommons.org/licenses/by-nc/3.0/nl/or send a letter to Creative Commons, 171 Second Street, Suite 300, San Francisco, California 94105, USA.
Typeset with LATEX.
Printed by Gildeprint Drukkerijen, Enschede, The Netherlands.
ISBN 978-90-365-3931-9
DOI 10.3990/1.9789036539319
F
IELD
-
PLATE ASSISTED
RESURF
POWER
DEVICES
:
G
RADIENT BASED OPTIMIZATION
,
DEGRADATION AND ANALYSIS
P
ROEFSCHRIFT
ter verkrijging van
de graad van doctor aan de Universiteit Twente, op gezag van de rector magnificus,
prof. dr. H. Brinksma,
volgens besluit van het College voor Promoties in het openbaar te verdedigen
op woensdag 26 augustus 2015 om 12.45 uur
door
Boni Kofi Boksteen
geboren op 15 augustus 1986 te Paramaribo, Suriname
To my Parents
A
BSTRACT
Compact fluorescent and solid-state lights rapidly gain ground in the light-ing market. Developments in the size, efficiency and reliability of these light sources are accompanied by advancements in the embedded elec-tronics driving them. The long lifetime of these light sources requires that the electronics parts last at least equally long. The power transistor, a transistor specially designed to withstand high voltages or currents, is a key component in these and many other (e.g. automotive) electronics.
This PhD-work focuses on the development of optimization method-ologies for these power transistors and studies how long-term electrical stress affects their performance. The developed (gradient based) optimized device designs result in smaller and therefore less expensive transistors with an almost constant internal electric field (Reduced SURface Field -RESURF) having many unique features useful for modeling and the pre-diction of electrical behavior. During electrical stress however, parasitic charge can build up in certain locations, thus distorting the electric field distribution which in turn leads to changing (potentially destructive) tran-sistor performance.
The main mechanisms responsible for degradation in these transistors under different stress conditions are identified, as well as the location in the transistor where the stress induced physical and chemical changes take place. Diagnostic techniques and analytical models were subsequently developed to allow the prediction of the transistor’s performance after stress. As such, this work provides the necessary insights and tools for the design and in depth electrical characterization of gradient based field-plate assisted RESURF optimized power transistors before and after electrical stress.
Overview
Each chapter in this work is based on, and expands upon, published work performed throughout my PhD track.
Field (RESURF) device design based on: ’Design optimization of field-plate assisted RESURF devices’ published in 2013 as part of the 25th ISPSD pro-ceedings, Kanazawa Japan [2]. This chapter provides design rules on how to optimize the electric field distribution for different types of dielectric based RESURF while also focusing on reducing the specific on resistance.
Chapter 3: Field changes and degradation due to interface charge in
FP assisted RESURF devices based on: ’Impact of interface charge on the elec-trostatics of field-plate assisted RESURF Devices’ published in 2014 in IEEE Transactions on Electron Devices (TED) [3]. This chapter treats the theory and provides application guidelines required to model the electrostatic in-fluence of interface charge degradation caused by arbitrary charge profiles.
Chapter 4: Extraction of the electric field and interface charge
pro-files based on: ’Extraction of the electric field in field plate assisted RESURF devices’ published in 2012 as part of the 24th ISPSD proceedings, Bruges, Belgium [4], and ’Electric field and interface charge extraction in field-plate assisted RESURF devices’ published in 2015 in TED [5]. This chapter focuses on subthreshold impact ionization in gradient based FP assisted RESURF devices, how it can be used to extract lateral fields, their changes and the interface charge distributions causing them.
Chapter 5: Off-state leakage behavior in gradient based FP assisted
RESURF power devices based on: ’On the degradation of field-plate assisted RESURF power devices’ published in 2012 as part of the IEDM proceedings, San Francisco, CA, USA [6]. This chapter focuses on extracting and model-ing the leakage generation components, how they degrade and how they are affected by the temperature.
Chapter 6: Measurement results and their analysis based partly on:
’On the degradation of field-plate assisted RESURF power devices’ published in 2012 as part of the IEDM proceedings, San Francisco, CA, USA [6]. This chapter focuses on the obtained measurement results and their analysis using the developed methods described in previous chapters.
Chapter 7: This chapter provides a summary of the most important
ix
ABSTRACT
Ordering the above chapters chronologically ([1],[4],[6],[2],[3],[5]) shows a path typical in research of any kind, namely the quest to explain obtained (measurement) results and all the different tangential paths those can lead to. This work, by arranging the myriad of obtained insights in a coherent story line, provides a guide for those who are interested in:
Field-plate assisted RESURF power devices, their gradient based optimization, degradation and analysis.
S
AMENVATTING
Compacte fluorescente en licht-emitterende diode (LED) lampen hebben een steeds groter marktaandeel in de lichtindustrie. De snelle ontwik-kelingen met betrekking tot grootte, efficiëntie en betrouwbaarheid van deze lichtbronnen gaan hand in hand met de ontwikkelingen van de in-gebouwde sturingselektronica. Voor de lange levensduur van deze licht-bronnen is het daarom essentieel dat hun sturingselektronica minstens zo robuust is. Transistors specifiek ontworpen om hoge spanningen of stromen te kunnen weerstaan (zogenaamde vermogenstransistors) vormen een belangrijk deel van de verlichtingselektronica.
Dit doctoraalonderzoek focusseert zich op het ontwikkelen van op-timalisatiemethodes voor deze vermogenstransistors en bestudeert hoe langdurige elektrische stress de werking daarvan beïnvloedt. De (op gra-diënten gebaseerde) geoptimaliseerde transistorontwerpen resulteren in kleinere en daardoor goedkopere transistors met een bijna constant intern elektrisch veld (Reduced SURface Field, RESURF) en vele unieke eigen-schappen, nuttig voor het modelleren en voorspellen van het elektrisch gedrag. Echter, door elektrische stress kan er parasitaire lading op bepaalde locaties in de transistor opgebouwd worden die het interne elektrische veld beïnvloedt, wat vervolgens leidt tot een ander (en mogelijk destructief) transistorgedrag.
De belangrijkste mechanismen die degradatie onder verschillende stress-condities in de transistors teweegbrengen zijn geïdentificeerd, evenals de locatie waar de door stress veroorzaakte fysieke en chemische verande-ringen plaatsvinden. Met deze kennis zijn diagnostische technieken en analytische methoden ontwikkeld om voorspellingen van de transistor-werking na elektrische stress mogelijk te maken. Als zodanig levert dit onderzoekswerk de benodigde inzichten en gereedschappen voor het ont-werp en diepgaande elektrische karakterisatie van op gradiënten geba-seerde veld-plaat ondersteunde RESURF vermogenstransistors voor en na elektrische stress.
Overzicht
Elk hoofdstuk in dit werk is gebaseerd, en weidt uit, op gepubliceerd werk uitgevoerd tijdens mijn doctoraal onderzoek.
ondersteunde RESURF vermogenstransistors gebaseerd op: ’Design optimi-zation of field-plate assisted RESURF devices’ gepubliceerd in 2013 als deel van de 25ste ISPSD conferentie te Kanazawa, Japan [2]. Dit hoofdstuk presen-teert de benodigde ontwerpregels voor de optimalisatie van de elektrische velddistributie en het reduceren van de aanweerstand in verschillende typen op diëlektrica gebaseerde RESURF transistors.
Hoofdstuk 3: Veldveranderingen en degradatie veroorzaakt door
op-pervlaktelading in veld-plaat ondersteunde RESURF transistors gebaseerd op: ’Impact of interface charge on the electrostatics of field-plate assisted RESURF Devices’ gepubliceerd in 2014 in het wetenschappelijk tijdschrift TED [3]. Dit hoofdstuk gaat in op de benodigde richtlijnen voor het modelleren van oppervlakteladingsdegradatie veroorzaakt door arbitraire ladingsprofie-len.
Hoofdstuk 4: De extractie van het elektrisch veld en
oppervlaktela-dingsdistributie gebaseerd op: ’Extraction of the electric field in field plate assisted RESURF devices’ gepubliceerd in 2012 als deel van de 24ste ISPSD te Brugge, België [4]. En ’Electric field and interface charge extraction in field-plate assisted RESURF devices’ gepubliceerd in 2015 in het wetenschappelijk tijd-schrift TED [5]. Dit hoofdstuk bestudeert de botsingsionisatie beneden de drempelspanning in de op gradiënten gebaseerde veld-plaat ondersteunde RESURF transistors, hoe dit te gebruiken bij het extraheren van het lateraal elektrisch veld en hoe dit verandert aan de hand van oppervlaktelading.
Hoofdstuk 5: Het gedrag van de lekstroom in uitstand voor de op
gradiënten gebaseerde veld-plaat ondersteunde RESURF transistors ge-baseerd op: ’On the degradation of field-plate assisted RESURF power devices’ gepubliceerd in 2012 als deel van de IEDM conferentie te San Francisco, CA, Verenigde Staten [6]. Dit hoofdstuk presenteert de extractie en de modellering van verschillende contributies in de lekstroomgeneratie, hoe die degraderen en hoe zij worden beïnvloed door de temperatuur.
Hoofdstuk 6: Meetresultaten en de analyse daarvan gebaseerd op: ’On
the degradation of field-plate assisted RESURF power devices’ gepubliceerd in 2012 als deel van de IEDM conferentie te San Francisco, CA, Verenigde Staten [6]. Dit hoofdstuk presenteert de verkregen meetresultaten en de
xiii
SAMENV
A
TTING
daarbij behorende analyse aan de hand van de ontwikkelde methoden.
Hoofdstuk 7: Dit hoofdstuk presenteert de belangrijkste conclusies,
aanbevelingen en mogelijke vooruitzichten.
Als de hoofstukken chronologisch zouden worden geordend ([1],[4],[6], [2],[3],[5]) zien wij een typisch onderzoekspad, namelijk de zoektocht naar de oorzaak van verkregen (meet) resultaten en de vele tangentiële wegen waar dit toe leidt. In dit doctoraalonderzoek is door het organiseren van de vele verkregen inzichten in een coherent verhaal een algemeen leidraad ontwikkeld voor diegene die geïntresseerd zijn in:
Veld-plaat ondersteunde RESURF vermogenstransistors, de daarvoor op gradiënten gebaseerde optimalisatie, degradatie en analyse.
1 POWER SEMICONDUCTOR DEVICES · 1
1.1 Introduction · 2 1.2 Size and breakdown voltage · 2 1.3 Specific on-resistance · 5 1.4 The RESURF principle · 7 1.5 Degradation and reliability · 11 1.6 Methodology · 13 1.7 Conclusion · 14
2 DEVICE DESIGN OPTIMIZATION · 15
2.1 Introduction · 16 2.2 Gradient based FP assisted RESURF model · 16 2.3 Breakdown · 21 2.4 Field-plate potential · 29 2.5 Application guidelines and results · 32 2.6 Conclusion · 33
3 INTERFACECHARGE AND ELECTROSTATICS · 35
3.1 Introduction · 36 3.2 Interface charge - 1-D electrostatics · 38 3.3 Lateral decay characteristic · 38 3.4 Modeling the interface charge · 43 3.5 Conclusions · 50
4 SUBTHRESHOLD CURRENT AND EXTRACTION · 51
4.1 Introduction · 52 4.2 Subthreshold multiplication and field extraction · 54 4.3 Field extraction in RESURF devices · 57 4.4 Voltage range of validity · 64 4.5 Interface charge extraction · 65 4.6 Conclusions · 68
5 OFF-STATE CURRENT AND TEMPERATURE DEPENDENCE · 69
xv
CONTENTS
5.1 Introduction · 70 5.2 Off-state leakage current model · 70 5.3 Depletion expansion and carrier generation · 72 5.4 Off-state multiplication · 75 5.5 Virgin leakage current · 77 5.6 Band to band tunneling generation · 78 5.7 Interface charge carrier generation · 79 5.8 Degraded leakage current · 80 5.9 Conclusions · 83
6 MEASUREMENTS AND STRESS ANALYSIS · 85
6.1 Introduction · 86 6.2 Stress procedure · 87 6.3 Specific on-resistance and threshold voltage · 88 6.4 Off-state leakage degradation · 89 6.5 Off-state stress acceleration · 90 6.6 Stress evolution · 96 6.7 Modeling · 98 6.8 Conclusion · 99
7 SUMMARY& RECOMMENDATIONS ·101
7.1 Summary ·102 7.2 General Conclusion ·103 7.3 Original contributions ·104 7.4 Recommendations and Future work ·104
A THE PARABOLIC POTENTIAL APPROXIMATION ·113
A.1 Derivation - Single Sided device ·113 A.2 Dielectric asymmetry ·116 A.3 Solving Merchant’s equation - non-reachtrough case ·117 A.4 2-D distribution ·119
B IMPACT IONIZATION INTEGRAL ANDMULTIPLICATION ·121
C GRADEDMOSCAP DEPLETION ·123
D PARAMETERS ·125 BIBLIOGRAPHY ·129 LIST OF PUBLICATIONS ·135 Peer-reviewed ·135 Other ·135 ACKNOWLEDGMENTS ·137
CHAPTER
1
P
OWER
S
EMICONDUCTOR
D
EVICES
Abstract
An initial literature study combined with some basic comparisons has been performed on electric-field modulation (or electrostatic) tech-niques and the subsequent reliability issues of power semiconductor devices. An explanation of the most important power device met-rics such as the off-state breakdown voltage (BV) and the specific on-resistance RONA will be given, followed by a short overview of
some of the electrostatic techniques used to suppress peak electric fields. Furthermore it will be argued that depending on the operating conditions of these devices changes in electric field peaks and therefore avalanche behavior can occur. This results in (oxide) reliability issues unlike those of conventional field-effect transistors.
This Chapter was published as part of the SAFE at STW.ICT ’10 proceedings [1]. For clarity it has been expanded with additional figures and explanations.
conductors required some of these creative design trends ([8],[9]) long before their low power counterparts.
Power devices have to withstand high voltages imperative for many applications such as motor drives and power distribution systems. There-fore high breakdown voltage is a primary requirement for power devices (paragraph1.2). The field of power semiconductor devices encapsulates everything from the extremely high power (>10 MW) low switching speed thyristors (e.g. in high-voltage DC power transmission [10]), the mid-range (1 kW-1 MW) MOS- Bipolar devices (IGBTs [11]), to the ’low’ power (<1 kW) high switching speed double-diffused MOS (DMOS, [12]) transis-tors. In this work the focus will be on, silicon based, devices falling in the lower end of this spectrum.
An other figure of merit is the so-called on-resistance (RON) [13]. This
parameter is defined as the total resistance to current flow between the conducting terminals (i.e. source, drain) when the device is turned on (i.e. by the gate). The RON limits the maximum current-handling capability of
the power device:
P= ID· VDS = I2D· RON, (1.1) with ID the drain current, VDS the drain-source voltage and P the device
power dissipation. Hence to reduce power loss RONshould be minimized.
Since power dissipation per unit area has a limit (temperature) Eq. (1.1) is also expressed using:
P Aw = J
2
D· RONA, (1.2)
with Awthe active device area, JD the on-state drain current density, and
RONAthe so-called specific on-resistance, a key parameter used in the field
of power semiconductor devices (paragraph1.3).
1.2
Size and breakdown voltage
In the field of power semiconductors size reduction is also of great im-portance, although fundamental material properties combined with the high voltage, high current needs make this an inherently complicated task. When switching/blocking a given voltage (V) a device size reduction will lead to higher fields ( V/μm). At a certain critical field electrical breakdown will occur. This type of breakdown does not have to be physically destruc-tive but indicates the point at which the device will start to electrically
3 CHAPTER 1. POWER SEMICONDUCT OR DEVICES
Figure 1.1: Device cross section of a P+N(a) and PIN (b) diode with equal BVcharacteristics (750 V, dashed Fig.1.2) at a reverse bias of 500 V showing the simulated potential line and electric field distributions.
conduct, making it unable to switch/block the given voltage. Size reduc-tion is therefore inherently limited by the device’s electric field having to be lower than the material (semiconductor) critical field.
Figure1.1visualizes the size vs. breakdown voltage relation [14–16] of a silicon P+N and a PIN diode, the basic components used in most power devices. For the PIN diode the breakdown scales stronger with the drift length (Fig.1.2) since there is no space charge in the (intrinsic) drift region. In this intrinsic layer the potential can spread evenly across an increased length resulting in lower electric fields than at comparable P+N drift lengths. Therefore for the same device length the breakdown voltage (BV) of a PIN diode is higher than that of a P+N diode. This difference can be observed in their electric field distributions (E(x)) as illustrated in Fig. 1.1a and b. The difference in field distribution can be obtained by solving the 1-D Poisson equation with (left, P+N) and without (right, PIN) space charge density (ρ), as described below:
∂2ψ(x) ∂x2 = − ∂E(x) ∂x = − ρ εsi E(x) = ρ εsi x+ c ∂2ψ(x) ∂x2 = − ∂E(x) ∂x = 0 E(x) = c, (1.3)
where ψ is the potential and εsi is the permittivity of silicon.
distri-VOL
T
AGE Figure 1.2: The device or drift length vs breakdown voltage relation of a sil-icon PIN diode (using [14]) and that of the P+Ndiode (Fig.1.3, L = W max).
The dashed line indicates the intrinsic resp. N− region lengths of the devices depicted in Fig.1.1.
Figure 1.3: Analytically determined [13] breakdown voltage (left-axis) vs doping concentration (ND, N− Fig.1.1a) of an abrupt one-sided (Si) P+N
diode with the corresponding maximum depletion width (Wmax,
right-axis).
bution across the whole intrinsic layer (Fig. 1.1b) while that of the P+N diode is triangular in shape with a peak critical field (≈ 2 · 105 V/cm) at the P+Njunction (Fig. 1.1a). The slope of this field (Eq. (1.3)) is determined
5 CHAPTER 1. POWER SEMICONDUCT OR DEVICES
Figure 1.4: Schematic representation of device geometry as related to the specific on-resistance. The active device area Awis projected on the wafer,
while Acis the current cross-sectional area.
by the doping [13]. Figure 1.3shows that the maximum depletion layer width increases for lower (n-type) doping concentrations yielding higher breakdown voltages.
Therefore, for a given maximum voltage, a PIN diode can be made more compact than a P+Ndiode and an N+Pdiode, for that matter. This however comes with a crucial disadvantage. The lower, ultimately intrinsic (PIN), layer doping with its higher breakdown will cause the specific on-resistance to increase compared to the higher doped counterparts.
1.3
Specific on-resistance
As explained before, for determining the power consumption of electric circuits the on- resistance (RON) is a key figure of merit. A higher RON
results in increased power loss, resulting in systems that consume more energy (produce more heat, have shorter battery life etc.). The specific on- resistance (RONA) additionally takes into account device dimensions
and orientation (Fig.1.4), a physical characteristic. The latter is the world standard as it indirectly includes the cost of (on wafer) implementation. The specific on-resistance is defined as:
RONA = ρ· L Ac · A
w, (1.4)
with Ac is the current flow cross section, Aw is the active device area or
wafer footprint, L is the drift length and ρ the resistivity, see Fig.1.4: ρ= 1
ANCE
LDMOS biased in on-state (VGS=Vth, VDS=VDD). The contact resistances
(RCS and RCD), n+ resistance (Rn+), the channel resistance (RCh), the JFET
resistance (RJFET) and drift resistance (Rdrain) are indicated.
with q the elementary charge, μ mobility and N the doping (ND or NA)
concentration. Examining Fig.1.4, and then employing Eq. (1.4) and (1.5), RONA for both the lateral (left) and vertical (right) case can be obtained:
Ac = W × t, Aw = W × L RONA= L2 qμNt Ac = Aw = W × t RONA= L qμN (1.6)
As shown in Fig. 1.4for a given design a vertical device orientation makes better use of the available semiconductor (volume) for the same wafer area [9] and therefore provides the lowest RONA. The small wafer
footprint combined with large drift length required in power MOSFETs has caused a large part of power device components, in particular discrete, to be vertically designed. However vertical power devices, such as the vertical double-diffused MOSFET (VDMOS), are inherently difficult to integrate with CMOS and generally suffer from worse quasi-saturation behavior [17] than their lateral (LDMOS) counterparts. As such planar RESURF devices have found widespread commercial success in a variety of fields such as integrated high-side circuitry [18,19] and as driver transistors in high end analog applications [20].
A universally accepted set of specified bias conditions, what devices to use and how exactly to measure the on-resistance is lacking. However when measuring the resistance of a device that is turned on (RON), e.g.
by the gate, the doped drain (drift) extension of a device is usually only a part of the total resistance. Figure 1.5 gives an illustration of typical contributing resistances, such as contact resistance (RC), channel resistance
(RCh), junction FET resistance (RJFET) and drift resistance (Rdrain), in an
(on-state) LDMOS [13]. The percentage of contribution to the total device resistance is strongly dependent on the breakdown voltage (∝ drift length) and on how the device has been optimized. The focus of this work will only be on the understanding and optimization of the drift length or doped
7 CHAPTER 1. POWER SEMICONDUCT OR DEVICES
Figure 1.6: Two-dimensional simulations and analytical results of the I-V curves (or on-resistance) for the three different drift region types. Note that the results depicted are for unipolar devices which use drift region doping distributions identical to the diode types treated.
drain extension (Rdrain) contribution. This is because it is by far the largest
contribution in the device breakdown voltage range (250-1 kV) this work focuses on.
Figure1.6shows the drift region current density vs. voltage characteris-tic of various unipolar devices with the same drift region. The slope gives the on-resistance obtained from 2-D numerical simulations and analytical models in which the active area has not been taken into account. For a higher doping (N) concentration the RON reduces (Eq. (1.6)) at the price
of a lower breakdown voltage BV (Fig. 1.3). This RONA-BV trade-off is
often referred to as the 1-D silicon limit. In Fig. 1.7the RONA is plotted
against BV for various power device technologies, close to this limit. This relation is not linear as for instance increased doping reduces the carrier mean free path resulting in a mobility (μ) decrease [13,21] affecting RON
and breakdown (impact ionization rate) in different ways. A more detailed theoretical limit analysis (of novel high-voltage topologies) can be found in [22].
1.4
The RESURF principle
To break the 1-D silicon limit Appels and Vaes proposed the RESURF principle of a lateral power diode in 1979 [26–28], although originally the so-called superjunction structure comes from a different field: the varactor with a highly dense capacitance, introduced by S. Shirota and S. Kaneda
Figure 1.7: The 1D silicon limit plotted with experimental RON-BV results
for various power device technologies [23–25].
in 1978 [29]. Ten years later in 1988 the superjunction power device was invented by D. Coe [30], with the first experimental superjunction devices being reported in 1998 by G. Deboy et al. [25]. The device created was a VDMOS containing vertical superjunctions and was named "CoolMOS". The theory of these superjunctions is well described in [31]. The idea behind this RESURF or superjunction concept is to have a relatively highly doped drift region (Low RON) while maintaining the high BVs [32] associated
with a constant electric field distribution along the current flow direction. The RESURF principle which stands for REduced SURface Field is based on reducing the peak electric field through a 2-D or 3-D depletion effect (Fig. 1.8a) using additional charge. The diode formed consists of two parts: a lateral diode with a vertical P+/N− (and N+/P−) junction with a possible lateral breakdown and a vertical diode with a horizontal N−/P− junction and possible vertical breakdown. The optimal (epitaxial) doping vs. layer thickness (Nepi· tepi) was shown to be≈ 1 · 1012cm−2
[27],[31]. This results in the lateral depletion layer being influenced by the vertical N−/P− junction in such a way that the (lateral) surface electric field is spread along the drift extension and the peak (horizontal) fields are suppressed. This then leads to a higher breakdown condition, occurring not at the surface, but vertically in the semiconductor body.
Merchant et al. [33] expanded the RESURF principle for implementa-tion in SOI devices (Fig.1.8b). The authors solved the 2D-Poisson equation:
∂2ψ(x, y) ∂x2 + ∂2ψ(x, y) ∂y2 = − ρ(x, y) εsi , (1.7)
9 CHAPTER 1. POWER SEMICONDUCT OR DEVICES
Figure 1.8: Schematic cross section of a junction RESURF (a) and graded doped FP assisted SOI based RESURF (b) diode. Handler wafer (HW) acts as field-plate (FP). Shown fields at a reverse bias of 500 V with BV 750 V.
by forcing the 1-D contradictory requirements of having low RON(ρ = 0),
and also a constant lateral field (∂2ψ∂x(x,y)2 = −
∂E(x,y)
∂x = 0) as a central
boundary condition (AppendixA). This resulted in the necessity of a lateral linear grading in doping [33] according to:
N(x) = (si/q)(BV/L) tsi(tsi2 + si
oxtox)
x, (1.8)
with BV/L the desired uniform electric field at breakdown, tsi the silicon
thickness and tox the oxide thickness. The required doping gradients
are achieved through ion implantation and diffusion through specifically spaced mask openings as explained in [34] and [35]. It should be mentioned that the superior field distribution and low RON made possible by this type
of RESURF is by no means exclusive to planar devices and has also been proposed in vertical (trench) MOSFETs [36,37]. Using the methodologies presented by S. Merchant et al. this work will generalize and expand gradient based FP assisted RESURF device optimization (chapter2).
Figure 1.9: Electric field evolution for (a) P+/N− and (b) Junction RESURF normalized to that of a (c) Gradient based FP assisted RESURF extension. Dashed lines clarify size and field difference compared to the optimal distribution of (c).
11 CHAPTER 1. POWER SEMICONDUCT OR DEVICES
A normalized overview of the field distribution and expansion during reverse bias operation for different diodes with equal BV (750 V) drain ex-tensions is shown in Fig.1.9. The differences in drift extension length, due to the non-optimal field distributions, are highlighted by the dashed lines. It is clear that the field in gradient based FP assisted RESURF extensions expands in a unique way: the field peak does not change for a bias change, rather only the depletion width (Fig.1.9c). This distinct field ’clamping’ [4] and expansion behavior provides unique advantages and is the basis of many of the models and analysis techniques developed in this work.
1.5
Degradation and reliability
After (prolonged) use device behavior can slowly start to change or even undergo abrupt catastrophic failure. Understanding, predicting and antici-pating this type of unwanted behavior is therefore of great importance for the design of reliable electrical (power) systems. Robust design is especially important for critical applications operating in harsh environments such as those for automotive applications, in which the (power) transistor plays an increasingly important role.
In analog applications, where these devices are used as driver transis-tors [20], [38], the presence of high voltages on the drain terminal serves as a source of degradation. When using DMOS devices for switching appli-cations, the devices generally operate in either the on (high VGS, low VDS)
or the off (low VGS, high VDS) state. Extended periods in any of these two
static DC states can induce some degradation. During the transient states however, when both higher than off-state currents and high VDS(<BV) can
occur (i.e. the DC semi on-state), the device is typically most vulnerable. As it was still lacking, understanding the root cause of DC off-state and semi on-state degradation in gradient based FP assisted RESURF devices is the main focus of this study. This according to the general philosophy that, without first understanding DC device behavior, understanding transient behavior and its many changing parameters is impossible.
The study of device degradation shows that three effects can be relevant: 1) injection, trapping/release of hot electrons in the oxide [39],
2) injection, trapping/release of hot holes in the oxide [40], 3) interface state creation [41].
In CMOS these Hot-Carrier Injection (HCI) effects can be distinguished by capacitance-voltage (C-V) measurements or a combination of current-voltage (I-V) measurements and charge pumping. In high current-voltage (LD)MOS devices, the more complex potential distributions due to the advanced drain extensions (e.g. using field plates, thick field oxides, doping gra-dients etc) complicate the separation and distinction of these individual mechanisms. However, one can separate the general spots of electric field
AND
RELIABILITY
suppression through double-sided symmetric RESURF [18,23] allowing higher drift region doping thus lowering RONfurther. Possible high (lateral)
electric field spots are indicated (circles, arrows).
peaks as highlighted in Fig.1.10. In combination with large current flows these areas form locations of impact ionization in which the generated hot carriers can more easily interact with the silicon - silicon dioxide interface. Analyzing [4], expanding [5] and developing [3] methods to locate field peaks and consequently the responsible HCI charge, is an integral part of this work.
It should be clear by now that the electric field distribution in high-voltage (HV)-devices is different from that of their low power CMOS counterparts. Moreover, the high current densities associated with the relatively lowly doped (ND) drift regions in these HV devices result in
large amounts of additional charge (related to mobile carriers n and p) in on-state operation. This charge alters the space charge distribution according to:
ρ(x, y) = q(N+D(x, y) − n(x, y) + p(x, y)), (1.9)
which in turn causes shifts in the electric field distribution. Commonly referred to as the base push out or Kirk effect [42],[43] this effect causes a destructive snapback phenomenon [44], limits the voltage handling capa-bilities (or Safe-Operating-Area, SOA) of RESURF devices [45] and makes finding both the physical and electrical HCI points of interests yet more complicated [46]. Furthermore accelerated lifetime tests of HV-devices of-ten result in self-heating effects which are otherwise not present in normal device operation [47]. This should therefore also be taken into account when studying HCI and complicates the extraction of good device life time predictions [48]. A failure analysis of thermal behavior in these types of devices can be found in [49].
Throughout the years a multitude of device design strategies (e.g. mov-ing current paths away from high electric field regions) have been proposed to mitigate the degradation effects in HV-devices [28]. But the lack of pure
13 CHAPTER 1. POWER SEMICONDUCT OR DEVICES
reliability research based on understanding HV degradation phenomena, specifically for charge gradient optimized devices, has made this mostly a practice of trial and error with room for improvement. Through a combined characterization, modeling and simulation strategy this work presents a first step towards this deeper understanding.
1.6
Methodology
Electrical measurements, Technology Computer-Aided Design (TCAD) simulations and (analytical) modeling are the main pillars of semiconductor device research. Each has its own strengths and weaknesses that usually require combined use to provide a complete understanding of device behavior. The extent to which these tools are used is usually dependent on the task to be performed. Obtaining a better understanding of a single existing device for instance requires a different approach (measurement and TCAD) than that of predicting behavior across large design ranges or multiple interconnected devices (compact modeling). General constraints such as, available (computing) time, simulation tools and equipment can also play an important role.
A large time (and monetary) investment is required to create (on wafer or packaged) test structures and measurement setups. Measurements generally provide I-V characteristics alone while the device itself remains a ’black box’ without (easy or non-destructive) ways to look into it. When for instance measurements show a type of behavior not understood one might choose to study the physics behind it by employing TCAD device simulations. These simulation tools [50] are based on node by node (finite element) calculations of interacting physical models. As such they provide a computer based numerical framework/environment to develop devices and study their operation while also providing the ability to look ’into’ the device. Depending on the complexity of the models and the density of nodes (the mesh) TCAD simulation can be highly time consuming.
A key feature of these tools is the ability to enable and disable different physical models. This is an often used method to determine what phe-nomena affect certain observed device behavior. Using this approach the key physical models can be identified, which can then be used to create general (physics based) analytical models. The initial time investment for the development of these types of models is generally very high but once implemented, are usually (computationally) fast and provide capabilities to optimize device design and predict their behavior across wide design and operating ranges.
The methodology of observation through electrical measurements, TCAD modeling to identify key phenomena and subsequent analytical modeling as described above, is the general research methodology followed throughout this work.
were briefly addressed. And finally the general (measurement, TCAD, modeling) research methodology adopted in this work was discussed.
CHAPTER
2
D
EVICE DESIGN OPTIMIZATION
Abstract
A mathematical model for optimizing the 2-D potential distribu-tion in the drift region of field-plate (FP) assisted REduced SURface Field (RESURF) devices (Fig.2.1) at reverse breakdown condition is presented. The proposed model generalizes earlier work [33,37] by in-cluding top-bottom dielectric asymmetry (typical in SOI devices [51]), non-zero field plate potentials (VFP) and grading of design parameters
other than drift region doping. This generally-applicable, TCAD veri-fied [50], model provides a guideline for gradient based optimization of the drain extension in a wide range of FP assisted RESURF devices.
The core of this chapter was published as part of the Kanazawa Japan ISPSD’13 proceedings [2]. It has been expanded with respect to its original publication by including a variety of additional figures and clarifications.
This chapter focuses on FP assisted RESURF only. This type of RESURF can be realized in both SOI [52] and trench-MOS [54] technology by tailor-ing one or a combination of the design parameters shown in Fig.2.1: (a) drift region doping, ND [34,37]
(b) dielectric layer permittivity, εd[55]
(c) dielectric layer thickness, td[56,57]
(d) semiconductor layer thickness, ts
(e) FP-potential, VFP[58,59]
A mathematical model will be presented that allows RONA-BV optimization
for all above mentioned FP assisted RESURF devices. Based on this, a generalized expansion that includes super junction based RESURF and the importance of curved contact electrodes is presented in [60].
The chapter is outlined as follows: paragraph2.2presents the gradient based FP assisted RESURF optimization model, paragraph2.3treats device breakdown and how to determine it, paragraph 2.4presents the use of constant field-plate potentials to optimize device design, paragraph2.5 focuses on application guidelines and the attainable RONA-BV trade-off,
while in paragraph2.6conclusions are drawn.
2.2
Gradient based FP assisted RESURF model
The model proposed in this chapter generalizes the work by S. Merchant [37], while achieving deeper physical insight into the RONA-BV trade-off
optimization of gradient based FP assisted RESURF devices. For this pur-pose, a more general model is presented describing the optimal RESURF electric fields and potential distributions, at reverse breakdown condition, in drain extensions using any substrate/dielectric combination (Fig.2.1) or 2-D symmetry (Fig.2.2).
2.2.1
Constant lateral field condition
The general description of the field distribution inside the depleted drain extension is given by the 2-D Poisson equation (assuming only a lateral vari-ation in drift doping ND(x) and constant semiconductor permittivity εs):
17 CHAPTER 2. DEVICE DESIGN OPTIMIZA TION
Figure 2.1: Breakdown voltage (BV) optimization methods for FP assisted RESURF devices. Optimal structures shown for: a) graded ND; b) graded
εd; c) graded td; d) graded ts; e) graded VFP. Methods shown are also
applicable to vertical trench-MOS type devices.
∂Ex(x, y) ∂x + ∂Ey(x, y) ∂y = qND(x) εs (2.1) Since optimal RESURF design requires a constant horizontal field ( Ex = −BVL ,
with L the drift length) it holds that at breakdown: ∂Ex(x, y)
∂x = 0. (2.2)
The constant lateral field Ex necessarily requires the lateral potential to
be a linear function of x (ψx = u(x) = BVL x). Using this, Eq. (2.1) can be
solved for the 2-D potential distribution (ψ) giving: ψ(x, y) = BV L x+ ψy(x, y), (2.3) with ψy(x, y) = − qND(x) 2εs y2 + c, (2.4)
obtained by accounting for Eq. (2.2) and integrating Eq. (2.1) twice. Using boundary condition Ey(x, 0) = 0 the integration constant c is zero. Thus
the general expression for an optimal (2-D) potential distribution (at break-down) in the depleted drift extension is:
ψ(x, y) = BV L x−
qND(x)
2εs
FP
ASSISTED
RESURF
MODEL
Figure 2.2: Cut along the y-direction of cross sections shown in Fig.2.1 for SS, ASYM and SYM devices and their equivalent structure. Top and bottom FP potentials are equal, dark gray regions represent the dielectric and white/light gray region represent the semiconductor.
Using this parabolic potential approximation different drain exten-sion vertical designs (single-sided SS, double-sided ASYM, and SYM) can be modeled as a single symmetrical field-plate/semiconductor structure (’EQV’, Fig. 2.2), with teq the equivalent thickness and VFP the vertical
potential boundary (dashed line, Fig.2.3). Imposing the equivalent (verti-cal) boundary condition to the (laterally) optimal semiconductor potential equation (Eq. (2.5), ψ(x, teq(x)) = VFP(x)) yields the design equation for
creating devices under the constant lateral field ( Ex = −BVL ) condition:
VFP(x) = BV L x− qND(x) 2εs t2eq(x) ⇔ εs BV L x− VFP(x) qND(x) t2 eq(x) 2 = 1. (2.6)
2.2.2
Vertical design, equivalent thickness t
eqand λ
Figure2.3shows that for any vertical design teqis the equivalent
semicon-ductor depletion thickness necessary for a parabolic drop from the peak potential (u) to the vertical potential boundary (VFP). A relation for this
equivalent thickness to the semiconductor and oxide thicknesses is essen-tial for a generalized set of optimal RESURF design rules (Section2.2.3). From the known vertical potential drop (ψy) and the (parabolic)
19 CHAPTER 2. DEVICE DESIGN OPTIMIZA TION
Figure 2.3: Vertical parabolic potential distribution ψ(y) for SS, ASYM and SYM devices (solid). Also shown the distribution for the equivalent (’EQV’, Fig.2.2) structure (dashed).
semiconductor (ψs) and dielectric (ψd) potential drop are (Fig.2.3a):
ψs = − qND 2εs t2s, ψd = Qs cd = −qND ts td εd , (2.7)
with Qs is the silicon (depletion) charge per unit area and cd the areal
dielectric capacitance. The total vertical potential drop is therefore: ψy = u − VFP = ψs+ ψd = −qNDts ts 2εs + td εd . (2.8)
Using the parabolic description of Eq. (2.4) the equivalent thickness ( teq)
for this potential drop in a SS device is: qND 2εs t2eq = qNDts ts 2εs + td εd , teq= 2· ts ts 2 + εs εd td . (2.9)
This is related to the parabolic approximation based λ-parameter ([37], Eq. (A.15)) using:
λ= ts ts 2 + εs εd td , teq = √ 2λ, (2.10)
whereby the separate parameters can be dependent on lateral location x (Fig.2.1). Using Eq. (2.8) and (2.10) we obtain (see also appendixA):
u− VFP
λ2 =
qND
εs
BASED FP ASSISTED RESURF MODEL λ= ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎩ ts1,2 2 + ε d1,2td1,2 ⇒ ASYM (b) ts 2 ts 4 + εs εdtd ⇒ SYM (c) (2.12)
Laterally along the device extension the vertical point of potential sym-metry (u, Fig.2.3) forms the potential line of symmetry (path 1, Fig.2.4). For an SS and SYM device this is y= ts resp. t2s from the dielectric
inter-face (Fig.2.3, Fig.2.4a,c). For the fully depleted ASYM case this location depends on the asymmetry in dielectric properties and thicknesses. Since the potential drop (Eq. (2.8)) is equal from this location to the respective vertical potential boundaries (Fig.2.3b) and it holds that ts1+ ts2 = ts, the
ASYM vertical point of potential symmetry can be obtained using:
ts1,2 = ts 2 (ts+ 2 εs d2,1td2,1) ts+ εs d1td1+ εs d2td2 . (2.13)
The derivation for the above equation is given in appendixA.2
2.2.3
Lateral design rule equations
Rewriting Eq. (2.6) in terms of λ (Eq. (2.10)) leads to Eq. (2.14). This de-scribes how the different design parameters should be tailored as a function of x (Fig.2.1) in order to achieve optimal RESURF, i.e. a constant lateral field at breakdown, by means of graded (Eq. (2.14)):
(a) doping RESURF, ND(x)
(b) ’ λ-RESURF’, λ2(x)
(c) FP-potential RESURF, VFP(x)
Whereby the grading of λ can be achieved through grading of the dielectric constant (Eq. (2.14)i), dielectric layer thickness (Eq. (2.14)ii) or semiconduc-tor layer thickness (Eq. (2.14)iii).
21 CHAPTER 2. DEVICE DESIGN OPTIMIZA TION εsBVL x− VFP qNDλ2 = 1 ⇒ ⎧ ⎪ ⎪ ⎨ ⎪ ⎪ ⎩ ND(x) = qλεs2 BV L x− VFP (a) λ2(x) = εs qND BV L x− VFP (b) VFP(x) = BVL x− qNεsDλ2 (c) ⇒ ⎧ ⎪ ⎪ ⎪ ⎪ ⎨ ⎪ ⎪ ⎪ ⎪ ⎩ εd(x)= 2qεsNDtdts 2εs(BVL x−VFP)−qNDt2s (i) td(x) = −t2εsεsd + εd(BVL x−VFP) qNDts (ii) ts(x) = εεstd d + εstd εd 2 + 2εs qND BV L x− VFP (iii) (2.14)
Optimal RESURF can also be obtained using a block type combination of graded profiles as long as Eq. (2.14) is fulfilled. Although the graded profiles from Eq. (2.14) are not exact solutions of the Poisson equation, good agreement between the model and TCAD simulations is achieved. Though the general approach does not change it should be noted that for the semiconductor thickness ( ts) and the dielectric permittivity ( εd)
equations the initial assumptions made in Eq. (2.1) have to be changed to include non-constant boundary conditions. To fully optimize the potential distribution uniquely shaped terminal connections, as discussed in [60], might also be necessary.
Equations (2.12) - (2.14) provide a guideline for RESURF optimization across a wide range of drain extensions types. However, they will only lead to optimal RESURF if the device breakdown voltage is limited by a constant lateral field Ex (Fig.2.5), as discussed in following section.
2.3
Breakdown
Breakdown in 2-D structures can occur in three possible ways: lateral ( Ex) breakdown, vertical (Ey) breakdown and P-body/N–drain junction
breakdown. The breakdown voltage BV of the device is determined by the lowest of each of the three contributions. Each of these breakdown possibilities will be treated separately in the subsequent sections.
Breakdown is analyzed as follows, first Eq. (2.15) is solved for u(x) (= ψ(x, 0)), to obtain the potential distribution along the symmetry line y = 0 (Path 1, Fig.2.4) using Eq. (2.11).
∂2u(x) ∂x2 − u(x) − VFP(x) λ2(x) = − qND(x) εs (2.15)
Figure 2.4: a) Highest electron impact ionization (highest e−− II) paths [6] for BV modeling in the three vertical configurations SS, ASYM and SYM.
Subsequently the field distributions important for impact ionization (II) [6] are obtained using (appendixA.4):
Ex(x, 0) = −u(x)
Ey(x, y) =
u(x) − VFP(x)
λ2(x) y.
(2.16)
And finally the impact ionization (II) integrals (IIint) along these main
horizontal and vertical ionization paths [6] (Fig.2.4) are calculated using:
IIxint = Path1 An · exp −Bn Ex(x, 0) dx (2.17) and IIyint = Path2 An· exp −Bn Ey(W(VDS), y) dy. (2.18)
For a more in depth treatment of the IIint and its relation to carrier
multi-plication and breakdown (runaway multimulti-plication) see chapter4.
2.3.1
Lateral ( E
x) breakdown
Lateral breakdown occurs when IIxint (Eq. (2.17)) along the symmetry
line of the depleted drift region (path 1, Fig. 2.4) reaches unity. This is when impact ionization results in runaway carrier multiplication (M =
1
1−IIint, appendixB) causing electrical failure. For optimal (VDS = BVmax)
23 CHAPTER 2. DEVICE DESIGN OPTIMIZA TION
at y= 0 (Fig.2.5a). Solving IIx
int = 1 for any drift region length (L) under
this constant lateral field condition gives: 1= L 0 An· exp −Bn Excrit dx 1= AnL· exp −BnL BVmax ln 1 AnL = −BnL BVmax BVmax(L) = BnL ln(AnL) Excrit(L) = Bn ln(AnL) . (2.19)
This is the maximum BV vs. RESURF drift length (L) equation ([33]) and equal to that of the breakdown condition of the PIN diode (chapter 1.2, [21]). When using the correct (silicon) coefficients (An = 7.03 · 105cm−1,
Bn = 1.47 · 105Vcm−1[52]) Eq. (2.19) can be used to calculate the material
gradients necessary (Eq. (2.14)) for constant critical lateral field distribu-tions at breakdown. Figure 2.5 shows modeled (Eq. 2.16, solved in ap-pendix.A.3) and TCAD simulated lateral fields. This is done at y= 0 using optimal (with slope a) and two non-optimal (with reduced slope 0.8a and increased slope 1.2a) graded doping profiles as described by Eq. (2.14)a.
In Fig. 2.5a it is seen that the device has a drift length (L) of 25 μm with an optimal breakdown of 490 V as obtained by Eq. (2.19). For the non-optimal reduced grading case of Fig.2.5b the lateral field is below the critical value. This results in a field that expands faster with increasing potential causing a reachthrough, i.e. the lateral field reaches the drain contact, peak field that limits breakdown. For the non-optimal increased grading case depicted in Fig.2.5c the above critical field value obtained causes premature breakdown (IIx
int=1 for path1 < L).
Using Eq. (2.17) each of the field distributions shown in Fig.2.5can be rep-resented as a single IIx
int value. Figure2.6compares the model and TCAD
obtained field distributions using IIx
int for: (a) Doping (ND(x), Eq. (2.14)a),
FP-potential (VFP(x), Eq. (2.14)c) and (b) dielectric ( td(x), Eq. (2.14)ii) graded
devices. Good agreement between model and TCAD (chapter1.6) has been obtained across the full VDSrange and across multiple (optimal and
non-optimal) gradient values. For an even better fit see the discussion on the use of the parabolic assumption based λ as the decay characteristic in Chapter3. Finally, non-optimal design of the lateral electrode boundaries (Anode/Source, Cathode/Drain) introduces Ex non-idealities that limit
optimal lateral breakdown. Although not a big issue for the breakdown voltage ranges discussed here (>150 V), an in-depth discussion on electrode design is given in [60].
Figure 2.5: TCAD and modeled Ex at y = 0 for different VDS. Shown is
graded-NDRESURF in three different cases: a) optimal slope, b) reduced
25 CHAPTER 2. DEVICE DESIGN OPTIMIZA TION
Figure 2.6: a) TCAD and modeled Ex-ionization integrals (IIxint) for SYM
graded-NDand graded-VFPRESURF in three different grading cases b) As
in (a) but for graded- td. For all simulations a Si/SiO2 structure is assumed
with a fixed εs/ εd ratio of 3.
2.3.2
Vertical (E
y) breakdown
Vertical breakdown occurs when IIyint (Eq. (2.18)) along a vertical ioniza-tion path reaches unity. The largest vertical ionizaioniza-tion path is found along the longest path at the edge of the depletion region (path 2, Fig.2.4), where Ey is maximum (Fig.A.2). Figure2.7shows the calculated IIyint at the edge
of the depletion region (x = W(VDS)) of an L = 40 μm and ts = 1 μm
de-vice with three different vertical configurations of the dielectrics (Fig.2.4). A clear reduction in breakdown is seen for increasing ionization paths. As such the SS configuration with its longest vertical ionization path ( ts,
Figure 2.7: Ey-II integrals calculated for SYM ( td=3 μm), ASYM ( td1=6 μm,
td2=3 μm) and SS ( td=3 μm) devices showing vertical breakdown decrease
as the y-path length (Path 2, Fig. 2.4) increases. Inset: corresponding simulated off-state I-V in the three cases.
Fig.2.4) has the lowest breakdown voltage followed by the ASYM and sub-sequently the SYM configuration. For an ASYM device the longest amongst ts1 and ts2 (Eq. (2.13)) is the breakdown limiting path of importance.
The vertical designs used in Fig. 2.7 don’t reach the optimal lateral breakdown (BVmax(40 μm) = 740 V, Eq. (2.19)), even for the shortest vertical
ionization path (SS = 12ts = 0.5 μm). This, because a critical Ey field is
reached before lateral breakdown could occur. Solving IIyint = 1 the critical vertical peak field can be obtained for any given path length as shown in Fig.2.8a. Contrary to Eq. (2.19) this is performed numerically as Ey is a
function of y (Eq. (2.16)) andexp(y1)dy (Eq. (2.18)) does not have a closed form solution. Figure2.8a shows that for a 0.5 μm vertical path length, like for the (SYM) devices shown in Fig.2.8b, Eycrit is 65 V/μm.
Figure2.8b shows the increase of the peak Ey field, located along the
semiconductor/dielectric interface (Ey(x,12 ts), Eq. (2.16), Fig. A.2). For 3
different oxide thicknesses these peak values are shown along the lateral direction x of the extension. When reducing the oxide thickness a larger part of the vertical voltage is dropped in the semiconductor resulting in a sharper increase in Ey at the interface. As such a critical Ey field is reached
earlier (lower BV) for the thinner oxide devices, i.e. those having a smaller λ(Eq. (2.16)). For an optimized design, Eycrit should not be reached before
Excrit. An overview of the Excrit vs. Eycritlimited breakdown interaction, for
the SYM ts = 1 μm device is shown in Fig.2.8c. The theoretical minimum
27 CHAPTER 2. DEVICE DESIGN OPTIMIZA TION
Figure 2.8: a) Numerically obtained Eycrit for different vertical ionization
path lengths. b) Simulated ts = 1 μm SYM device (y-path = 0.5 μm)
show-ing lateral increase of Ey-fields at Ey(x,12 ts) for different dielectric
thick-nesses. Vertical breakdown locations are indicated in the same figure. c) BV vs. drift length L for graded-ND RESURF, showing the limitations on the
choice of td imposed by Ey-breakdown. The inset shows a comparison
extension location x > 34 μm.
Finally, when the vertical path is sufficiently short (e.g. 0.25 μm in Fig.A.2) the critical field values (Eycrit = 85 V/μm, Fig. 2.8a) can exceed
fields at which Band to Band (B2B) tunneling starts playing a significant role (EB2B > 70 V/μm in silicon) [61,62]. Tunneling is not an impact
ioniza-tion current, rather a generaioniza-tion current that rises steeply with increasing fields (beyond EB2B). Devices that have (vertical) fields that exceed EB2B
while still being below Eycritcan therefore have ’runaway’ tunneling
gen-eration, that limit breakdown (Fig. 5.7). As is clear from Fig. 2.8a this scenario (Eycrit>Ey>EB2B) is primarily an issue for ultrathin SOI (or
ultra-scaled trench) high-voltage devices. Chapter5[6] will further discuss this generation component and its unique (minimal) temperature dependence related to off-state leakage generation.
2.3.3
Junction breakdown
Having a high initial doping N0 (ND(x=0)) at the source/anode junction
might lead to junction field peaks not suppressed by the vertical depletion side of the 2-D RESURF effect (Fig.2.9a). In 1979 when Appels and Vaes first described the occurrence of REduced SURface Fields by means of a 2-D depletion effect [26] the maximum junction dose rule was postulated:
tmax · ND(0) = 1 · 1012. (2.20)
This describes the relation between the initial doping (ND(0)) and
max-imum silicon layer thickness (tmax) that can be (2-D) depleted (in a SS
device) without premature breakdown from the (1-D) junction fields. The vertical semiconductor thickness to be depleted for SYM and ASYM de-vices are as described previously in Fig. 2.3. Figure 2.9a shows TCAD obtained lateral field distribution of a SYM L = 40 μm and ts = 0.5 μm
dielectric graded RESURF device (Eq. (2.14)ii). The results show junction breakdown limiting the ideal device breakdown (BVmax = 740 V) when
ND(0) exceeds the 4· 1016cm−3maximum obtained for tmax = 0.25 μm in
Eq. (2.20). Figure2.9b gives an overview of TCAD obtained breakdown val-ues for two SYM device semiconductor layer thicknesses (0.5 μm, 0.2 μm). Breakdown is clearly shown to be junction limited at those doping lev-els exceeding 4· 1016cm−3 resp. 1· 1017cm−3 (dashed) as stated by the maximum junction dose rule of Eq. (2.20).
29 CHAPTER 2. DEVICE DESIGN OPTIMIZA TION
Figure 2.9: a) Junction breakdown in a SYM td-graded RESURF device.
Doping concentration ND increase leads to higher junction Ex-fields
limit-ing breakdown. b) BV vs. ND for different thicknesses ts showing onset of
junction breakdown shifted towards higher NDwhen reducing ts (see also
inset).
2.4
Field-plate potential
Obtaining a constant Ex is not always possible with grounded field-plates
(VFP=0 V), because Eq. (2.14) predicts unrealistic (i.e. negative) values
for device parameters at x=0. Equation (2.21) shows how to get rid off these unrealistic terms by tailoring the VFP-value [63] for the different
POTENTIAL
Figure 2.10: a) Simulated Ex-fields at breakdown for graded-NDRESURF
with and without VFP compensation. b) Simulated and modeled BV vs.
VFP for different values of the initial doping ND(0).
VFPcomp = ⎧ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎨ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎩ −qND(0)ts εs ts 2 + εs εdtd ND(x) −qNDts εs td(0) + t2εsεd s td(x) −qNDts εs ts 2 + εs εd(0)td εd(x) −qNDts(0) 2εs ts(0) − 2εεs dtd ts(x) (2.21)
31 CHAPTER 2. DEVICE DESIGN OPTIMIZA TION
Figure 2.11: Simulated and modeled BV vs. ND(0) with and without VFP
-compensation for different values of ts. Breakdown for VFPcompensation
is limited to junction breakdown similar to Fig.2.9b. The VFP values used
are obtained from Eq. (2.21) - ND(x).
From a design perspective field-plate compensation can be of particular interest in the case of graded ND and td as it allows for compensation
of technological design limitations. For instance, if an (increased) initial doping ND(0) is needed or a minimum td(0) this can be accounted for in
the ND(x) resp. td(x) cases (Fig.2.1a,c) using an appropriate VFP.
Figure2.10a shows TCAD obtained lateral fields of a graded-ND(x) device
with high and low initial doping, with and without VFP compensation. For
a sufficiently low initial doping (high RON, chap.1.3) no field-plate
compen-sation is needed for optimal lateral breakdown. When the initial doping is increased (lower RON) however, this has to be compensated according to
Eq. (2.21).
Figure2.10b visualizes the gradual increase in breakdown across a range of negative field plate potentials and different initial doping values. The optimal breakdown plateau is at the voltages described by Eq. (2.21). When compensating the initial doping in doping graded devices it is important to note that the junction breakdown limit, as described by Eq.(2.20)), will still hold. In Fig.2.11the same vertical device symmetries (tmax) as Fig.2.9b
are used and show similar junction limited breakdown for the VFP
compen-sated curves. Finally, smart usage of field-plate potentials can be beneficial not only for off-state breakdown optimization as discussed here, but also for active RONreduction as discussed in [64]. Understandably, non-optimal
field-plate potentials can reduce both on and off-state breakdown, this parasitic effect is discussed in [65].
GUIDELINES
AND
RESUL
TS
Figure 2.12: Comparison of theoretical RONA-BV trade-off for graded-ND
RESURF with and without VFP-compensation for both lateral and vertical
devices. For ts=1 μm (SYM device) and optimal ND(x) profile, other design
parameters ( tdand ND(0)) are selected to achieve minimum RONA for ideal
BV.
2.5
Application guidelines and results
Using the proposed model, the following guideline for optimizing FP assisted RESURF can be derived:
1. first determine the drift-region length (L) for the desired ideal BV from Eq. (2.19) ;
2. then optimize the lateral BV by grading one of the design parameters according to Eq. (2.14);
3. finally tailor the other device parameters such that: a) the device is not subjected to vertical breakdown (Chapter 2.3.2) or junction breakdown (Chapter2.3.3); and b) the specific on-resistance RONA is
minimized.
2.5.1
Specific on-resistance (R
ONA) optimization
Because of the complex interaction between the different breakdown limit-ing criteria an optimization routine has been developed that incorporates given design parameters (e.g. ND(0), ts, td) for optimizing the RONA-BV
trade-off. Figure2.12shows this for a ts=1 μm device for which the
33 CHAPTER 2. DEVICE DESIGN OPTIMIZA TION
determined. Performing such optimization on a graded-ND device shows
RONA-BV improvements when using negatively-biased VFP compared to
the grounded counterpart (Chapter2.4). An improvement of a factor 5 for lateral and 2 for vertical devices is obtained.
2.5.2
Deviations from optimal design
The device designs treated here have been optimized at the edge of their maximum breakdown conditions. This is however ill advised for real applications since any non-optimal characteristics such as drift doping fluctuation or injected (interface) charge will affect the ideal fields and result in premature breakdown or drastic reliability concerns. For reliable device operation the drain extension is therefore usually designed with longer than required L or thicker td. To improve the understanding to
what extent this is necessary the influence of (charge) non-idealities on optimal fields and general device I-V characteristics has to be analyzed. This is the main topic of interest for all subsequent chapters.
2.6
Conclusion
A mathematical model describing field and potential distributions in dif-ferent configurations of gradient based FP assisted RESURF devices has been presented and verified by TCAD simulations. Using the proposed model, an optimal RONA-BV trade-off can be achieved for both lateral and
CHAPTER
3
I
NTERFACE
C
HARGE AND
E
LECTROSTATICS
Abstract
A systematic study on the effects of arbitrary parasitic charge profiles, such as trapped or fixed charge, on the 2-D potential dis-tribution in the drain extension of reverse-biased (gradient based) field-plate (FP) assisted RESURF devices is presented. Using TCAD device simulations and analytical means the significance of the so-called characteristic or natural length λ is highlighted with respect to the potential distribution and related phenomena in both ideal (virgin) and non-ideal (degraded) drain extensions. Subsequently a novel and easy-to-use charge-response method is introduced that enables cal-culation of the potential distribution for an arbitrary parasitic charge profile once the peak potential and lateral fall-off (∝ λ) caused by a sin-gle unit charge has been determined. This can be used for optimizing and predicting the performance of RESURF power devices, after hot carrier injection.
The core of this chapter was published in IEEE Transactions on Electron Devices, Vol.61, No.8, [3].
INTRODUCTION to failure.
This chapter focuses on devices where the RESURF effect is dominantly induced by field-plates, as found in many SOI or Trench-MOS based tech-nologies [2,33,54,57,66–69]. Figure3.1shows the lateral field distribution and resulting (subthreshold) device characteristics in reverse-bias operation for:
i) a virgin device with ideal RESURF
ii) after degradation by a uniformly distributed interface charge profile iii) after degradation by a Gaussian-shaped interface charge profile with the degraded devices containing interface charge along the drain extension at the Si/SiO2 interface as indicated in Fig. 3.1a.
For the ideal device i) a uniform lateral field and a high breakdown voltage (chapter2) of around 760 V is observed. When interface charge is introduced, in cases ii) and iii), a non-uniform field is obtained resulting in non-ideal I-V curves with reduced breakdown voltages (BV). Since inter-face charge can lead to an electric field increase, hot-carrier-induced charge injection is a reliability concern in RESURFdevices [6,70–72]. Physical un-derstanding and models of the charge induced changes in the electric field are therefore essential for the design of drain extensions that can withstand worst case scenario HCI phenomena. The objectives of this chapter are to provide an intuitive method to study the effect of (non-ideal) interface charge on device characteristics (Fig.3.1b-d), to model this and to clarify the significance of the geometry-related modeling term λ. Except for the physically larger dimensions, the electrostatics in field plate RESURF de-vices are quite similar to that observed in (multi-gate) FD-SOI, FinFETs, nanowires [73] and junctionless transistors [74,75]. This makes many of the analysis techniques and methods described applicable to a variety of device types.
This chapter is outlined as follows. Paragraph3.2focuses on the effect of interface charge on the one-dimensional (1-D) electrostatics along a vertical cross-section of the device. Paragraph3.3introduces the geometry-related length λ, and its impact on the electrostatic device behavior. Paragraph 3.4extends the quasi-two-dimensional (2-D) gradient based FP assisted RESURF model [2, 37] to include interface charge, focuses on how this changes the 2-D electrostatics and how to model these changes for arbitrary Nitdistributions. In paragraph3.5conclusions are drawn.
37 CHAPTER 3. INTERF ACE CHARGE AND ELECTROST A TICS
Figure 3.1: The effect of interface charge on the reverse-bias operation of gradient based FP assisted RESURF structures. a) Schematic half-width cross-section of the device, in which the axis of device symmetry is at y= 0, with interface charge (Qit) indicated; b) Fixed and Gaussian shaped
interface charge profiles (Nit(x) = Qit(x)/q); c) Virgin and degraded
lateral fields; d) Subthreshold I-V and breakdown behavior at the backgate (body) terminal.
